Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T212,T213,T214
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	13686	0	0
DisabledNoTrigBkwd_A	2147483647	716121	0	0
DisabledNoTrigFwd_A	2147483647	1554643612	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13686	0	0
T22	119518	0	0	0
T23	548473	0	0	0
T30	1147798	0	0	0
T31	39542	0	0	0
T46	775764	0	0	0
T48	7777	0	0	0
T49	56893	0	0	0
T72	304642	0	0	0
T73	183132	0	0	0
T75	70923	0	0	0
T93	388546	0	0	0
T178	0	663	0	0
T209	18390	0	0	0
T212	1461	685	0	0
T213	5228	394	0	0
T214	0	1003	0	0
T215	1402	585	0	0
T216	0	956	0	0
T217	0	634	0	0
T218	0	785	0	0
T219	0	436	0	0
T220	0	964	0	0
T221	0	779	0	0
T222	0	231	0	0
T223	0	314	0	0
T224	0	934	0	0
T225	0	413	0	0
T226	0	786	0	0
T227	0	890	0	0
T228	0	1243	0	0
T229	0	470	0	0
T230	0	521	0	0
T231	1721780	0	0	0
T232	1639706	0	0	0
T233	28346	0	0	0
T234	123488	0	0	0
T235	164510	0	0	0
T236	20767	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	716121	0	0
T1	509945	4	0	0
T2	30947	0	0	0
T3	702024	936	0	0
T4	948312	229	0	0
T5	60620	3	0	0
T6	881900	2	0	0
T7	656040	8362	0	0
T8	239302	23	0	0
T13	431060	277	0	0
T14	1472469	4103	0	0
T15	1621486	1625	0	0
T16	0	2603	0	0
T17	198808	21	0	0
T18	160408	0	0	0
T20	0	23	0	0
T21	0	2256	0	0
T43	270906	7	0	0
T44	420698	661	0	0
T45	0	2720	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1554643612	0	0
T1	2039780	1409149	0	0
T2	123788	59649	0	0
T3	1404048	751147	0	0
T4	1264416	976674	0	0
T5	121240	93656	0	0
T6	881900	874476	0	0
T7	656040	751521	0	0
T13	431060	325595	0	0
T17	198808	135458	0	0
T18	160408	65918	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T17
1	1	Covered	T2,T3,T5

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T215,T178,T220
1	1	Covered	T2,T3,T5

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T5,T17

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	697426547	5550	0	0
DisabledNoTrigBkwd_A	697426547	206710	0	0
DisabledNoTrigFwd_A	697426547	369261454	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	5550	0	0
T31	39542	0	0	0
T48	7777	0	0	0
T49	56893	0	0	0
T75	70923	0	0	0
T93	388546	0	0	0
T178	0	663	0	0
T209	18390	0	0	0
T215	1402	585	0	0
T220	0	964	0	0
T221	0	779	0	0
T225	0	413	0	0
T226	0	786	0	0
T227	0	890	0	0
T229	0	470	0	0
T234	123488	0	0	0
T235	164510	0	0	0
T236	20767	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	206710	0	0
T3	351012	358	0	0
T4	316104	0	0	0
T5	30310	3	0	0
T6	220475	0	0	0
T7	164010	2579	0	0
T8	0	13	0	0
T13	107765	1	0	0
T14	490823	1835	0	0
T15	0	906	0	0
T17	49702	18	0	0
T18	40102	0	0	0
T43	90302	7	0	0
T44	0	89	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	369261454	0	0
T1	509945	491279	0	0
T2	30947	2630	0	0
T3	351012	50223	0	0
T4	316104	312470	0	0
T5	30310	2984	0	0
T6	220475	220375	0	0
T7	164010	70211	0	0
T13	107765	107049	0	0
T17	49702	7427	0	0
T18	40102	30995	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T17
1	1	Covered	T2,T3,T17

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T212,T216,T218
1	1	Covered	T2,T3,T17

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T17,T7,T6

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	697426547	2947	0	0
DisabledNoTrigBkwd_A	697426547	172381	0	0
DisabledNoTrigFwd_A	697426547	400050755	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	2947	0	0
T22	119518	0	0	0
T30	573899	0	0	0
T46	387882	0	0	0
T72	304642	0	0	0
T73	91566	0	0	0
T212	1461	685	0	0
T213	2614	0	0	0
T216	0	956	0	0
T218	0	785	0	0
T230	0	521	0	0
T231	860890	0	0	0
T232	819853	0	0	0
T233	14173	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	172381	0	0
T6	220475	2	0	0
T7	164010	2498	0	0
T8	119651	7	0	0
T13	107765	276	0	0
T14	490823	4	0	0
T15	810743	5	0	0
T16	0	1420	0	0
T17	49702	1	0	0
T18	40102	0	0	0
T20	0	10	0	0
T43	90302	0	0	0
T44	420698	0	0	0
T45	0	5	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	400050755	0	0
T1	509945	457717	0	0
T2	30947	11136	0	0
T3	351012	347979	0	0
T4	316104	315490	0	0
T5	30310	30224	0	0
T6	220475	216582	0	0
T7	164010	127971	0	0
T13	107765	3486	0	0
T17	49702	44318	0	0
T18	40102	27926	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T213,T214,T219
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	697426547	2767	0	0
DisabledNoTrigBkwd_A	697426547	169000	0	0
DisabledNoTrigFwd_A	697426547	394460973	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	2767	0	0
T23	548473	0	0	0
T30	573899	0	0	0
T46	387882	0	0	0
T73	91566	0	0	0
T213	2614	394	0	0
T214	0	1003	0	0
T219	0	436	0	0
T224	0	934	0	0
T231	860890	0	0	0
T232	819853	0	0	0
T233	14173	0	0	0
T237	35967	0	0	0
T238	18202	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	169000	0	0
T1	509945	4	0	0
T2	30947	0	0	0
T3	351012	578	0	0
T4	316104	1	0	0
T5	30310	0	0	0
T6	220475	0	0	0
T7	164010	3105	0	0
T13	107765	0	0	0
T14	0	2256	0	0
T15	0	73	0	0
T16	0	1049	0	0
T17	49702	2	0	0
T18	40102	0	0	0
T44	0	175	0	0
T45	0	3	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	394460973	0	0
T1	509945	179191	0	0
T2	30947	19536	0	0
T3	351012	2624	0	0
T4	316104	314724	0	0
T5	30310	30224	0	0
T6	220475	220375	0	0
T7	164010	414449	0	0
T13	107765	107591	0	0
T17	49702	39383	0	0
T18	40102	590	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T17

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T217,T222,T223
1	1	Covered	T2,T4,T17

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T7,T14

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	697426547	2422	0	0
DisabledNoTrigBkwd_A	697426547	168030	0	0
DisabledNoTrigFwd_A	697426547	390870430	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	2422	0	0
T55	144788	0	0	0
T79	63217	0	0	0
T80	150765	0	0	0
T110	147385	0	0	0
T201	25500	0	0	0
T202	42596	0	0	0
T217	3077	634	0	0
T222	0	231	0	0
T223	0	314	0	0
T228	0	1243	0	0
T239	155538	0	0	0
T240	11082	0	0	0
T241	133393	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	168030	0	0
T4	316104	228	0	0
T6	220475	0	0	0
T7	164010	180	0	0
T8	119651	3	0	0
T13	107765	0	0	0
T14	490823	8	0	0
T15	810743	641	0	0
T16	0	134	0	0
T17	49702	0	0	0
T18	40102	0	0	0
T20	0	13	0	0
T21	0	2256	0	0
T43	90302	0	0	0
T44	0	397	0	0
T45	0	2712	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	697426547	390870430	0	0
T1	509945	280962	0	0
T2	30947	26347	0	0
T3	351012	350321	0	0
T4	316104	33990	0	0
T5	30310	30224	0	0
T6	220475	217144	0	0
T7	164010	138890	0	0
T13	107765	107469	0	0
T17	49702	44330	0	0
T18	40102	6407	0	0