SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_ping_timer.u_prim_count_esc_cnt | 100.00 | 100.00 | |||||
tb.dut.u_ping_timer.u_prim_count_cnt | 100.00 | 100.00 | |||||
tb.dut.gen_classes[0].u_accu.u_prim_count | 100.00 | 100.00 | |||||
tb.dut.gen_classes[0].u_esc_timer.u_prim_count | 100.00 | 100.00 | |||||
tb.dut.gen_classes[1].u_accu.u_prim_count | 100.00 | 100.00 | |||||
tb.dut.gen_classes[1].u_esc_timer.u_prim_count | 100.00 | 100.00 | |||||
tb.dut.gen_classes[2].u_accu.u_prim_count | 100.00 | 100.00 | |||||
tb.dut.gen_classes[2].u_esc_timer.u_prim_count | 100.00 | 100.00 | |||||
tb.dut.gen_classes[3].u_accu.u_prim_count | 100.00 | 100.00 | |||||
tb.dut.gen_classes[3].u_esc_timer.u_prim_count | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.46 | 100.00 | 97.30 | 100.00 | 100.00 | 100.00 | u_ping_timer |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.46 | 100.00 | 97.30 | 100.00 | 100.00 | 100.00 | u_ping_timer |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | gen_classes[0].u_accu |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.11 | 100.00 | 95.56 | 100.00 | 100.00 | 100.00 | gen_classes[0].u_esc_timer |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | gen_classes[1].u_accu |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.67 | 100.00 | 93.33 | 100.00 | 100.00 | 100.00 | gen_classes[1].u_esc_timer |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | gen_classes[2].u_accu |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.56 | 100.00 | 97.78 | 100.00 | 100.00 | 100.00 | gen_classes[2].u_esc_timer |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | gen_classes[3].u_accu |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.11 | 100.00 | 95.56 | 100.00 | 100.00 | 100.00 | gen_classes[3].u_esc_timer |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | TOGGLE |
100.00 | 100.00 |
SCORE | TOGGLE |
100.00 | 100.00 |
SCORE | TOGGLE |
100.00 | 100.00 |
SCORE | TOGGLE |
100.00 | 100.00 |
SCORE | TOGGLE |
100.00 | 100.00 |
SCORE | TOGGLE |
100.00 | 100.00 |
Total | Covered | Percent | |
---|---|---|---|
Totals | 10 | 10 | 100.00 |
Total Bits | 110 | 110 | 100.00 |
Total Bits 0->1 | 55 | 55 | 100.00 |
Total Bits 1->0 | 55 | 55 | 100.00 |
Ports | 10 | 10 | 100.00 |
Port Bits | 110 | 110 | 100.00 |
Port Bits 0->1 | 55 | 55 | 100.00 |
Port Bits 1->0 | 55 | 55 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T7,T16,T21 | Yes | T1,T2,T3 | INPUT |
clr_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
set_i | Yes | Yes | T1,T3,T4 | Yes | T1,T3,T4 | INPUT |
set_cnt_i[15:0] | Yes | Yes | T1,T3,T5 | Yes | T1,T3,T5 | INPUT |
incr_en_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
decr_en_i | Yes | Yes | T1,T3,T4 | Yes | T1,T3,T4 | INPUT |
step_i[15:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
commit_i | Unreachable | Unreachable | Unreachable | INPUT | ||
cnt_o[15:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
cnt_after_commit_o[15:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
err_o | Yes | Yes | T10,T11,T12 | Yes | T10,T11,T12 | OUTPUT |
SCORE | TOGGLE |
100.00 | 100.00 |
SCORE | TOGGLE |
100.00 | 100.00 |
SCORE | TOGGLE |
100.00 | 100.00 |
SCORE | TOGGLE |
100.00 | 100.00 |
Total | Covered | Percent | |
---|---|---|---|
Totals | 8 | 8 | 100.00 |
Total Bits | 140 | 140 | 100.00 |
Total Bits 0->1 | 70 | 70 | 100.00 |
Total Bits 1->0 | 70 | 70 | 100.00 |
Ports | 8 | 8 | 100.00 |
Port Bits | 140 | 140 | 100.00 |
Port Bits 0->1 | 70 | 70 | 100.00 |
Port Bits 1->0 | 70 | 70 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T7,T16,T21 | Yes | T1,T2,T3 | INPUT |
clr_i | Yes | Yes | T1,T3,T5 | Yes | T1,T3,T5 | INPUT |
set_i | Yes | Yes | T1,T3,T5 | Yes | T1,T3,T5 | INPUT |
set_cnt_i[31:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
incr_en_i | Yes | Yes | T1,T3,T5 | Yes | T1,T3,T5 | INPUT |
decr_en_i | Unreachable | Unreachable | Unreachable | INPUT | ||
step_i[31:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
commit_i | Unreachable | Unreachable | Unreachable | INPUT | ||
cnt_o[31:0] | Yes | Yes | T1,T3,T5 | Yes | T1,T3,T5 | OUTPUT |
cnt_after_commit_o[31:0] | Yes | Yes | T1,T3,T5 | Yes | T1,T3,T5 | OUTPUT |
err_o | Yes | Yes | T10,T11,T12 | Yes | T10,T11,T12 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 7 | 7 | 100.00 |
Total Bits | 74 | 74 | 100.00 |
Total Bits 0->1 | 37 | 37 | 100.00 |
Total Bits 1->0 | 37 | 37 | 100.00 |
Ports | 7 | 7 | 100.00 |
Port Bits | 74 | 74 | 100.00 |
Port Bits 0->1 | 37 | 37 | 100.00 |
Port Bits 1->0 | 37 | 37 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T7,T16,T21 | Yes | T1,T2,T3 | INPUT |
clr_i | Yes | Yes | T1,T3,T4 | Yes | T1,T3,T4 | INPUT |
set_i | Unreachable | Unreachable | Unreachable | INPUT | ||
set_cnt_i[15:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
incr_en_i | Yes | Yes | T1,T3,T4 | Yes | T1,T3,T4 | INPUT |
decr_en_i | Unreachable | Unreachable | Unreachable | INPUT | ||
step_i[15:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
commit_i | Unreachable | Unreachable | Unreachable | INPUT | ||
cnt_o[15:0] | Yes | Yes | T1,T3,T4 | Yes | T1,T3,T4 | OUTPUT |
cnt_after_commit_o[15:0] | Yes | Yes | T1,T3,T4 | Yes | T1,T3,T4 | OUTPUT |
err_o | Yes | Yes | T10,T11,T12 | Yes | T10,T11,T12 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 8 | 8 | 100.00 |
Total Bits | 106 | 106 | 100.00 |
Total Bits 0->1 | 53 | 53 | 100.00 |
Total Bits 1->0 | 53 | 53 | 100.00 |
Ports | 8 | 8 | 100.00 |
Port Bits | 106 | 106 | 100.00 |
Port Bits 0->1 | 53 | 53 | 100.00 |
Port Bits 1->0 | 53 | 53 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T7,T16,T21 | Yes | T1,T2,T3 | INPUT |
clr_i | Unreachable | Unreachable | Unreachable | INPUT | ||
set_i | Yes | Yes | T1,T3,T4 | Yes | T1,T3,T4 | INPUT |
set_cnt_i[15:0] | Yes | Yes | T1,T3,T5 | Yes | T1,T3,T5 | INPUT |
incr_en_i | Unreachable | Unreachable | Unreachable | INPUT | ||
decr_en_i | Yes | Yes | T1,T3,T4 | Yes | T1,T3,T4 | INPUT |
step_i[15:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
commit_i | Unreachable | Unreachable | Unreachable | INPUT | ||
cnt_o[15:0] | Yes | Yes | T1,T3,T4 | Yes | T1,T3,T4 | OUTPUT |
cnt_after_commit_o[15:0] | Yes | Yes | T1,T3,T4 | Yes | T1,T3,T4 | OUTPUT |
err_o | Yes | Yes | T10,T11,T12 | Yes | T10,T11,T12 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 7 | 7 | 100.00 |
Total Bits | 74 | 74 | 100.00 |
Total Bits 0->1 | 37 | 37 | 100.00 |
Total Bits 1->0 | 37 | 37 | 100.00 |
Ports | 7 | 7 | 100.00 |
Port Bits | 74 | 74 | 100.00 |
Port Bits 0->1 | 37 | 37 | 100.00 |
Port Bits 1->0 | 37 | 37 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T7,T16,T21 | Yes | T1,T2,T3 | INPUT |
clr_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
set_i | Unreachable | Unreachable | Unreachable | INPUT | ||
set_cnt_i[15:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
incr_en_i | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | INPUT |
decr_en_i | Unreachable | Unreachable | Unreachable | INPUT | ||
step_i[15:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
commit_i | Unreachable | Unreachable | Unreachable | INPUT | ||
cnt_o[15:0] | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
cnt_after_commit_o[15:0] | Yes | Yes | T2,T3,T5 | Yes | T2,T3,T5 | OUTPUT |
err_o | Yes | Yes | T10,T11,T12 | Yes | T10,T11,T12 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 8 | 8 | 100.00 |
Total Bits | 140 | 140 | 100.00 |
Total Bits 0->1 | 70 | 70 | 100.00 |
Total Bits 1->0 | 70 | 70 | 100.00 |
Ports | 8 | 8 | 100.00 |
Port Bits | 140 | 140 | 100.00 |
Port Bits 0->1 | 70 | 70 | 100.00 |
Port Bits 1->0 | 70 | 70 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T7,T16,T21 | Yes | T1,T2,T3 | INPUT |
clr_i | Yes | Yes | T3,T5,T17 | Yes | T3,T5,T17 | INPUT |
set_i | Yes | Yes | T3,T5,T17 | Yes | T3,T5,T17 | INPUT |
set_cnt_i[31:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
incr_en_i | Yes | Yes | T3,T5,T17 | Yes | T3,T5,T17 | INPUT |
decr_en_i | Unreachable | Unreachable | Unreachable | INPUT | ||
step_i[31:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
commit_i | Unreachable | Unreachable | Unreachable | INPUT | ||
cnt_o[31:0] | Yes | Yes | T3,T5,T17 | Yes | T3,T5,T17 | OUTPUT |
cnt_after_commit_o[31:0] | Yes | Yes | T3,T5,T17 | Yes | T3,T5,T17 | OUTPUT |
err_o | Yes | Yes | T10,T11,T12 | Yes | T10,T11,T12 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 7 | 7 | 100.00 |
Total Bits | 74 | 74 | 100.00 |
Total Bits 0->1 | 37 | 37 | 100.00 |
Total Bits 1->0 | 37 | 37 | 100.00 |
Ports | 7 | 7 | 100.00 |
Port Bits | 74 | 74 | 100.00 |
Port Bits 0->1 | 37 | 37 | 100.00 |
Port Bits 1->0 | 37 | 37 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T7,T16,T21 | Yes | T1,T2,T3 | INPUT |
clr_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
set_i | Unreachable | Unreachable | Unreachable | INPUT | ||
set_cnt_i[15:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
incr_en_i | Yes | Yes | T2,T3,T17 | Yes | T2,T3,T17 | INPUT |
decr_en_i | Unreachable | Unreachable | Unreachable | INPUT | ||
step_i[15:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
commit_i | Unreachable | Unreachable | Unreachable | INPUT | ||
cnt_o[15:0] | Yes | Yes | T2,T17,T18 | Yes | T2,T3,T17 | OUTPUT |
cnt_after_commit_o[15:0] | Yes | Yes | T2,T17,T18 | Yes | T2,T3,T17 | OUTPUT |
err_o | Yes | Yes | T10,T11,T12 | Yes | T10,T11,T12 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 8 | 8 | 100.00 |
Total Bits | 140 | 140 | 100.00 |
Total Bits 0->1 | 70 | 70 | 100.00 |
Total Bits 1->0 | 70 | 70 | 100.00 |
Ports | 8 | 8 | 100.00 |
Port Bits | 140 | 140 | 100.00 |
Port Bits 0->1 | 70 | 70 | 100.00 |
Port Bits 1->0 | 70 | 70 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T7,T16,T21 | Yes | T1,T2,T3 | INPUT |
clr_i | Yes | Yes | T17,T18,T7 | Yes | T17,T18,T7 | INPUT |
set_i | Yes | Yes | T17,T18,T7 | Yes | T17,T18,T7 | INPUT |
set_cnt_i[31:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
incr_en_i | Yes | Yes | T17,T18,T7 | Yes | T17,T18,T7 | INPUT |
decr_en_i | Unreachable | Unreachable | Unreachable | INPUT | ||
step_i[31:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
commit_i | Unreachable | Unreachable | Unreachable | INPUT | ||
cnt_o[31:0] | Yes | Yes | T17,T18,T7 | Yes | T17,T18,T7 | OUTPUT |
cnt_after_commit_o[31:0] | Yes | Yes | T17,T18,T7 | Yes | T17,T18,T7 | OUTPUT |
err_o | Yes | Yes | T10,T11,T12 | Yes | T10,T11,T12 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 7 | 7 | 100.00 |
Total Bits | 74 | 74 | 100.00 |
Total Bits 0->1 | 37 | 37 | 100.00 |
Total Bits 1->0 | 37 | 37 | 100.00 |
Ports | 7 | 7 | 100.00 |
Port Bits | 74 | 74 | 100.00 |
Port Bits 0->1 | 37 | 37 | 100.00 |
Port Bits 1->0 | 37 | 37 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T7,T16,T21 | Yes | T1,T2,T3 | INPUT |
clr_i | Yes | Yes | T1,T3,T4 | Yes | T1,T3,T4 | INPUT |
set_i | Unreachable | Unreachable | Unreachable | INPUT | ||
set_cnt_i[15:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
incr_en_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
decr_en_i | Unreachable | Unreachable | Unreachable | INPUT | ||
step_i[15:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
commit_i | Unreachable | Unreachable | Unreachable | INPUT | ||
cnt_o[15:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
cnt_after_commit_o[15:0] | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | OUTPUT |
err_o | Yes | Yes | T10,T11,T12 | Yes | T10,T11,T12 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 8 | 8 | 100.00 |
Total Bits | 140 | 140 | 100.00 |
Total Bits 0->1 | 70 | 70 | 100.00 |
Total Bits 1->0 | 70 | 70 | 100.00 |
Ports | 8 | 8 | 100.00 |
Port Bits | 140 | 140 | 100.00 |
Port Bits 0->1 | 70 | 70 | 100.00 |
Port Bits 1->0 | 70 | 70 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T7,T16,T21 | Yes | T1,T2,T3 | INPUT |
clr_i | Yes | Yes | T1,T3,T4 | Yes | T1,T3,T4 | INPUT |
set_i | Yes | Yes | T1,T3,T4 | Yes | T1,T3,T4 | INPUT |
set_cnt_i[31:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
incr_en_i | Yes | Yes | T1,T3,T4 | Yes | T1,T3,T4 | INPUT |
decr_en_i | Unreachable | Unreachable | Unreachable | INPUT | ||
step_i[31:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
commit_i | Unreachable | Unreachable | Unreachable | INPUT | ||
cnt_o[31:0] | Yes | Yes | T1,T3,T4 | Yes | T1,T3,T4 | OUTPUT |
cnt_after_commit_o[31:0] | Yes | Yes | T1,T3,T4 | Yes | T1,T3,T4 | OUTPUT |
err_o | Yes | Yes | T10,T11,T12 | Yes | T10,T11,T12 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 7 | 7 | 100.00 |
Total Bits | 74 | 74 | 100.00 |
Total Bits 0->1 | 37 | 37 | 100.00 |
Total Bits 1->0 | 37 | 37 | 100.00 |
Ports | 7 | 7 | 100.00 |
Port Bits | 74 | 74 | 100.00 |
Port Bits 0->1 | 37 | 37 | 100.00 |
Port Bits 1->0 | 37 | 37 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T7,T16,T21 | Yes | T1,T2,T3 | INPUT |
clr_i | Yes | Yes | T1,T3,T4 | Yes | T1,T3,T4 | INPUT |
set_i | Unreachable | Unreachable | Unreachable | INPUT | ||
set_cnt_i[15:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
incr_en_i | Yes | Yes | T2,T4,T17 | Yes | T2,T4,T17 | INPUT |
decr_en_i | Unreachable | Unreachable | Unreachable | INPUT | ||
step_i[15:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
commit_i | Unreachable | Unreachable | Unreachable | INPUT | ||
cnt_o[15:0] | Yes | Yes | T2,T4,T17 | Yes | T2,T4,T17 | OUTPUT |
cnt_after_commit_o[15:0] | Yes | Yes | T2,T4,T17 | Yes | T2,T4,T17 | OUTPUT |
err_o | Yes | Yes | T10,T11,T12 | Yes | T10,T11,T12 | OUTPUT |
Total | Covered | Percent | |
---|---|---|---|
Totals | 8 | 8 | 100.00 |
Total Bits | 140 | 140 | 100.00 |
Total Bits 0->1 | 70 | 70 | 100.00 |
Total Bits 1->0 | 70 | 70 | 100.00 |
Ports | 8 | 8 | 100.00 |
Port Bits | 140 | 140 | 100.00 |
Port Bits 0->1 | 70 | 70 | 100.00 |
Port Bits 1->0 | 70 | 70 | 100.00 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i | Yes | Yes | T1,T2,T3 | Yes | T1,T2,T3 | INPUT |
rst_ni | Yes | Yes | T7,T16,T21 | Yes | T1,T2,T3 | INPUT |
clr_i | Yes | Yes | T4,T17,T18 | Yes | T4,T17,T18 | INPUT |
set_i | Yes | Yes | T4,T17,T18 | Yes | T4,T17,T18 | INPUT |
set_cnt_i[31:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
incr_en_i | Yes | Yes | T4,T17,T18 | Yes | T4,T17,T18 | INPUT |
decr_en_i | Unreachable | Unreachable | Unreachable | INPUT | ||
step_i[31:0] | Unreachable | Unreachable | Unreachable | INPUT | ||
commit_i | Unreachable | Unreachable | Unreachable | INPUT | ||
cnt_o[31:0] | Yes | Yes | T4,T17,T18 | Yes | T4,T17,T18 | OUTPUT |
cnt_after_commit_o[31:0] | Yes | Yes | T4,T17,T18 | Yes | T4,T17,T18 | OUTPUT |
err_o | Yes | Yes | T10,T11,T12 | Yes | T10,T11,T12 | OUTPUT |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |