Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.30	100.00	100.00	89.19			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.07	100.00		97.20			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	89.19			89.19

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.95	100.00	100.00	83.78			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.07	100.00		97.20			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	83.78			83.78

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.62	100.00	100.00	86.49			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.07	100.00		97.20			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	86.49			86.49

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.30	100.00	100.00	89.19			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.07	100.00		97.20			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	89.19			89.19

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T24,T215,T216
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	12717	0	0
DisabledNoTrigBkwd_A	2147483647	772829	0	0
DisabledNoTrigFwd_A	2147483647	1586883079	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	12717	0	0
T6	22370	0	0	0
T8	782501	0	0	0
T9	298872	0	0	0
T24	3104	822	0	0
T25	33285	0	0	0
T26	84577	0	0	0
T42	11170	0	0	0
T43	92058	0	0	0
T63	595981	0	0	0
T77	36402	0	0	0
T83	14872	0	0	0
T195	0	464	0	0
T215	0	1272	0	0
T216	1370	625	0	0
T217	0	1232	0	0
T218	0	251	0	0
T219	0	764	0	0
T220	0	923	0	0
T221	0	180	0	0
T222	0	440	0	0
T223	0	833	0	0
T224	0	927	0	0
T225	0	587	0	0
T226	0	1276	0	0
T227	0	272	0	0
T228	935	185	0	0
T229	0	292	0	0
T230	0	780	0	0
T231	0	259	0	0
T232	0	333	0	0
T233	7212	0	0	0
T234	6638	0	0	0
T235	16377	0	0	0
T236	724336	0	0	0
T237	155647	0	0	0
T238	405788	0	0	0
T239	147776	0	0	0
T240	335227	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	772829	0	0
T1	1605112	2900	0	0
T2	78268	0	0	0
T3	650088	2375	0	0
T4	184152	0	0	0
T5	2509284	3684	0	0
T8	0	271	0	0
T9	0	1574	0	0
T10	122476	6	0	0
T11	80612	0	0	0
T14	0	1387	0	0
T15	0	14	0	0
T16	0	296	0	0
T20	0	8	0	0
T22	130568	12	0	0
T23	69728	0	0	0
T24	12416	9	0	0
T26	0	16	0	0
T27	0	444	0	0
T42	0	5	0	0
T43	0	59	0	0
T44	0	69	0	0
T45	0	12	0	0
T46	0	8	0	0
T47	0	28	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1586883079	0	0
T1	1605112	1151190	0	0
T2	78268	39210	0	0
T3	650088	486948	0	0
T4	184152	81764	0	0
T5	2509284	1569851	0	0
T10	122476	92327	0	0
T11	80612	58468	0	0
T22	130568	86892	0	0
T23	69728	51820	0	0
T24	12416	8639	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T24,T215,T222
1	1	Covered	T1,T2,T5

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T10

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	694166456	6429	0	0
DisabledNoTrigBkwd_A	694166456	221805	0	0
DisabledNoTrigFwd_A	694166456	339652113	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	6429	0	0
T6	22370	0	0	0
T8	782501	0	0	0
T9	298872	0	0	0
T24	3104	822	0	0
T25	33285	0	0	0
T26	84577	0	0	0
T42	11170	0	0	0
T43	92058	0	0	0
T77	36402	0	0	0
T83	14872	0	0	0
T215	0	1272	0	0
T222	0	440	0	0
T223	0	833	0	0
T224	0	927	0	0
T225	0	587	0	0
T226	0	1276	0	0
T227	0	272	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	221805	0	0
T1	401278	45	0	0
T2	19567	0	0	0
T3	162522	0	0	0
T4	46038	0	0	0
T5	627321	1752	0	0
T9	0	370	0	0
T10	30619	6	0	0
T11	20153	0	0	0
T22	32642	0	0	0
T23	17432	0	0	0
T24	3104	9	0	0
T26	0	9	0	0
T27	0	419	0	0
T42	0	5	0	0
T43	0	59	0	0
T44	0	69	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	339652113	0	0
T1	401278	371217	0	0
T2	19567	18485	0	0
T3	162522	162515	0	0
T4	46038	20441	0	0
T5	627321	233138	0	0
T10	30619	728	0	0
T11	20153	20053	0	0
T22	32642	32576	0	0
T23	17432	9409	0	0
T24	3104	2136	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T11
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T228
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	694166456	185	0	0
DisabledNoTrigBkwd_A	694166456	150394	0	0
DisabledNoTrigFwd_A	694166456	431889312	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	185	0	0
T63	595981	0	0	0
T228	935	185	0	0
T233	7212	0	0	0
T234	6638	0	0	0
T235	16377	0	0	0
T236	724336	0	0	0
T237	155647	0	0	0
T238	405788	0	0	0
T239	147776	0	0	0
T240	335227	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	150394	0	0
T1	401278	228	0	0
T2	19567	0	0	0
T3	162522	2363	0	0
T4	46038	0	0	0
T5	627321	466	0	0
T8	0	269	0	0
T9	0	1150	0	0
T10	30619	0	0	0
T11	20153	0	0	0
T16	0	296	0	0
T20	0	3	0	0
T22	32642	0	0	0
T23	17432	0	0	0
T24	3104	0	0	0
T27	0	7	0	0
T45	0	3	0	0
T47	0	23	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	431889312	0	0
T1	401278	310697	0	0
T2	19567	18485	0	0
T3	162522	586	0	0
T4	46038	20441	0	0
T5	627321	502558	0	0
T10	30619	30533	0	0
T11	20153	18560	0	0
T22	32642	32576	0	0
T23	17432	11680	0	0
T24	3104	2157	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T11
1	0	Covered	T1,T3,T11
1	1	Covered	T1,T2,T11

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T216,T221
1	1	Covered	T1,T2,T11

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T22

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	694166456	805	0	0
DisabledNoTrigBkwd_A	694166456	167026	0	0
DisabledNoTrigFwd_A	694166456	414179997	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	805	0	0
T35	140627	0	0	0
T52	901777	0	0	0
T85	7462	0	0	0
T109	670998	0	0	0
T115	760981	0	0	0
T216	1370	625	0	0
T221	0	180	0	0
T241	125897	0	0	0
T242	248395	0	0	0
T243	27628	0	0	0
T244	27857	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	167026	0	0
T1	401278	2587	0	0
T2	19567	0	0	0
T3	162522	0	0	0
T4	46038	0	0	0
T5	627321	964	0	0
T9	0	20	0	0
T10	30619	0	0	0
T11	20153	0	0	0
T14	0	1387	0	0
T20	0	5	0	0
T22	32642	1	0	0
T23	17432	0	0	0
T24	3104	0	0	0
T26	0	7	0	0
T27	0	6	0	0
T46	0	3	0	0
T47	0	5	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	414179997	0	0
T1	401278	119308	0	0
T2	19567	604	0	0
T3	162522	162515	0	0
T4	46038	20441	0	0
T5	627321	294462	0	0
T10	30619	30533	0	0
T11	20153	3967	0	0
T22	32642	19608	0	0
T23	17432	13351	0	0
T24	3104	2169	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T217,T218,T219
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	694166456	5298	0	0
DisabledNoTrigBkwd_A	694166456	233604	0	0
DisabledNoTrigFwd_A	694166456	401161657	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	5298	0	0
T53	53186	0	0	0
T96	715836	0	0	0
T117	689411	0	0	0
T195	0	464	0	0
T217	5183	1232	0	0
T218	3583	251	0	0
T219	0	764	0	0
T220	0	923	0	0
T229	0	292	0	0
T230	0	780	0	0
T231	0	259	0	0
T232	0	333	0	0
T245	61596	0	0	0
T246	38312	0	0	0
T247	2751	0	0	0
T248	28255	0	0	0
T249	826571	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	233604	0	0
T1	401278	40	0	0
T2	19567	0	0	0
T3	162522	12	0	0
T4	46038	0	0	0
T5	627321	502	0	0
T8	0	2	0	0
T9	0	34	0	0
T10	30619	0	0	0
T11	20153	0	0	0
T15	0	14	0	0
T22	32642	11	0	0
T23	17432	0	0	0
T24	3104	0	0	0
T27	0	12	0	0
T45	0	9	0	0
T46	0	5	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	401161657	0	0
T1	401278	349968	0	0
T2	19567	1636	0	0
T3	162522	161332	0	0
T4	46038	20441	0	0
T5	627321	539693	0	0
T10	30619	30533	0	0
T11	20153	15888	0	0
T22	32642	2132	0	0
T23	17432	17380	0	0
T24	3104	2177	0	0