Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.41	100.00	93.33	37.14	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.07	100.00		97.20			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	37.14			37.14
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.41	100.00	93.33	37.14	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.07	100.00		97.20			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	37.14			37.14
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.41	100.00	93.33	37.14	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.07	100.00		97.20			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	37.14			37.14
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.78	100.00	95.56	37.14	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.07	100.00		97.20			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	37.14			37.14
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T5

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T11
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T1,T2,T11
1	1	1	Covered	T1,T2,T11

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T11
0	1	Covered	T1,T11,T5
1	0	Covered	T9,T21,T28

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T11
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T9,T21,T28

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T11
1	0	Covered	T29
1	1	Covered	T1,T11,T5

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T3,T11

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T11
1	Covered	T1,T5,T22

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T11
1	Covered	T1,T3,T5

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T11
1	Covered	T1,T3,T5

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T6,T7

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T3,T11

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T5,T23

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T3,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T3,T5

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T4,T6,T7
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T3,T11
Phase1St	193	Covered	T1,T3,T11
Phase2St	210	Covered	T1,T3,T11
Phase3St	228	Covered	T1,T3,T11
TerminalSt	244	Covered	T1,T3,T11
TimeoutSt	154	Covered	T1,T2,T11

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	279	Covered	T4,T6,T7
IdleSt->Phase0St	147	Covered	T1,T3,T5
IdleSt->TimeoutSt	154	Covered	T1,T2,T11
Phase0St->FsmErrorSt	279	Not Covered
Phase0St->IdleSt	189	Covered	T1,T28,T30
Phase0St->Phase1St	193	Covered	T1,T3,T11
Phase1St->FsmErrorSt	279	Not Covered
Phase1St->IdleSt	206	Covered	T31,T32,T33
Phase1St->Phase2St	210	Covered	T1,T3,T11
Phase2St->FsmErrorSt	279	Not Covered
Phase2St->IdleSt	224	Covered	T1,T27,T34
Phase2St->Phase3St	228	Covered	T1,T3,T11
Phase3St->FsmErrorSt	279	Not Covered
Phase3St->IdleSt	240	Covered	T35,T36,T37
Phase3St->TerminalSt	244	Covered	T1,T3,T11
TerminalSt->FsmErrorSt	279	Not Covered
TerminalSt->IdleSt	256	Covered	T1,T3,T5
TimeoutSt->FsmErrorSt	279	Not Covered
TimeoutSt->IdleSt	176	Covered	T1,T2,T11
TimeoutSt->Phase0St	167	Covered	T1,T11,T5

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T11
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T11,T5
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T11
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T11
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T28,T38
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T11
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T11
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T31,T32,T33
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T11
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T11
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T27,T34
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T11
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T11
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T36,T37,T39
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T11
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T11
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T3,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T11
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T7
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1280	0	0
CheckAccumTrig0_A	2147483647	2365	0	0
CheckAccumTrig1_A	2147483647	105	0	0
CheckClr_A	2147483647	1096	0	0
CheckEn_A	2147483647	1272033001	0	0
CheckPhase0_A	2147483647	2681	0	0
CheckPhase1_A	2147483647	2634	0	0
CheckPhase2_A	2147483647	2584	0	0
CheckPhase3_A	2147483647	2522	0	0
CheckTimeout0_A	2147483647	4440	0	0
CheckTimeoutSt1_A	2147483647	483242	0	0
CheckTimeoutSt2_A	2147483647	4076	0	0
CheckTimeoutStTrig_A	2147483647	254	0	0
ErrorStAllEscAsserted_A	2147483647	6361	0	0
ErrorStIsTerminal_A	2147483647	5281	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1280	0	0
T4	184152	269	0	0
T5	2509284	0	0	0
T6	0	160	0	0
T7	0	282	0	0
T10	122476	0	0	0
T11	80612	0	0	0
T22	130568	0	0	0
T23	69728	0	0	0
T24	12416	0	0	0
T25	133140	0	0	0
T26	338308	0	0	0
T40	0	285	0	0
T41	0	284	0	0
T42	44680	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2365	0	0
T1	1605112	15	0	0
T2	78268	0	0	0
T3	650088	2	0	0
T4	184152	0	0	0
T5	2509284	20	0	0
T8	0	1	0	0
T9	0	4	0	0
T10	122476	1	0	0
T11	80612	0	0	0
T14	0	1	0	0
T16	0	2	0	0
T20	0	2	0	0
T21	0	5	0	0
T22	130568	1	0	0
T23	69728	0	0	0
T24	12416	1	0	0
T26	0	1	0	0
T27	0	14	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	105	0	0
T6	22370	0	0	0
T9	298872	1	0	0
T14	100936	0	0	0
T15	101935	0	0	0
T17	528881	0	0	0
T21	350908	1	0	0
T27	542254	0	0	0
T28	642572	3	0	0
T31	0	2	0	0
T33	0	1	0	0
T34	111824	0	0	0
T44	31987	0	0	0
T45	56744	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	3	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	60974	0	0	0
T66	41249	0	0	0
T67	39521	0	0	0
T68	4365	0	0	0
T69	185276	0	0	0
T70	109939	0	0	0
T71	16875	0	0	0
T72	468731	0	0	0
T73	469747	0	0	0
T74	77197	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1096	0	0
T1	1203834	8	0	0
T2	58701	0	0	0
T3	650088	2	0	0
T4	184152	0	0	0
T5	2509284	6	0	0
T9	0	1	0	0
T10	122476	0	0	0
T11	80612	0	0	0
T16	0	3	0	0
T21	0	7	0	0
T22	130568	0	0	0
T23	69728	0	0	0
T24	12416	0	0	0
T25	33285	0	0	0
T26	84577	2	0	0
T27	0	8	0	0
T28	0	8	0	0
T31	0	7	0	0
T34	0	3	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T75	0	8	0	0
T76	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1272033001	0	0
T1	1605112	1825183	0	0
T2	78268	39208	0	0
T3	650088	328103	0	0
T4	1752	1408	0	0
T5	2509284	1378388	0	0
T10	122476	92324	0	0
T11	80612	58465	0	0
T22	130568	76763	0	0
T23	69728	41655	0	0
T24	12416	8639	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2681	0	0
T1	1605112	19	0	0
T2	78268	0	0	0
T3	650088	4	0	0
T4	184152	0	0	0
T5	2509284	24	0	0
T8	0	2	0	0
T9	0	6	0	0
T10	122476	1	0	0
T11	80612	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	2	0	0
T22	130568	2	0	0
T23	69728	1	0	0
T24	12416	1	0	0
T26	0	5	0	0
T27	0	17	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	3	0	0
T47	0	2	0	0
T67	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2634	0	0
T1	1605112	19	0	0
T2	78268	0	0	0
T3	650088	4	0	0
T4	184152	0	0	0
T5	2509284	24	0	0
T8	0	2	0	0
T9	0	6	0	0
T10	122476	1	0	0
T11	80612	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	2	0	0
T22	130568	2	0	0
T23	69728	1	0	0
T24	12416	1	0	0
T26	0	5	0	0
T27	0	17	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	3	0	0
T47	0	2	0	0
T67	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2584	0	0
T1	1605112	18	0	0
T2	78268	0	0	0
T3	650088	4	0	0
T4	184152	0	0	0
T5	2509284	24	0	0
T8	0	2	0	0
T9	0	6	0	0
T10	122476	1	0	0
T11	80612	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	2	0	0
T22	130568	2	0	0
T23	69728	1	0	0
T24	12416	1	0	0
T26	0	5	0	0
T27	0	15	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	3	0	0
T47	0	2	0	0
T67	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2522	0	0
T1	1605112	18	0	0
T2	78268	0	0	0
T3	650088	4	0	0
T4	184152	0	0	0
T5	2509284	24	0	0
T8	0	2	0	0
T9	0	6	0	0
T10	122476	1	0	0
T11	80612	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	2	0	0
T22	130568	2	0	0
T23	69728	1	0	0
T24	12416	1	0	0
T26	0	5	0	0
T27	0	15	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	3	0	0
T47	0	2	0	0
T67	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4440	0	0
T1	1605112	49	0	0
T2	78268	7	0	0
T3	650088	0	0	0
T4	184152	0	0	0
T5	2509284	3	0	0
T9	0	3	0	0
T10	122476	2	0	0
T11	80612	6	0	0
T21	0	8	0	0
T22	130568	0	0	0
T23	69728	2	0	0
T24	12416	0	0	0
T25	0	7	0	0
T26	0	5	0	0
T27	0	1	0	0
T28	0	2	0	0
T45	0	6	0	0
T46	0	1	0	0
T47	0	2	0	0
T65	0	14	0	0
T67	0	22	0	0
T68	0	1	0	0
T77	0	29	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	483242	0	0
T1	1605112	9020	0	0
T2	78268	702	0	0
T3	650088	0	0	0
T4	184152	0	0	0
T5	2509284	623	0	0
T9	0	453	0	0
T10	122476	88	0	0
T11	80612	783	0	0
T21	0	1060	0	0
T22	130568	0	0	0
T23	69728	345	0	0
T24	12416	0	0	0
T25	0	1022	0	0
T26	0	2320	0	0
T27	0	500	0	0
T28	0	574	0	0
T45	0	4652	0	0
T46	0	217	0	0
T47	0	22	0	0
T65	0	2825	0	0
T67	0	2629	0	0
T68	0	72	0	0
T77	0	2230	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4076	0	0
T1	1605112	47	0	0
T2	78268	7	0	0
T3	650088	0	0	0
T4	184152	0	0	0
T5	2509284	2	0	0
T9	0	2	0	0
T10	122476	2	0	0
T11	80612	5	0	0
T21	0	20	0	0
T22	130568	0	0	0
T23	69728	1	0	0
T24	12416	0	0	0
T25	0	7	0	0
T26	0	1	0	0
T28	0	2	0	0
T31	0	4	0	0
T45	0	4	0	0
T46	0	1	0	0
T47	0	1	0	0
T65	0	14	0	0
T67	0	21	0	0
T68	0	1	0	0
T75	0	11	0	0
T77	0	29	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	254	0	0
T1	401278	2	0	0
T2	19567	0	0	0
T3	162522	0	0	0
T4	46038	0	0	0
T5	1881963	1	0	0
T6	22370	0	0	0
T8	782501	0	0	0
T9	298872	0	0	0
T10	91857	0	0	0
T11	40306	1	0	0
T14	100936	0	0	0
T21	0	1	0	0
T22	97926	0	0	0
T23	52296	1	0	0
T24	9312	0	0	0
T25	66570	0	0	0
T26	253731	3	0	0
T27	0	1	0	0
T28	0	1	0	0
T31	0	2	0	0
T33	0	2	0	0
T42	33510	0	0	0
T43	276174	0	0	0
T44	31987	0	0	0
T45	0	2	0	0
T47	0	1	0	0
T51	0	2	0	0
T52	0	3	0	0
T67	0	1	0	0
T75	0	9	0	0
T77	72804	0	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	2	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	14872	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6361	0	0
T4	184152	1391	0	0
T5	2509284	0	0	0
T6	0	670	0	0
T7	0	1390	0	0
T10	122476	0	0	0
T11	80612	0	0	0
T22	130568	0	0	0
T23	69728	0	0	0
T24	12416	0	0	0
T25	133140	0	0	0
T26	338308	0	0	0
T40	0	1442	0	0
T41	0	1468	0	0
T42	44680	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5281	0	0
T4	184152	1151	0	0
T5	2509284	0	0	0
T6	0	550	0	0
T7	0	1150	0	0
T10	122476	0	0	0
T11	80612	0	0	0
T22	130568	0	0	0
T23	69728	0	0	0
T24	12416	0	0	0
T25	133140	0	0	0
T26	338308	0	0	0
T40	0	1202	0	0
T41	0	1228	0	0
T42	44680	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1605112	1604712	0	0
T2	78268	78052	0	0
T3	650088	650060	0	0
T4	184152	81764	0	0
T5	2509284	2509232	0	0
T10	122476	122132	0	0
T11	80612	80212	0	0
T22	130568	130304	0	0
T23	69728	69520	0	0
T24	12416	12168	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T5,T10
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T10

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T5,T10

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T5
1	0	1	Covered	T5,T24,T9
1	1	0	Covered	T1,T2,T11
1	1	1	Covered	T1,T5,T10

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T10
0	1	Covered	T5,T27,T45
1	0	Covered	T21,T28,T31

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T5,T10
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T21,T28,T31

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T10
1	0	Not Covered
1	1	Covered	T5,T27,T45

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T10
1	Covered	T1,T5,T24

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T24
1	Covered	T5,T10,T44

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T10
1	Covered	T1,T5,T27

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T10
1	Covered	T43,T44,T27

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T6,T7

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T5,T10

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T5,T24,T26

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T5,T24

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T5,T10

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T4,T6,T7
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T5,T10
Phase1St	193	Covered	T1,T5,T10
Phase2St	210	Covered	T1,T5,T10
Phase3St	228	Covered	T1,T5,T10
TerminalSt	244	Covered	T1,T5,T10
TimeoutSt	154	Covered	T1,T5,T10

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T4,T6,T7
IdleSt->Phase0St	147	Covered	T1,T5,T10
IdleSt->TimeoutSt	154	Covered	T1,T5,T10
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T28,T84,T55
Phase0St->Phase1St	193	Covered	T1,T5,T10
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T31,T85,T57
Phase1St->Phase2St	210	Covered	T1,T5,T10
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T1,T27,T50
Phase2St->Phase3St	228	Covered	T1,T5,T10
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T35,T36,T39
Phase3St->TerminalSt	244	Covered	T1,T5,T10
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T1,T5,T43
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T1,T5,T10
TimeoutSt->Phase0St	167	Covered	T5,T27,T45

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T10
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T10
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T27,T45
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T10
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T10
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T28,T84,T59
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T5,T10
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T5,T10
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T31,T85,T57
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T5,T10
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T5,T10
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T27,T50
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T5,T10
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T5,T10
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T36,T39,T86
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T5,T10
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T5,T10
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T5,T43,T44
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T5,T10
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T7
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	694166456	310	0	0
CheckAccumTrig0_A	694166456	906	0	0
CheckAccumTrig1_A	694166456	51	0	0
CheckClr_A	694166456	460	0	0
CheckEn_A	693902987	259115194	0	0
CheckPhase0_A	694166456	996	0	0
CheckPhase1_A	694166456	975	0	0
CheckPhase2_A	694166456	956	0	0
CheckPhase3_A	694166456	932	0	0
CheckTimeout0_A	694166456	1508	0	0
CheckTimeoutSt1_A	694166456	147037	0	0
CheckTimeoutSt2_A	694166456	1396	0	0
CheckTimeoutStTrig_A	694166456	61	0	0
ErrorStAllEscAsserted_A	694166456	1580	0	0
ErrorStIsTerminal_A	694166456	1310	0	0
u_state_regs_A	694166456	693980546	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	310	0	0
T4	46038	66	0	0
T5	627321	0	0	0
T6	0	34	0	0
T7	0	86	0	0
T10	30619	0	0	0
T11	20153	0	0	0
T22	32642	0	0	0
T23	17432	0	0	0
T24	3104	0	0	0
T25	33285	0	0	0
T26	84577	0	0	0
T40	0	68	0	0
T41	0	56	0	0
T42	11170	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	906	0	0
T1	401278	2	0	0
T2	19567	0	0	0
T3	162522	0	0	0
T4	46038	0	0	0
T5	627321	7	0	0
T9	0	1	0	0
T10	30619	1	0	0
T11	20153	0	0	0
T22	32642	0	0	0
T23	17432	0	0	0
T24	3104	1	0	0
T26	0	1	0	0
T27	0	10	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	51	0	0
T17	528881	0	0	0
T21	350908	1	0	0
T28	0	1	0	0
T31	0	1	0	0
T34	111824	0	0	0
T49	0	1	0	0
T50	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T57	0	2	0	0
T58	0	1	0	0
T68	4365	0	0	0
T69	185276	0	0	0
T70	109939	0	0	0
T71	16875	0	0	0
T72	468731	0	0	0
T73	469747	0	0	0
T74	77197	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	460	0	0
T1	401278	1	0	0
T2	19567	0	0	0
T3	162522	0	0	0
T4	46038	0	0	0
T5	627321	2	0	0
T10	30619	0	0	0
T11	20153	0	0	0
T16	0	2	0	0
T21	0	1	0	0
T22	32642	0	0	0
T23	17432	0	0	0
T24	3104	0	0	0
T27	0	7	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T71	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693902987	259115194	0	0
T1	401278	371216	0	0
T2	19567	18484	0	0
T3	162522	162515	0	0
T4	438	352	0	0
T5	627321	191859	0	0
T10	30619	728	0	0
T11	20153	20052	0	0
T22	32642	32575	0	0
T23	17432	9408	0	0
T24	3104	2136	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	996	0	0
T1	401278	2	0	0
T2	19567	0	0	0
T3	162522	0	0	0
T4	46038	0	0	0
T5	627321	8	0	0
T9	0	1	0	0
T10	30619	1	0	0
T11	20153	0	0	0
T22	32642	0	0	0
T23	17432	0	0	0
T24	3104	1	0	0
T26	0	1	0	0
T27	0	11	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	975	0	0
T1	401278	2	0	0
T2	19567	0	0	0
T3	162522	0	0	0
T4	46038	0	0	0
T5	627321	8	0	0
T9	0	1	0	0
T10	30619	1	0	0
T11	20153	0	0	0
T22	32642	0	0	0
T23	17432	0	0	0
T24	3104	1	0	0
T26	0	1	0	0
T27	0	11	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	956	0	0
T1	401278	1	0	0
T2	19567	0	0	0
T3	162522	0	0	0
T4	46038	0	0	0
T5	627321	8	0	0
T9	0	1	0	0
T10	30619	1	0	0
T11	20153	0	0	0
T22	32642	0	0	0
T23	17432	0	0	0
T24	3104	1	0	0
T26	0	1	0	0
T27	0	9	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	932	0	0
T1	401278	1	0	0
T2	19567	0	0	0
T3	162522	0	0	0
T4	46038	0	0	0
T5	627321	8	0	0
T9	0	1	0	0
T10	30619	1	0	0
T11	20153	0	0	0
T22	32642	0	0	0
T23	17432	0	0	0
T24	3104	1	0	0
T26	0	1	0	0
T27	0	9	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	1508	0	0
T1	401278	15	0	0
T2	19567	0	0	0
T3	162522	0	0	0
T4	46038	0	0	0
T5	627321	3	0	0
T10	30619	2	0	0
T11	20153	0	0	0
T22	32642	0	0	0
T23	17432	0	0	0
T24	3104	0	0	0
T27	0	1	0	0
T45	0	4	0	0
T46	0	1	0	0
T47	0	1	0	0
T65	0	7	0	0
T67	0	7	0	0
T77	0	6	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	147037	0	0
T1	401278	2667	0	0
T2	19567	0	0	0
T3	162522	0	0	0
T4	46038	0	0	0
T5	627321	623	0	0
T10	30619	88	0	0
T11	20153	0	0	0
T22	32642	0	0	0
T23	17432	0	0	0
T24	3104	0	0	0
T27	0	500	0	0
T45	0	3273	0	0
T46	0	217	0	0
T47	0	15	0	0
T65	0	1398	0	0
T67	0	826	0	0
T77	0	497	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	1396	0	0
T1	401278	15	0	0
T2	19567	0	0	0
T3	162522	0	0	0
T4	46038	0	0	0
T5	627321	2	0	0
T10	30619	2	0	0
T11	20153	0	0	0
T21	0	9	0	0
T22	32642	0	0	0
T23	17432	0	0	0
T24	3104	0	0	0
T45	0	3	0	0
T46	0	1	0	0
T47	0	1	0	0
T65	0	7	0	0
T67	0	7	0	0
T77	0	6	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	61	0	0
T5	627321	1	0	0
T10	30619	0	0	0
T22	32642	0	0	0
T23	17432	0	0	0
T24	3104	0	0	0
T25	33285	0	0	0
T26	84577	0	0	0
T27	0	1	0	0
T33	0	1	0	0
T42	11170	0	0	0
T43	92058	0	0	0
T45	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T75	0	1	0	0
T77	36402	0	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	1580	0	0
T4	46038	362	0	0
T5	627321	0	0	0
T6	0	172	0	0
T7	0	367	0	0
T10	30619	0	0	0
T11	20153	0	0	0
T22	32642	0	0	0
T23	17432	0	0	0
T24	3104	0	0	0
T25	33285	0	0	0
T26	84577	0	0	0
T40	0	342	0	0
T41	0	337	0	0
T42	11170	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	1310	0	0
T4	46038	302	0	0
T5	627321	0	0	0
T6	0	142	0	0
T7	0	307	0	0
T10	30619	0	0	0
T11	20153	0	0	0
T22	32642	0	0	0
T23	17432	0	0	0
T24	3104	0	0	0
T25	33285	0	0	0
T26	84577	0	0	0
T40	0	282	0	0
T41	0	277	0	0
T42	11170	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	693980546	0	0
T1	401278	401178	0	0
T2	19567	19513	0	0
T3	162522	162515	0	0
T4	46038	20441	0	0
T5	627321	627308	0	0
T10	30619	30533	0	0
T11	20153	20053	0	0
T22	32642	32576	0	0
T23	17432	17380	0	0
T24	3104	3042	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T3,T11
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T11

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T5

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T11
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T1,T2,T11
1	1	1	Covered	T1,T11,T25

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T25
0	1	Covered	T1,T67,T21
1	0	Covered	T9,T31,T51

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T11,T25
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T9,T31,T51

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T25
1	0	Not Covered
1	1	Covered	T1,T67,T21

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T3,T5

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T9,T27,T47

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T5,T9

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T3,T8

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T6,T7

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T3,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T5,T8

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T3,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T3,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T4,T6,T7
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T3,T5
Phase1St	193	Covered	T1,T3,T5
Phase2St	210	Covered	T1,T3,T5
Phase3St	228	Covered	T1,T3,T5
TerminalSt	244	Covered	T1,T3,T5
TimeoutSt	154	Covered	T1,T11,T25

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T4,T6,T7
IdleSt->Phase0St	147	Covered	T1,T3,T5
IdleSt->TimeoutSt	154	Covered	T1,T11,T25
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T30,T87,T88
Phase0St->Phase1St	193	Covered	T1,T3,T5
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T32,T33,T89
Phase1St->Phase2St	210	Covered	T1,T3,T5
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T51,T90,T91
Phase2St->Phase3St	228	Covered	T1,T3,T5
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T90,T92,T93
Phase3St->TerminalSt	244	Covered	T1,T3,T5
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T1,T3,T5
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T1,T11,T25
TimeoutSt->Phase0St	167	Covered	T1,T9,T67

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T11,T25
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T9,T67
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T11,T25
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T11,T25
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T30,T87,T61
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T32,T33,T89
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T51,T90,T91
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T90,T92,T93
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T3,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T7
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	694166456	308	0	0
CheckAccumTrig0_A	694166456	426	0	0
CheckAccumTrig1_A	694166456	12	0	0
CheckClr_A	694166456	153	0	0
CheckEn_A	693902987	349491710	0	0
CheckPhase0_A	694166456	490	0	0
CheckPhase1_A	694166456	483	0	0
CheckPhase2_A	694166456	475	0	0
CheckPhase3_A	694166456	466	0	0
CheckTimeout0_A	694166456	1064	0	0
CheckTimeoutSt1_A	694166456	117998	0	0
CheckTimeoutSt2_A	694166456	993	0	0
CheckTimeoutStTrig_A	694166456	57	0	0
ErrorStAllEscAsserted_A	694166456	1601	0	0
ErrorStIsTerminal_A	694166456	1331	0	0
u_state_regs_A	694166456	693980546	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	308	0	0
T4	46038	71	0	0
T5	627321	0	0	0
T6	0	39	0	0
T7	0	56	0	0
T10	30619	0	0	0
T11	20153	0	0	0
T22	32642	0	0	0
T23	17432	0	0	0
T24	3104	0	0	0
T25	33285	0	0	0
T26	84577	0	0	0
T40	0	59	0	0
T41	0	83	0	0
T42	11170	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	426	0	0
T1	401278	5	0	0
T2	19567	0	0	0
T3	162522	2	0	0
T4	46038	0	0	0
T5	627321	4	0	0
T8	0	1	0	0
T9	0	2	0	0
T10	30619	0	0	0
T11	20153	0	0	0
T16	0	2	0	0
T20	0	1	0	0
T22	32642	0	0	0
T23	17432	0	0	0
T24	3104	0	0	0
T27	0	2	0	0
T45	0	1	0	0
T47	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	12	0	0
T6	22370	0	0	0
T9	298872	1	0	0
T14	100936	0	0	0
T15	101935	0	0	0
T27	542254	0	0	0
T31	0	1	0	0
T33	0	1	0	0
T44	31987	0	0	0
T45	56744	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	60974	0	0	0
T66	41249	0	0	0
T67	39521	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	153	0	0
T1	401278	1	0	0
T2	19567	0	0	0
T3	162522	1	0	0
T4	46038	0	0	0
T5	627321	1	0	0
T9	0	1	0	0
T10	30619	0	0	0
T11	20153	0	0	0
T16	0	1	0	0
T21	0	1	0	0
T22	32642	0	0	0
T23	17432	0	0	0
T24	3104	0	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T75	0	3	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693902987	349491710	0	0
T1	401278	397121	0	0
T2	19567	18484	0	0
T3	162522	586	0	0
T4	438	352	0	0
T5	627321	489773	0	0
T10	30619	30532	0	0
T11	20153	18559	0	0
T22	32642	32575	0	0
T23	17432	11679	0	0
T24	3104	2157	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	490	0	0
T1	401278	7	0	0
T2	19567	0	0	0
T3	162522	2	0	0
T4	46038	0	0	0
T5	627321	4	0	0
T8	0	1	0	0
T9	0	3	0	0
T10	30619	0	0	0
T11	20153	0	0	0
T16	0	2	0	0
T22	32642	0	0	0
T23	17432	0	0	0
T24	3104	0	0	0
T27	0	2	0	0
T45	0	1	0	0
T47	0	2	0	0
T67	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	483	0	0
T1	401278	7	0	0
T2	19567	0	0	0
T3	162522	2	0	0
T4	46038	0	0	0
T5	627321	4	0	0
T8	0	1	0	0
T9	0	3	0	0
T10	30619	0	0	0
T11	20153	0	0	0
T16	0	2	0	0
T22	32642	0	0	0
T23	17432	0	0	0
T24	3104	0	0	0
T27	0	2	0	0
T45	0	1	0	0
T47	0	2	0	0
T67	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	475	0	0
T1	401278	7	0	0
T2	19567	0	0	0
T3	162522	2	0	0
T4	46038	0	0	0
T5	627321	4	0	0
T8	0	1	0	0
T9	0	3	0	0
T10	30619	0	0	0
T11	20153	0	0	0
T16	0	2	0	0
T22	32642	0	0	0
T23	17432	0	0	0
T24	3104	0	0	0
T27	0	2	0	0
T45	0	1	0	0
T47	0	2	0	0
T67	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	466	0	0
T1	401278	7	0	0
T2	19567	0	0	0
T3	162522	2	0	0
T4	46038	0	0	0
T5	627321	4	0	0
T8	0	1	0	0
T9	0	3	0	0
T10	30619	0	0	0
T11	20153	0	0	0
T16	0	2	0	0
T22	32642	0	0	0
T23	17432	0	0	0
T24	3104	0	0	0
T27	0	2	0	0
T45	0	1	0	0
T47	0	2	0	0
T67	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	1064	0	0
T1	401278	13	0	0
T2	19567	0	0	0
T3	162522	0	0	0
T4	46038	0	0	0
T5	627321	0	0	0
T9	0	2	0	0
T10	30619	0	0	0
T11	20153	1	0	0
T21	0	1	0	0
T22	32642	0	0	0
T23	17432	0	0	0
T24	3104	0	0	0
T25	0	1	0	0
T28	0	1	0	0
T65	0	4	0	0
T67	0	6	0	0
T68	0	1	0	0
T77	0	9	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	117998	0	0
T1	401278	2514	0	0
T2	19567	0	0	0
T3	162522	0	0	0
T4	46038	0	0	0
T5	627321	0	0	0
T9	0	208	0	0
T10	30619	0	0	0
T11	20153	43	0	0
T21	0	62	0	0
T22	32642	0	0	0
T23	17432	0	0	0
T24	3104	0	0	0
T25	0	145	0	0
T28	0	266	0	0
T65	0	805	0	0
T67	0	600	0	0
T68	0	72	0	0
T77	0	609	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	993	0	0
T1	401278	11	0	0
T2	19567	0	0	0
T3	162522	0	0	0
T4	46038	0	0	0
T5	627321	0	0	0
T9	0	1	0	0
T10	30619	0	0	0
T11	20153	1	0	0
T22	32642	0	0	0
T23	17432	0	0	0
T24	3104	0	0	0
T25	0	1	0	0
T28	0	1	0	0
T65	0	4	0	0
T67	0	5	0	0
T68	0	1	0	0
T75	0	1	0	0
T77	0	9	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	57	0	0
T1	401278	2	0	0
T2	19567	0	0	0
T3	162522	0	0	0
T4	46038	0	0	0
T5	627321	0	0	0
T10	30619	0	0	0
T11	20153	0	0	0
T21	0	1	0	0
T22	32642	0	0	0
T23	17432	0	0	0
T24	3104	0	0	0
T33	0	1	0	0
T51	0	1	0	0
T52	0	2	0	0
T67	0	1	0	0
T75	0	5	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	1601	0	0
T4	46038	360	0	0
T5	627321	0	0	0
T6	0	176	0	0
T7	0	332	0	0
T10	30619	0	0	0
T11	20153	0	0	0
T22	32642	0	0	0
T23	17432	0	0	0
T24	3104	0	0	0
T25	33285	0	0	0
T26	84577	0	0	0
T40	0	340	0	0
T41	0	393	0	0
T42	11170	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	1331	0	0
T4	46038	300	0	0
T5	627321	0	0	0
T6	0	146	0	0
T7	0	272	0	0
T10	30619	0	0	0
T11	20153	0	0	0
T22	32642	0	0	0
T23	17432	0	0	0
T24	3104	0	0	0
T25	33285	0	0	0
T26	84577	0	0	0
T40	0	280	0	0
T41	0	333	0	0
T42	11170	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	693980546	0	0
T1	401278	401178	0	0
T2	19567	19513	0	0
T3	162522	162515	0	0
T4	46038	20441	0	0
T5	627321	627308	0	0
T10	30619	30533	0	0
T11	20153	20053	0	0
T22	32642	32576	0	0
T23	17432	17380	0	0
T24	3104	3042	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T2,T11
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T11

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T11
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T5,T22

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T11
1	0	1	Covered	T1,T5,T8
1	1	0	Covered	T1,T11,T5
1	1	1	Covered	T1,T2,T11

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T11
0	1	Covered	T11,T23,T26
1	0	Covered	T28,T52,T56

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T11
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T28,T52,T56

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T11
1	0	Not Covered
1	1	Covered	T11,T23,T26

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T22
1	Covered	T11,T5,T47

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T11,T5
1	Covered	T1,T22,T26

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T11,T5
1	Covered	T1,T5,T27

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T11,T5
1	Covered	T1,T5,T23

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T6,T7

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T11,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T5,T23

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T5,T23

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T5,T22

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T4,T6,T7
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T11,T5
Phase1St	193	Covered	T1,T11,T5
Phase2St	210	Covered	T1,T11,T5
Phase3St	228	Covered	T1,T11,T5
TerminalSt	244	Covered	T1,T11,T5
TimeoutSt	154	Covered	T1,T2,T11

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T4,T6,T7
IdleSt->Phase0St	147	Covered	T1,T5,T22
IdleSt->TimeoutSt	154	Covered	T1,T2,T11
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T1,T94,T95
Phase0St->Phase1St	193	Covered	T1,T11,T5
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T31,T86,T96
Phase1St->Phase2St	210	Covered	T1,T11,T5
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T34,T97,T98
Phase2St->Phase3St	228	Covered	T1,T11,T5
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T37,T96,T99
Phase3St->TerminalSt	244	Covered	T1,T11,T5
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T1,T5,T26
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T1,T2,T11
TimeoutSt->Phase0St	167	Covered	T11,T23,T26

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T5,T22
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T11
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T11,T23,T26
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T11
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T11
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T63,T100
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T11,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T11,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T31,T86,T96
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T11,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T11,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T34,T97,T98
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T11,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T11,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T37,T96,T99
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T11,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T11,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T5,T26
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T11,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T7
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	694166456	361	0	0
CheckAccumTrig0_A	694166456	497	0	0
CheckAccumTrig1_A	694166456	18	0	0
CheckClr_A	694166456	235	0	0
CheckEn_A	693902987	344771252	0	0
CheckPhase0_A	694166456	580	0	0
CheckPhase1_A	694166456	568	0	0
CheckPhase2_A	694166456	558	0	0
CheckPhase3_A	694166456	544	0	0
CheckTimeout0_A	694166456	851	0	0
CheckTimeoutSt1_A	694166456	98108	0	0
CheckTimeoutSt2_A	694166456	759	0	0
CheckTimeoutStTrig_A	694166456	73	0	0
ErrorStAllEscAsserted_A	694166456	1588	0	0
ErrorStIsTerminal_A	694166456	1318	0	0
u_state_regs_A	694166456	693980546	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	361	0	0
T4	46038	73	0	0
T5	627321	0	0	0
T6	0	36	0	0
T7	0	79	0	0
T10	30619	0	0	0
T11	20153	0	0	0
T22	32642	0	0	0
T23	17432	0	0	0
T24	3104	0	0	0
T25	33285	0	0	0
T26	84577	0	0	0
T40	0	79	0	0
T41	0	94	0	0
T42	11170	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	497	0	0
T1	401278	8	0	0
T2	19567	0	0	0
T3	162522	0	0	0
T4	46038	0	0	0
T5	627321	9	0	0
T9	0	1	0	0
T10	30619	0	0	0
T11	20153	0	0	0
T14	0	1	0	0
T20	0	1	0	0
T21	0	5	0	0
T22	32642	1	0	0
T23	17432	0	0	0
T24	3104	0	0	0
T27	0	2	0	0
T46	0	1	0	0
T48	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	18	0	0
T18	882199	0	0	0
T28	642572	2	0	0
T31	428526	0	0	0
T52	0	1	0	0
T56	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T75	318477	0	0	0
T78	91843	0	0	0
T79	72663	0	0	0
T101	0	1	0	0
T102	0	1	0	0
T103	0	1	0	0
T104	0	1	0	0
T105	64693	0	0	0
T106	60681	0	0	0
T107	78352	0	0	0
T108	172096	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	235	0	0
T1	401278	6	0	0
T2	19567	0	0	0
T3	162522	0	0	0
T4	46038	0	0	0
T5	627321	3	0	0
T10	30619	0	0	0
T11	20153	0	0	0
T21	0	2	0	0
T22	32642	0	0	0
T23	17432	0	0	0
T24	3104	0	0	0
T26	0	2	0	0
T27	0	1	0	0
T28	0	6	0	0
T34	0	3	0	0
T46	0	1	0	0
T72	0	1	0	0
T75	0	3	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693902987	344771252	0	0
T1	401278	118699	0	0
T2	19567	604	0	0
T3	162522	162515	0	0
T4	438	352	0	0
T5	627321	226146	0	0
T10	30619	30532	0	0
T11	20153	3967	0	0
T22	32642	9481	0	0
T23	17432	3189	0	0
T24	3104	2169	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	580	0	0
T1	401278	7	0	0
T2	19567	0	0	0
T3	162522	0	0	0
T4	46038	0	0	0
T5	627321	9	0	0
T9	0	1	0	0
T10	30619	0	0	0
T11	20153	1	0	0
T14	0	1	0	0
T22	32642	1	0	0
T23	17432	1	0	0
T24	3104	0	0	0
T26	0	3	0	0
T27	0	2	0	0
T45	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	568	0	0
T1	401278	7	0	0
T2	19567	0	0	0
T3	162522	0	0	0
T4	46038	0	0	0
T5	627321	9	0	0
T9	0	1	0	0
T10	30619	0	0	0
T11	20153	1	0	0
T14	0	1	0	0
T22	32642	1	0	0
T23	17432	1	0	0
T24	3104	0	0	0
T26	0	3	0	0
T27	0	2	0	0
T45	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	558	0	0
T1	401278	7	0	0
T2	19567	0	0	0
T3	162522	0	0	0
T4	46038	0	0	0
T5	627321	9	0	0
T9	0	1	0	0
T10	30619	0	0	0
T11	20153	1	0	0
T14	0	1	0	0
T22	32642	1	0	0
T23	17432	1	0	0
T24	3104	0	0	0
T26	0	3	0	0
T27	0	2	0	0
T45	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	544	0	0
T1	401278	7	0	0
T2	19567	0	0	0
T3	162522	0	0	0
T4	46038	0	0	0
T5	627321	9	0	0
T9	0	1	0	0
T10	30619	0	0	0
T11	20153	1	0	0
T14	0	1	0	0
T22	32642	1	0	0
T23	17432	1	0	0
T24	3104	0	0	0
T26	0	3	0	0
T27	0	2	0	0
T45	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	851	0	0
T1	401278	3	0	0
T2	19567	5	0	0
T3	162522	0	0	0
T4	46038	0	0	0
T5	627321	0	0	0
T9	0	1	0	0
T10	30619	0	0	0
T11	20153	4	0	0
T22	32642	0	0	0
T23	17432	2	0	0
T24	3104	0	0	0
T26	0	4	0	0
T45	0	1	0	0
T65	0	3	0	0
T67	0	9	0	0
T77	0	6	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	98108	0	0
T1	401278	537	0	0
T2	19567	425	0	0
T3	162522	0	0	0
T4	46038	0	0	0
T5	627321	0	0	0
T9	0	245	0	0
T10	30619	0	0	0
T11	20153	699	0	0
T22	32642	0	0	0
T23	17432	345	0	0
T24	3104	0	0	0
T26	0	1418	0	0
T45	0	523	0	0
T65	0	622	0	0
T67	0	1203	0	0
T77	0	480	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	759	0	0
T1	401278	3	0	0
T2	19567	5	0	0
T3	162522	0	0	0
T4	46038	0	0	0
T5	627321	0	0	0
T9	0	1	0	0
T10	30619	0	0	0
T11	20153	3	0	0
T21	0	5	0	0
T22	32642	0	0	0
T23	17432	1	0	0
T24	3104	0	0	0
T26	0	1	0	0
T65	0	3	0	0
T67	0	9	0	0
T77	0	6	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	73	0	0
T5	627321	0	0	0
T10	30619	0	0	0
T11	20153	1	0	0
T22	32642	0	0	0
T23	17432	1	0	0
T24	3104	0	0	0
T25	33285	0	0	0
T26	84577	3	0	0
T28	0	1	0	0
T31	0	2	0	0
T35	0	1	0	0
T42	11170	0	0	0
T43	92058	0	0	0
T45	0	1	0	0
T47	0	1	0	0
T49	0	1	0	0
T75	0	3	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	1588	0	0
T4	46038	321	0	0
T5	627321	0	0	0
T6	0	149	0	0
T7	0	364	0	0
T10	30619	0	0	0
T11	20153	0	0	0
T22	32642	0	0	0
T23	17432	0	0	0
T24	3104	0	0	0
T25	33285	0	0	0
T26	84577	0	0	0
T40	0	373	0	0
T41	0	381	0	0
T42	11170	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	1318	0	0
T4	46038	261	0	0
T5	627321	0	0	0
T6	0	119	0	0
T7	0	304	0	0
T10	30619	0	0	0
T11	20153	0	0	0
T22	32642	0	0	0
T23	17432	0	0	0
T24	3104	0	0	0
T25	33285	0	0	0
T26	84577	0	0	0
T40	0	313	0	0
T41	0	321	0	0
T42	11170	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	693980546	0	0
T1	401278	401178	0	0
T2	19567	19513	0	0
T3	162522	162515	0	0
T4	46038	20441	0	0
T5	627321	627308	0	0
T10	30619	30533	0	0
T11	20153	20053	0	0
T22	32642	32576	0	0
T23	17432	17380	0	0
T24	3104	3042	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T5

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T11
1	0	1	Covered	T1,T5,T22
1	1	0	Covered	T1,T11,T5
1	1	1	Covered	T1,T2,T11

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T11
0	1	Covered	T26,T21,T75
1	0	Covered	T47,T109,T110

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T11
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T47,T109,T110

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T11
1	0	Covered	T29
1	1	Covered	T26,T21,T75

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T5,T9

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T22,T27,T21

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T3,T5

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T3,T26

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T4,T6,T7

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T5,T22,T9

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T3,T5

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T3,T5,T22

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T7
1	0	Covered	T1,T5,T22

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T4,T6,T7
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T1,T3,T5
Phase1St	193	Covered	T1,T3,T5
Phase2St	210	Covered	T1,T3,T5
Phase3St	228	Covered	T1,T3,T5
TerminalSt	244	Covered	T1,T3,T5
TimeoutSt	154	Covered	T1,T2,T11

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T4,T6,T7
IdleSt->Phase0St	147	Covered	T1,T3,T5
IdleSt->TimeoutSt	154	Covered	T1,T2,T11
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T38,T111,T112
Phase0St->Phase1St	193	Covered	T1,T3,T5
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T31,T113,T114
Phase1St->Phase2St	210	Covered	T1,T3,T5
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T31,T35,T115
Phase2St->Phase3St	228	Covered	T1,T3,T5
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T52,T111,T116
Phase3St->TerminalSt	244	Covered	T1,T3,T5
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T1,T3,T5
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T1,T2,T11
TimeoutSt->Phase0St	167	Covered	T26,T47,T21

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T11
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T26,T47,T21
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T11
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T11
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T38,T111,T112
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T31,T113,T114
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T31,T35,T115
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T52,T111,T116
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T21,T28
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T7
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T7

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	694166456	301	0	0
CheckAccumTrig0_A	694166456	536	0	0
CheckAccumTrig1_A	694166456	24	0	0
CheckClr_A	694166456	248	0	0
CheckEn_A	693902987	318654845	0	0
CheckPhase0_A	694166456	615	0	0
CheckPhase1_A	694166456	608	0	0
CheckPhase2_A	694166456	595	0	0
CheckPhase3_A	694166456	580	0	0
CheckTimeout0_A	694166456	1017	0	0
CheckTimeoutSt1_A	694166456	120099	0	0
CheckTimeoutSt2_A	694166456	928	0	0
CheckTimeoutStTrig_A	694166456	63	0	0
ErrorStAllEscAsserted_A	694166456	1592	0	0
ErrorStIsTerminal_A	694166456	1322	0	0
u_state_regs_A	694166456	693980546	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	301	0	0
T4	46038	59	0	0
T5	627321	0	0	0
T6	0	51	0	0
T7	0	61	0	0
T10	30619	0	0	0
T11	20153	0	0	0
T22	32642	0	0	0
T23	17432	0	0	0
T24	3104	0	0	0
T25	33285	0	0	0
T26	84577	0	0	0
T40	0	79	0	0
T41	0	51	0	0
T42	11170	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	536	0	0
T1	401278	3	0	0
T2	19567	0	0	0
T3	162522	2	0	0
T4	46038	0	0	0
T5	627321	3	0	0
T8	0	1	0	0
T9	0	1	0	0
T10	30619	0	0	0
T11	20153	0	0	0
T15	0	1	0	0
T22	32642	1	0	0
T23	17432	0	0	0
T24	3104	0	0	0
T27	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	24	0	0
T17	528881	0	0	0
T20	297174	0	0	0
T21	350908	0	0	0
T47	21575	1	0	0
T48	9061	0	0	0
T61	0	1	0	0
T68	4365	0	0	0
T69	185276	0	0	0
T70	109939	0	0	0
T71	16875	0	0	0
T72	468731	0	0	0
T88	0	1	0	0
T109	0	1	0	0
T110	0	1	0	0
T117	0	1	0	0
T118	0	1	0	0
T119	0	1	0	0
T120	0	1	0	0
T121	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	248	0	0
T3	162522	1	0	0
T4	46038	0	0	0
T5	627321	0	0	0
T10	30619	0	0	0
T11	20153	0	0	0
T21	0	3	0	0
T22	32642	0	0	0
T23	17432	0	0	0
T24	3104	0	0	0
T25	33285	0	0	0
T26	84577	0	0	0
T28	0	2	0	0
T31	0	7	0	0
T35	0	1	0	0
T38	0	1	0	0
T51	0	1	0	0
T75	0	2	0	0
T76	0	1	0	0
T80	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	693902987	318654845	0	0
T1	401278	938147	0	0
T2	19567	1636	0	0
T3	162522	2487	0	0
T4	438	352	0	0
T5	627321	470610	0	0
T10	30619	30532	0	0
T11	20153	15887	0	0
T22	32642	2132	0	0
T23	17432	17379	0	0
T24	3104	2177	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	615	0	0
T1	401278	3	0	0
T2	19567	0	0	0
T3	162522	2	0	0
T4	46038	0	0	0
T5	627321	3	0	0
T8	0	1	0	0
T9	0	1	0	0
T10	30619	0	0	0
T11	20153	0	0	0
T15	0	1	0	0
T22	32642	1	0	0
T23	17432	0	0	0
T24	3104	0	0	0
T26	0	1	0	0
T27	0	2	0	0
T45	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	608	0	0
T1	401278	3	0	0
T2	19567	0	0	0
T3	162522	2	0	0
T4	46038	0	0	0
T5	627321	3	0	0
T8	0	1	0	0
T9	0	1	0	0
T10	30619	0	0	0
T11	20153	0	0	0
T15	0	1	0	0
T22	32642	1	0	0
T23	17432	0	0	0
T24	3104	0	0	0
T26	0	1	0	0
T27	0	2	0	0
T45	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	595	0	0
T1	401278	3	0	0
T2	19567	0	0	0
T3	162522	2	0	0
T4	46038	0	0	0
T5	627321	3	0	0
T8	0	1	0	0
T9	0	1	0	0
T10	30619	0	0	0
T11	20153	0	0	0
T15	0	1	0	0
T22	32642	1	0	0
T23	17432	0	0	0
T24	3104	0	0	0
T26	0	1	0	0
T27	0	2	0	0
T45	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	580	0	0
T1	401278	3	0	0
T2	19567	0	0	0
T3	162522	2	0	0
T4	46038	0	0	0
T5	627321	3	0	0
T8	0	1	0	0
T9	0	1	0	0
T10	30619	0	0	0
T11	20153	0	0	0
T15	0	1	0	0
T22	32642	1	0	0
T23	17432	0	0	0
T24	3104	0	0	0
T26	0	1	0	0
T27	0	2	0	0
T45	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	1017	0	0
T1	401278	18	0	0
T2	19567	2	0	0
T3	162522	0	0	0
T4	46038	0	0	0
T5	627321	0	0	0
T10	30619	0	0	0
T11	20153	1	0	0
T21	0	7	0	0
T22	32642	0	0	0
T23	17432	0	0	0
T24	3104	0	0	0
T25	0	6	0	0
T26	0	1	0	0
T28	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T77	0	8	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	120099	0	0
T1	401278	3302	0	0
T2	19567	277	0	0
T3	162522	0	0	0
T4	46038	0	0	0
T5	627321	0	0	0
T10	30619	0	0	0
T11	20153	41	0	0
T21	0	998	0	0
T22	32642	0	0	0
T23	17432	0	0	0
T24	3104	0	0	0
T25	0	877	0	0
T26	0	902	0	0
T28	0	308	0	0
T45	0	856	0	0
T47	0	7	0	0
T77	0	644	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	928	0	0
T1	401278	18	0	0
T2	19567	2	0	0
T3	162522	0	0	0
T4	46038	0	0	0
T5	627321	0	0	0
T10	30619	0	0	0
T11	20153	1	0	0
T21	0	6	0	0
T22	32642	0	0	0
T23	17432	0	0	0
T24	3104	0	0	0
T25	0	6	0	0
T28	0	1	0	0
T31	0	4	0	0
T45	0	1	0	0
T75	0	10	0	0
T77	0	8	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	63	0	0
T6	22370	0	0	0
T8	782501	0	0	0
T9	298872	0	0	0
T14	100936	0	0	0
T21	0	1	0	0
T26	84577	1	0	0
T33	0	1	0	0
T35	0	2	0	0
T42	11170	0	0	0
T43	92058	0	0	0
T44	31987	0	0	0
T75	0	3	0	0
T77	36402	0	0	0
T80	0	1	0	0
T83	14872	0	0	0
T117	0	1	0	0
T120	0	1	0	0
T122	0	2	0	0
T123	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	1592	0	0
T4	46038	348	0	0
T5	627321	0	0	0
T6	0	173	0	0
T7	0	327	0	0
T10	30619	0	0	0
T11	20153	0	0	0
T22	32642	0	0	0
T23	17432	0	0	0
T24	3104	0	0	0
T25	33285	0	0	0
T26	84577	0	0	0
T40	0	387	0	0
T41	0	357	0	0
T42	11170	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	1322	0	0
T4	46038	288	0	0
T5	627321	0	0	0
T6	0	143	0	0
T7	0	267	0	0
T10	30619	0	0	0
T11	20153	0	0	0
T22	32642	0	0	0
T23	17432	0	0	0
T24	3104	0	0	0
T25	33285	0	0	0
T26	84577	0	0	0
T40	0	327	0	0
T41	0	297	0	0
T42	11170	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	694166456	693980546	0	0
T1	401278	401178	0	0
T2	19567	19513	0	0
T3	162522	162515	0	0
T4	46038	20441	0	0
T5	627321	627308	0	0
T10	30619	30533	0	0
T11	20153	20053	0	0
T22	32642	32576	0	0
T23	17432	17380	0	0
T24	3104	3042	0	0