Unified Coverage Report :: Module :: prim_count

Module : prim_count

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
68.57			68.57

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_count_0/rtl/prim_count.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_ping_timer.u_prim_count_esc_cnt	24.32			24.32
tb.dut.gen_classes[0].u_esc_timer.u_prim_count	37.14			37.14
tb.dut.gen_classes[1].u_esc_timer.u_prim_count	37.14			37.14
tb.dut.gen_classes[2].u_esc_timer.u_prim_count	37.14			37.14
tb.dut.gen_classes[3].u_esc_timer.u_prim_count	37.14			37.14
tb.dut.gen_classes[1].u_accu.u_prim_count	83.78			83.78
tb.dut.gen_classes[2].u_accu.u_prim_count	86.49			86.49
tb.dut.gen_classes[0].u_accu.u_prim_count	89.19			89.19
tb.dut.gen_classes[3].u_accu.u_prim_count	89.19			89.19
tb.dut.u_ping_timer.u_prim_count_cnt	100.00			100.00

---

Module Instance : tb.dut.u_ping_timer.u_prim_count_esc_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
24.32			24.32

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
24.32			24.32

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.46	100.00	97.30		100.00	100.00	100.00	u_ping_timer

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
37.14			37.14

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
37.14			37.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.67	100.00	93.33		100.00	100.00	100.00	gen_classes[0].u_esc_timer

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
37.14			37.14

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
37.14			37.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.67	100.00	93.33		100.00	100.00	100.00	gen_classes[1].u_esc_timer

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
37.14			37.14

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
37.14			37.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.67	100.00	93.33		100.00	100.00	100.00	gen_classes[2].u_esc_timer

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
37.14			37.14

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
37.14			37.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.11	100.00	95.56		100.00	100.00	100.00	gen_classes[3].u_esc_timer

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_classes[1].u_accu.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.78			83.78

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.78			83.78

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	gen_classes[1].u_accu

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_classes[2].u_accu.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.49			86.49

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.49			86.49

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	gen_classes[2].u_accu

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_classes[0].u_accu.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.19			89.19

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.19			89.19

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	gen_classes[0].u_accu

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_classes[3].u_accu.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.19			89.19

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.19			89.19

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	gen_classes[3].u_accu

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ping_timer.u_prim_count_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.46	100.00	97.30		100.00	100.00	100.00	u_ping_timer

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_count ( parameter Width=16,ResetValue=0,EnableAlertTriggerSVA=0,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
24.32	24.32

tb.dut.u_ping_timer.u_prim_count_esc_cnt

SCORE	TOGGLE
100.00	100.00

tb.dut.u_ping_timer.u_prim_count_cnt

SCORE	TOGGLE
89.19	89.19

tb.dut.gen_classes[0].u_accu.u_prim_count

SCORE	TOGGLE
83.78	83.78

tb.dut.gen_classes[1].u_accu.u_prim_count

SCORE	TOGGLE
86.49	86.49

tb.dut.gen_classes[2].u_accu.u_prim_count

SCORE	TOGGLE
89.19	89.19

tb.dut.gen_classes[3].u_accu.u_prim_count

	Total	Covered	Percent
Totals	10	10	100.00
Total Bits	110	110	100.00
Total Bits 0->1	55	55	100.00
Total Bits 1->0	55	55	100.00

Ports	10	10	100.00
Port Bits	110	110	100.00
Port Bits 0->1	55	55	100.00
Port Bits 1->0	55	55	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
set_cnt_i[15:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
incr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
decr_en_i	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
step_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[15:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cnt_after_commit_o[15:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
err_o	Yes	Yes	T4,T6,T7	Yes	T4,T6,T7	OUTPUT

---

Toggle Coverage for Module : prim_count ( parameter Width=32,ResetValue=0,EnableAlertTriggerSVA=0,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
37.14	37.14

tb.dut.gen_classes[0].u_esc_timer.u_prim_count

SCORE	TOGGLE
37.14	37.14

tb.dut.gen_classes[1].u_esc_timer.u_prim_count

SCORE	TOGGLE
37.14	37.14

tb.dut.gen_classes[2].u_esc_timer.u_prim_count

SCORE	TOGGLE
37.14	37.14

tb.dut.gen_classes[3].u_esc_timer.u_prim_count

	Total	Covered	Percent
Totals	8	6	75.00
Total Bits	140	52	37.14
Total Bits 0->1	70	26	37.14
Total Bits 1->0	70	26	37.14

Ports	8	6	75.00
Port Bits	140	52	37.14
Port Bits 0->1	70	26	37.14
Port Bits 1->0	70	26	37.14

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_cnt_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[9:0]	Yes	Yes	T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
cnt_o[31:10]	No	No		No		OUTPUT
cnt_after_commit_o[9:0]	Yes	Yes	T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
cnt_after_commit_o[31:10]	No	No		No		OUTPUT
err_o	Yes	Yes	T4,T6,T7	Yes	T4,T6,T7	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_ping_timer.u_prim_count_esc_cnt

	Total	Covered	Percent
Totals	7	5	71.43
Total Bits	74	18	24.32
Total Bits 0->1	37	9	24.32
Total Bits 1->0	37	9	24.32

Ports	7	5	71.43
Port Bits	74	18	24.32
Port Bits 0->1	37	9	24.32
Port Bits 1->0	37	9	24.32

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T3,T8,T9	Yes	T3,T8,T9	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T3,T8,T9	Yes	T3,T8,T9	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[1:0]	Yes	Yes	T3,T8,T9	Yes	T3,T8,T9	OUTPUT
cnt_o[15:2]	No	No		No		OUTPUT
cnt_after_commit_o[1:0]	Yes	Yes	T3,T8,T9	Yes	T3,T8,T9	OUTPUT
cnt_after_commit_o[15:2]	No	No		No		OUTPUT
err_o	Yes	Yes	T4,T6,T7	Yes	T4,T6,T7	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer.u_prim_count

	Total	Covered	Percent
Totals	8	6	75.00
Total Bits	140	52	37.14
Total Bits 0->1	70	26	37.14
Total Bits 1->0	70	26	37.14

Ports	8	6	75.00
Port Bits	140	52	37.14
Port Bits 0->1	70	26	37.14
Port Bits 1->0	70	26	37.14

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
set_i	Yes	Yes	T1,T5,T10	Yes	T1,T5,T10	INPUT
set_cnt_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T5,T10	Yes	T1,T5,T10	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[9:0]	Yes	Yes	*T1,T5,*T10	Yes	T1,T5,T10	OUTPUT
cnt_o[31:10]	No	No		No		OUTPUT
cnt_after_commit_o[9:0]	Yes	Yes	*T1,T5,*T10	Yes	T1,T5,T10	OUTPUT
cnt_after_commit_o[31:10]	No	No		No		OUTPUT
err_o	Yes	Yes	T4,T6,T7	Yes	T4,T6,T7	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer.u_prim_count

	Total	Covered	Percent
Totals	8	6	75.00
Total Bits	140	52	37.14
Total Bits 0->1	70	26	37.14
Total Bits 1->0	70	26	37.14

Ports	8	6	75.00
Port Bits	140	52	37.14
Port Bits 0->1	70	26	37.14
Port Bits 1->0	70	26	37.14

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
set_i	Yes	Yes	T1,T3,T11	Yes	T1,T3,T11	INPUT
set_cnt_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T3,T11	Yes	T1,T3,T11	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[9:0]	Yes	Yes	T1,T3,*T11	Yes	T1,T3,T11	OUTPUT
cnt_o[31:10]	No	No		No		OUTPUT
cnt_after_commit_o[9:0]	Yes	Yes	T1,T3,*T11	Yes	T1,T3,T11	OUTPUT
cnt_after_commit_o[31:10]	No	No		No		OUTPUT
err_o	Yes	Yes	T4,T6,T7	Yes	T4,T6,T7	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer.u_prim_count

	Total	Covered	Percent
Totals	8	6	75.00
Total Bits	140	52	37.14
Total Bits 0->1	70	26	37.14
Total Bits 1->0	70	26	37.14

Ports	8	6	75.00
Port Bits	140	52	37.14
Port Bits 0->1	70	26	37.14
Port Bits 1->0	70	26	37.14

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
set_i	Yes	Yes	T1,T2,T11	Yes	T1,T2,T11	INPUT
set_cnt_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T2,T11	Yes	T1,T2,T11	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[9:0]	Yes	Yes	T1,*T2,*T11	Yes	T1,T2,T11	OUTPUT
cnt_o[31:10]	No	No		No		OUTPUT
cnt_after_commit_o[9:0]	Yes	Yes	T1,*T2,*T11	Yes	T1,T2,T11	OUTPUT
cnt_after_commit_o[31:10]	No	No		No		OUTPUT
err_o	Yes	Yes	T4,T6,T7	Yes	T4,T6,T7	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer.u_prim_count

	Total	Covered	Percent
Totals	8	6	75.00
Total Bits	140	52	37.14
Total Bits 0->1	70	26	37.14
Total Bits 1->0	70	26	37.14

Ports	8	6	75.00
Port Bits	140	52	37.14
Port Bits 0->1	70	26	37.14
Port Bits 1->0	70	26	37.14

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_cnt_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[9:0]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
cnt_o[31:10]	No	No		No		OUTPUT
cnt_after_commit_o[9:0]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
cnt_after_commit_o[31:10]	No	No		No		OUTPUT
err_o	Yes	Yes	T4,T6,T7	Yes	T4,T6,T7	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_classes[1].u_accu.u_prim_count

	Total	Covered	Percent
Totals	7	5	71.43
Total Bits	74	62	83.78
Total Bits 0->1	37	31	83.78
Total Bits 1->0	37	31	83.78

Ports	7	5	71.43
Port Bits	74	62	83.78
Port Bits 0->1	37	31	83.78
Port Bits 1->0	37	31	83.78

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[12:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cnt_o[15:13]	No	No		No		OUTPUT
cnt_after_commit_o[12:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cnt_after_commit_o[15:13]	No	No		No		OUTPUT
err_o	Yes	Yes	T4,T6,T7	Yes	T4,T6,T7	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_classes[2].u_accu.u_prim_count

	Total	Covered	Percent
Totals	7	5	71.43
Total Bits	74	64	86.49
Total Bits 0->1	37	33	89.19
Total Bits 1->0	37	31	83.78

Ports	7	5	71.43
Port Bits	74	64	86.49
Port Bits 0->1	37	33	89.19
Port Bits 1->0	37	31	83.78

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T2,T11	Yes	T1,T2,T11	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[12:0]	Yes	Yes	*T1,*T2,*T11	Yes	T1,T2,T11	OUTPUT
cnt_o[13]	No	No		Yes	T12,T13	OUTPUT
cnt_o[15:14]	No	No		No		OUTPUT
cnt_after_commit_o[12:0]	Yes	Yes	*T1,*T2,*T11	Yes	T1,T2,T11	OUTPUT
cnt_after_commit_o[13]	No	No		Yes	T12,T13	OUTPUT
cnt_after_commit_o[15:14]	No	No		No		OUTPUT
err_o	Yes	Yes	T4,T6,T7	Yes	T4,T6,T7	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_classes[0].u_accu.u_prim_count

	Total	Covered	Percent
Totals	7	5	71.43
Total Bits	74	66	89.19
Total Bits 0->1	37	33	89.19
Total Bits 1->0	37	33	89.19

Ports	7	5	71.43
Port Bits	74	66	89.19
Port Bits 0->1	37	33	89.19
Port Bits 1->0	37	33	89.19

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[13:0]	Yes	Yes	*T1,*T2,*T5	Yes	T1,T2,T5	OUTPUT
cnt_o[15:14]	No	No		No		OUTPUT
cnt_after_commit_o[13:0]	Yes	Yes	*T1,*T2,*T5	Yes	T1,T2,T5	OUTPUT
cnt_after_commit_o[15:14]	No	No		No		OUTPUT
err_o	Yes	Yes	T4,T6,T7	Yes	T4,T6,T7	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_classes[3].u_accu.u_prim_count

	Total	Covered	Percent
Totals	7	5	71.43
Total Bits	74	66	89.19
Total Bits 0->1	37	33	89.19
Total Bits 1->0	37	33	89.19

Ports	7	5	71.43
Port Bits	74	66	89.19
Port Bits 0->1	37	33	89.19
Port Bits 1->0	37	33	89.19

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[13:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cnt_o[15:14]	No	No		No		OUTPUT
cnt_after_commit_o[13:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cnt_after_commit_o[15:14]	No	No		No		OUTPUT
err_o	Yes	Yes	T4,T6,T7	Yes	T4,T6,T7	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_ping_timer.u_prim_count_cnt

	Total	Covered	Percent
Totals	8	8	100.00
Total Bits	106	106	100.00
Total Bits 0->1	53	53	100.00
Total Bits 1->0	53	53	100.00

Ports	8	8	100.00
Port Bits	106	106	100.00
Port Bits 0->1	53	53	100.00
Port Bits 1->0	53	53	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
clr_i	Unreachable	Unreachable		Unreachable		INPUT
set_i	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
set_cnt_i[15:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
incr_en_i	Unreachable	Unreachable		Unreachable		INPUT
decr_en_i	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
step_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[15:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
cnt_after_commit_o[15:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
err_o	Yes	Yes	T4,T6,T7	Yes	T4,T6,T7	OUTPUT