Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.69	96.04	76.60		65.00	88.46	82.35

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	87.50	96.04	77.78		92.86	88.46	82.35
tb.dut.gen_classes[1].u_esc_timer	87.50	96.04	77.78		92.86	88.46	82.35
tb.dut.gen_classes[2].u_esc_timer	87.50	96.04	77.78		92.86	88.46	82.35
tb.dut.gen_classes[3].u_esc_timer	87.94	96.04	80.00		92.86	88.46	82.35

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	96.04	77.78		92.86	88.46	82.35

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.22	96.36	77.78	35.71	92.86	89.29	83.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
81.27	100.00		96.95			46.88	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	35.71			35.71
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	96.04	77.78		92.86	88.46	82.35

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.22	96.36	77.78	35.71	92.86	89.29	83.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
81.27	100.00		96.95			46.88	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	35.71			35.71
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	96.04	77.78		92.86	88.46	82.35

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.22	96.36	77.78	35.71	92.86	89.29	83.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
81.27	100.00		96.95			46.88	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	35.71			35.71
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.94	96.04	80.00		92.86	88.46	82.35

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.59	96.36	80.00	35.71	92.86	89.29	83.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
81.27	100.00		96.95			46.88	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	35.71			35.71
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	97	96.04
CONT_ASSIGN	83	1	1	100.00
ALWAYS	132	89	85	95.51
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
ALWAYS	303	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
83	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
142	1	1
146	1	1
147	1	1
149	1	1
150	1	1
151	1	1
152	1	1
155	1	1
156	1	1
157	1	1
			MISSING_ELSE
167	1	1
169	1	1
170	1	1
171	1	1
172	1	1
173	1	1
176	1	1
177	1	1
179	1	1
180	1	1
185	1	1
186	1	1
187	1	1
188	1	1
189	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
			MISSING_ELSE
202	1	1
203	1	1
204	1	1
205	1	1
206	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
			MISSING_ELSE
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
226	1	1
227	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
			MISSING_ELSE
236	1	1
237	1	1
238	1	1
239	1	1
240	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
			MISSING_ELSE
256	1	1
257	1	1
258	1	1
259	1	1
			MISSING_ELSE
266	0	1
267	0	1
281	1	1
282	0	1
283	0	1
			MISSING_ELSE
290	4	4
293	4	4
303	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	36	76.60
Logical	47	36	76.60
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       64
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       149
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T4

 LINE       155
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T1,T4,T55
1	1	1	Covered	T1,T4,T65

 LINE       169
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T65
0	1	Covered	T1,T65,T16
1	0	Covered	T1,T16,T15

 LINE       169
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T65
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T16,T15

 LINE       169
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T65
1	0	Covered	T53
1	1	Covered	T1,T65,T16

 LINE       189
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T7

 LINE       206
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T8,T25

 LINE       223
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T8

 LINE       240
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T8
1	Covered	T1,T4,T5

 LINE       281
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       293
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T4,T5

 LINE       293
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T4,T25

 LINE       293
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T4,T8

 LINE       293
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T4,T5

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	7	87.50	(Not included in score)
Transitions	20	13	65.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	282	Not Covered
IdleSt	179	Covered	T1,T2,T3
Phase0St	150	Covered	T1,T4,T5
Phase1St	196	Covered	T1,T4,T5
Phase2St	213	Covered	T1,T4,T5
Phase3St	231	Covered	T1,T4,T5
TerminalSt	247	Covered	T1,T4,T5
TimeoutSt	157	Covered	T1,T4,T65

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	282	Not Covered
IdleSt->Phase0St	150	Covered	T1,T4,T5
IdleSt->TimeoutSt	157	Covered	T1,T4,T65
Phase0St->FsmErrorSt	282	Not Covered
Phase0St->IdleSt	192	Covered	T1,T20,T27
Phase0St->Phase1St	196	Covered	T1,T4,T5
Phase1St->FsmErrorSt	282	Not Covered
Phase1St->IdleSt	209	Covered	T16,T66,T49
Phase1St->Phase2St	213	Covered	T1,T4,T5
Phase2St->FsmErrorSt	282	Not Covered
Phase2St->IdleSt	227	Covered	T27,T67,T45
Phase2St->Phase3St	231	Covered	T1,T4,T5
Phase3St->FsmErrorSt	282	Not Covered
Phase3St->IdleSt	243	Covered	T16,T15,T22
Phase3St->TerminalSt	247	Covered	T1,T4,T5
TerminalSt->FsmErrorSt	282	Not Covered
TerminalSt->IdleSt	259	Covered	T1,T4,T25
TimeoutSt->FsmErrorSt	282	Not Covered
TimeoutSt->IdleSt	179	Covered	T1,T4,T16
TimeoutSt->Phase0St	170	Covered	T1,T65,T16

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	23	88.46
CASE	142	22	20	90.91
IF	281	2	1	50.00
IF	303	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	142	case (state_q)
-2-:	149	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	155	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	169	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	176	if (timeout_en_i)
-6-:	191	if (clr_i)
-7-:	195	if (cnt_ge)
-8-:	208	if (clr_i)
-9-:	212	if (cnt_ge)
-10-:	226	if (clr_i)
-11-:	230	if (cnt_ge)
-12-:	242	if (clr_i)
-13-:	246	if (cnt_ge)
-14-:	258	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T65
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T65,T16
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T65
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T4,T16,T20
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T4,T16,T20
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T4,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T4,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T16,T66,T49
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T4,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T4,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T27,T67,T45
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T4,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T16,T15,T22
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T4,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T4,T25
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T4,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	281	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	303	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	14	82.35
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	14	82.35

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	0	0	0
CheckAccumTrig0_A	2147483647	2266	0	0
CheckAccumTrig1_A	2147483647	140	0	0
CheckClr_A	2147483647	1088	0	0
CheckEn_A	2147483647	1070544959	0	0
CheckPhase0_A	2147483647	2601	0	0
CheckPhase1_A	2147483647	2545	0	0
CheckPhase2_A	2147483647	2494	0	0
CheckPhase3_A	2147483647	2455	0	0
CheckTimeout0_A	2147483647	4057	0	0
CheckTimeoutSt1_A	2147483647	410953	0	0
CheckTimeoutSt2_A	2147483647	3674	0	0
CheckTimeoutStTrig_A	2147483647	235	0	0
ErrorStAllEscAsserted_A	2147483647	0	0	0
ErrorStIsTerminal_A	2147483647	0	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2266	0	0
T1	1774998	15	0	0
T2	149232	0	0	0
T3	973395	0	0	0
T4	886712	26	0	0
T5	333948	1	0	0
T6	3924560	1	0	0
T7	1389420	3	0	0
T8	134064	3	0	0
T15	0	6	0	0
T16	366536	25	0	0
T17	0	2	0	0
T25	572720	4	0	0
T26	0	2	0	0
T30	0	1	0	0
T48	0	1	0	0
T54	0	1	0	0
T55	106340	1	0	0
T56	0	5	0	0
T65	91383	0	0	0
T68	29780	3	0	0
T69	0	3	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	140	0	0
T1	591666	1	0	0
T2	49744	0	0	0
T3	324465	0	0	0
T4	221678	0	0	0
T5	83487	0	0	0
T6	981140	0	0	0
T7	347355	0	0	0
T8	33516	0	0	0
T9	0	1	0	0
T10	0	2	0	0
T15	373490	1	0	0
T16	0	1	0	0
T19	0	1	0	0
T21	34052	4	0	0
T22	1498220	2	0	0
T23	270290	0	0	0
T25	143180	0	0	0
T45	0	3	0	0
T51	0	4	0	0
T52	0	2	0	0
T55	26585	0	0	0
T57	24147	0	0	0
T59	613339	0	0	0
T60	538389	0	0	0
T61	551205	0	0	0
T70	0	2	0	0
T71	0	4	0	0
T72	0	3	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	4	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	581544	0	0	0
T81	121492	0	0	0
T82	5416	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1088	0	0
T1	1183332	4	0	0
T2	99488	0	0	0
T3	648930	0	0	0
T4	665034	16	0	0
T5	250461	0	0	0
T6	2943420	0	0	0
T7	1042065	0	0	0
T8	100548	0	0	0
T15	0	7	0	0
T16	733072	9	0	0
T17	553329	0	0	0
T18	0	2	0	0
T20	22959	1	0	0
T21	0	7	0	0
T22	0	13	0	0
T25	572720	2	0	0
T26	3556	0	0	0
T27	0	8	0	0
T43	0	1	0	0
T49	0	2	0	0
T55	106340	0	0	0
T56	0	2	0	0
T60	0	2	0	0
T61	0	3	0	0
T63	0	1	0	0
T64	0	5	0	0
T65	182766	0	0	0
T66	0	1	0	0
T68	59560	0	0	0
T69	0	2	0	0
T83	0	2	0	0
T84	0	1	0	0
T85	74182	0	0	0
T86	3629	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1070544959	0	0
T1	2366664	1994340	0	0
T2	198976	12386	0	0
T3	1297860	937813	0	0
T4	886712	486470	0	0
T5	333948	255533	0	0
T6	3924560	2023834	0	0
T7	1389420	364704	0	0
T8	134064	42429	0	0
T25	572720	154244	0	0
T55	106340	89826	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2601	0	0
T1	2366664	17	0	0
T2	198976	0	0	0
T3	1297860	0	0	0
T4	886712	23	0	0
T5	333948	1	0	0
T6	3924560	1	0	0
T7	1389420	3	0	0
T8	134064	3	0	0
T16	0	28	0	0
T17	0	2	0	0
T25	572720	4	0	0
T26	0	1	0	0
T30	0	2	0	0
T48	0	1	0	0
T54	0	1	0	0
T55	106340	1	0	0
T56	0	1	0	0
T65	0	1	0	0
T68	0	3	0	0
T69	0	3	0	0
T87	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2545	0	0
T1	2366664	17	0	0
T2	198976	0	0	0
T3	1297860	0	0	0
T4	886712	20	0	0
T5	333948	1	0	0
T6	3924560	1	0	0
T7	1389420	3	0	0
T8	134064	3	0	0
T16	0	26	0	0
T17	0	2	0	0
T25	572720	4	0	0
T26	0	1	0	0
T30	0	2	0	0
T48	0	1	0	0
T54	0	1	0	0
T55	106340	1	0	0
T56	0	1	0	0
T65	0	1	0	0
T68	0	3	0	0
T69	0	3	0	0
T87	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2494	0	0
T1	2366664	17	0	0
T2	198976	0	0	0
T3	1297860	0	0	0
T4	886712	20	0	0
T5	333948	1	0	0
T6	3924560	1	0	0
T7	1389420	3	0	0
T8	134064	3	0	0
T16	0	26	0	0
T17	0	2	0	0
T25	572720	4	0	0
T26	0	1	0	0
T30	0	2	0	0
T48	0	1	0	0
T54	0	1	0	0
T55	106340	1	0	0
T56	0	1	0	0
T65	0	1	0	0
T68	0	3	0	0
T69	0	3	0	0
T87	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2455	0	0
T1	2366664	17	0	0
T2	198976	0	0	0
T3	1297860	0	0	0
T4	886712	19	0	0
T5	333948	1	0	0
T6	3924560	1	0	0
T7	1389420	3	0	0
T8	134064	3	0	0
T16	0	25	0	0
T17	0	2	0	0
T25	572720	4	0	0
T26	0	1	0	0
T30	0	2	0	0
T48	0	1	0	0
T54	0	1	0	0
T55	106340	1	0	0
T56	0	1	0	0
T65	0	1	0	0
T68	0	3	0	0
T69	0	3	0	0
T87	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4057	0	0
T1	2366664	10	0	0
T2	198976	0	0	0
T3	1297860	0	0	0
T4	886712	1	0	0
T5	333948	0	0	0
T6	3924560	0	0	0
T7	1389420	0	0	0
T8	134064	0	0	0
T15	0	2	0	0
T16	0	8	0	0
T20	0	8	0	0
T21	0	13	0	0
T22	0	8	0	0
T25	572720	0	0	0
T27	0	4	0	0
T28	0	1	0	0
T30	0	1	0	0
T49	0	1	0	0
T50	0	3	0	0
T55	106340	0	0	0
T63	0	2	0	0
T65	0	1	0	0
T69	0	1	0	0
T83	0	2	0	0
T87	0	3	0	0
T88	0	3	0	0
T89	0	4	0	0
T90	0	1	0	0
T91	0	3	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	410953	0	0
T1	2366664	891	0	0
T2	198976	0	0	0
T3	1297860	0	0	0
T4	886712	152	0	0
T5	333948	0	0	0
T6	3924560	0	0	0
T7	1389420	0	0	0
T8	134064	0	0	0
T16	0	542	0	0
T18	0	322	0	0
T20	0	563	0	0
T21	0	632	0	0
T22	0	374	0	0
T25	572720	0	0	0
T27	0	31	0	0
T30	0	186	0	0
T49	0	37	0	0
T50	0	687	0	0
T55	106340	0	0	0
T63	0	271	0	0
T65	0	34	0	0
T69	0	31	0	0
T83	0	272	0	0
T87	0	448	0	0
T88	0	268	0	0
T89	0	376	0	0
T90	0	56	0	0
T91	0	427	0	0
T92	0	139	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3674	0	0
T4	221678	1	0	0
T5	83487	0	0	0
T6	981140	0	0	0
T7	347355	0	0	0
T8	33516	0	0	0
T16	733072	1	0	0
T17	1106658	0	0	0
T18	0	3	0	0
T20	45918	4	0	0
T21	0	8	0	0
T22	0	3	0	0
T25	143180	0	0	0
T26	3556	0	0	0
T27	0	1	0	0
T28	0	4	0	0
T30	1125266	0	0	0
T31	0	8	0	0
T43	0	7	0	0
T48	334298	0	0	0
T49	0	1	0	0
T50	0	3	0	0
T54	242786	0	0	0
T55	26585	0	0	0
T63	0	2	0	0
T65	91383	0	0	0
T68	59560	0	0	0
T69	0	1	0	0
T83	0	1	0	0
T85	74182	0	0	0
T86	7258	0	0	0
T87	11062	2	0	0
T88	4542	2	0	0
T89	0	5	0	0
T90	0	1	0	0
T91	0	1	0	0
T92	0	1	0	0
T93	27303	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	235	0	0
T1	1183332	2	0	0
T2	99488	0	0	0
T3	648930	0	0	0
T4	443356	0	0	0
T5	166974	0	0	0
T6	1962280	0	0	0
T7	694710	0	0	0
T8	67032	0	0	0
T15	373490	0	0	0
T16	366536	1	0	0
T19	0	2	0	0
T20	0	1	0	0
T25	286360	0	0	0
T30	1125266	1	0	0
T31	0	1	0	0
T34	0	2	0	0
T43	0	3	0	0
T45	0	4	0	0
T48	334298	0	0	0
T51	0	2	0	0
T54	242786	0	0	0
T55	53170	0	0	0
T56	180786	0	0	0
T65	0	1	0	0
T66	21935	0	0	0
T69	40765	0	0	0
T84	0	1	0	0
T87	11062	1	0	0
T93	27303	0	0	0
T94	0	1	0	0
T95	0	1	0	0
T96	0	2	0	0
T97	0	1	0	0
T98	0	1	0	0
T99	0	1	0	0
T100	0	1	0	0
T101	0	1	0	0
T102	4458	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2366664	2366608	0	0
T2	198976	198452	0	0
T3	1297860	1297532	0	0
T4	886712	886668	0	0
T5	333948	333576	0	0
T6	3924560	3924188	0	0
T7	1389420	1389380	0	0
T8	134064	133764	0	0
T25	572720	572680	0	0
T55	106340	106024	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2366664	2366608	0	0
T2	198976	198452	0	0
T3	1297860	1297532	0	0
T4	886712	886668	0	0
T5	333948	333576	0	0
T6	3924560	3924188	0	0
T7	1389420	1389380	0	0
T8	134064	133764	0	0
T25	572720	572680	0	0
T55	106340	106024	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	97	96.04
CONT_ASSIGN	83	1	1	100.00
ALWAYS	132	89	85	95.51
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
ALWAYS	303	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
83	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
142	1	1
146	1	1
147	1	1
149	1	1
150	1	1
151	1	1
152	1	1
155	1	1
156	1	1
157	1	1
			MISSING_ELSE
167	1	1
169	1	1
170	1	1
171	1	1
172	1	1
173	1	1
176	1	1
177	1	1
179	1	1
180	1	1
185	1	1
186	1	1
187	1	1
188	1	1
189	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
			MISSING_ELSE
202	1	1
203	1	1
204	1	1
205	1	1
206	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
			MISSING_ELSE
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
226	1	1
227	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
			MISSING_ELSE
236	1	1
237	1	1
238	1	1
239	1	1
240	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
			MISSING_ELSE
256	1	1
257	1	1
258	1	1
259	1	1
			MISSING_ELSE
266	0	1
267	0	1
281	1	1
282	0	1
283	0	1
			MISSING_ELSE
290	4	4
293	4	4
303	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	35	77.78
Logical	45	35	77.78
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T3

 LINE       64
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

 LINE       149
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T5

 LINE       155
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T5
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T1,T4,T55
1	1	1	Covered	T1,T4,T65

 LINE       169
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T65
0	1	Covered	T1,T65,T45
1	0	Covered	T15,T21,T22

 LINE       169
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T65
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T15,T21,T22

 LINE       169
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T65
1	0	Not Covered
1	1	Covered	T1,T65,T45

 LINE       189
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T7

 LINE       206
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T8,T25

 LINE       223
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T65

 LINE       240
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T8
1	Covered	T1,T4,T5

 LINE       281
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       293
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T5,T8

 LINE       293
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T4,T16

 LINE       293
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T4,T8

 LINE       293
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T4,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	7	87.50	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	282	Not Covered
IdleSt	179	Covered	T1,T2,T3
Phase0St	150	Covered	T1,T4,T5
Phase1St	196	Covered	T1,T4,T5
Phase2St	213	Covered	T1,T4,T5
Phase3St	231	Covered	T1,T4,T5
TerminalSt	247	Covered	T1,T4,T5
TimeoutSt	157	Covered	T1,T4,T65

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	282	Not Covered
IdleSt->Phase0St	150	Covered	T1,T4,T5
IdleSt->TimeoutSt	157	Covered	T1,T4,T65
Phase0St->FsmErrorSt	282	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	192	Covered	T101,T35,T103
Phase0St->Phase1St	196	Covered	T1,T4,T5
Phase1St->FsmErrorSt	282	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	209	Covered	T16,T66,T104
Phase1St->Phase2St	213	Covered	T1,T4,T5
Phase2St->FsmErrorSt	282	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	227	Covered	T45,T99,T105
Phase2St->Phase3St	231	Covered	T1,T4,T5
Phase3St->FsmErrorSt	282	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	243	Covered	T10,T106,T35
Phase3St->TerminalSt	247	Covered	T1,T4,T5
TerminalSt->FsmErrorSt	282	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	259	Covered	T1,T4,T25
TimeoutSt->FsmErrorSt	282	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	179	Covered	T1,T4,T88
TimeoutSt->Phase0St	170	Covered	T1,T65,T15

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	23	88.46
CASE	142	22	20	90.91
IF	281	2	1	50.00
IF	303	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	142	case (state_q)
-2-:	149	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	155	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	169	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	176	if (timeout_en_i)
-6-:	191	if (clr_i)
-7-:	195	if (cnt_ge)
-8-:	208	if (clr_i)
-9-:	212	if (cnt_ge)
-10-:	226	if (clr_i)
-11-:	230	if (cnt_ge)
-12-:	242	if (clr_i)
-13-:	246	if (cnt_ge)
-14-:	258	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T65
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T65,T15
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T65
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T4,T88,T87
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T101,T35,T103
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T4,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T4,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T16,T66,T104
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T4,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T4,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T45,T99,T105
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T4,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T10,T106,T35
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T4,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T25,T16
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T4,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	281	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	303	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	14	82.35
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	14	82.35

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	611713173	0	0	0
CheckAccumTrig0_A	611713173	800	0	0
CheckAccumTrig1_A	611713173	66	0	0
CheckClr_A	611713173	386	0	0
CheckEn_A	611713173	240067758	0	0
CheckPhase0_A	611713173	918	0	0
CheckPhase1_A	611713173	897	0	0
CheckPhase2_A	611713173	880	0	0
CheckPhase3_A	611713173	868	0	0
CheckTimeout0_A	611713173	1234	0	0
CheckTimeoutSt1_A	611713173	118169	0	0
CheckTimeoutSt2_A	611713173	1105	0	0
CheckTimeoutStTrig_A	611713173	61	0	0
ErrorStAllEscAsserted_A	611713173	0	0	0
ErrorStIsTerminal_A	611713173	0	0	0
EscStateOut_A	611713173	611643977	0	0
u_state_regs_A	611713173	611643977	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	800	0	0
T1	591666	6	0	0
T2	49744	0	0	0
T3	324465	0	0	0
T4	221678	4	0	0
T5	83487	1	0	0
T6	981140	0	0	0
T7	347355	1	0	0
T8	33516	1	0	0
T16	0	12	0	0
T25	143180	1	0	0
T26	0	1	0	0
T55	26585	1	0	0
T68	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	66	0	0
T15	373490	1	0	0
T21	34052	3	0	0
T22	749110	1	0	0
T45	0	1	0	0
T51	0	4	0	0
T57	24147	0	0	0
T59	613339	0	0	0
T60	538389	0	0	0
T61	551205	0	0	0
T71	0	4	0	0
T72	0	3	0	0
T74	0	1	0	0
T76	0	1	0	0
T78	0	1	0	0
T80	290772	0	0	0
T81	60746	0	0	0
T82	2708	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	386	0	0
T1	591666	1	0	0
T2	49744	0	0	0
T3	324465	0	0	0
T4	221678	0	0	0
T5	83487	0	0	0
T6	981140	0	0	0
T7	347355	0	0	0
T8	33516	0	0	0
T15	0	2	0	0
T16	0	3	0	0
T21	0	4	0	0
T22	0	2	0	0
T25	143180	1	0	0
T27	0	1	0	0
T55	26585	0	0	0
T64	0	2	0	0
T66	0	1	0	0
T69	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	240067758	0	0
T1	591666	433094	0	0
T2	49744	3070	0	0
T3	324465	288450	0	0
T4	221678	87473	0	0
T5	83487	5354	0	0
T6	981140	981046	0	0
T7	347355	9965	0	0
T8	33516	7805	0	0
T25	143180	582	0	0
T55	26585	10311	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	918	0	0
T1	591666	7	0	0
T2	49744	0	0	0
T3	324465	0	0	0
T4	221678	4	0	0
T5	83487	1	0	0
T6	981140	0	0	0
T7	347355	1	0	0
T8	33516	1	0	0
T16	0	12	0	0
T25	143180	1	0	0
T55	26585	1	0	0
T65	0	1	0	0
T68	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	897	0	0
T1	591666	7	0	0
T2	49744	0	0	0
T3	324465	0	0	0
T4	221678	4	0	0
T5	83487	1	0	0
T6	981140	0	0	0
T7	347355	1	0	0
T8	33516	1	0	0
T16	0	11	0	0
T25	143180	1	0	0
T55	26585	1	0	0
T65	0	1	0	0
T68	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	880	0	0
T1	591666	7	0	0
T2	49744	0	0	0
T3	324465	0	0	0
T4	221678	4	0	0
T5	83487	1	0	0
T6	981140	0	0	0
T7	347355	1	0	0
T8	33516	1	0	0
T16	0	11	0	0
T25	143180	1	0	0
T55	26585	1	0	0
T65	0	1	0	0
T68	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	868	0	0
T1	591666	7	0	0
T2	49744	0	0	0
T3	324465	0	0	0
T4	221678	4	0	0
T5	83487	1	0	0
T6	981140	0	0	0
T7	347355	1	0	0
T8	33516	1	0	0
T16	0	11	0	0
T25	143180	1	0	0
T55	26585	1	0	0
T65	0	1	0	0
T68	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	1234	0	0
T1	591666	2	0	0
T2	49744	0	0	0
T3	324465	0	0	0
T4	221678	1	0	0
T5	83487	0	0	0
T6	981140	0	0	0
T7	347355	0	0	0
T8	33516	0	0	0
T15	0	1	0	0
T21	0	7	0	0
T22	0	4	0	0
T25	143180	0	0	0
T55	26585	0	0	0
T65	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T90	0	1	0	0
T91	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	118169	0	0
T1	591666	92	0	0
T2	49744	0	0	0
T3	324465	0	0	0
T4	221678	152	0	0
T5	83487	0	0	0
T6	981140	0	0	0
T7	347355	0	0	0
T8	33516	0	0	0
T21	0	347	0	0
T22	0	374	0	0
T25	143180	0	0	0
T55	26585	0	0	0
T65	0	34	0	0
T87	0	210	0	0
T88	0	134	0	0
T90	0	56	0	0
T91	0	219	0	0
T92	0	139	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	1105	0	0
T4	221678	1	0	0
T5	83487	0	0	0
T6	981140	0	0	0
T7	347355	0	0	0
T8	33516	0	0	0
T16	366536	0	0	0
T21	0	4	0	0
T22	0	3	0	0
T25	143180	0	0	0
T31	0	8	0	0
T43	0	1	0	0
T55	26585	0	0	0
T65	91383	0	0	0
T68	29780	0	0	0
T87	0	1	0	0
T88	0	1	0	0
T90	0	1	0	0
T91	0	1	0	0
T92	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	61	0	0
T1	591666	1	0	0
T2	49744	0	0	0
T3	324465	0	0	0
T4	221678	0	0	0
T5	83487	0	0	0
T6	981140	0	0	0
T7	347355	0	0	0
T8	33516	0	0	0
T25	143180	0	0	0
T34	0	2	0	0
T45	0	2	0	0
T51	0	2	0	0
T55	26585	0	0	0
T65	0	1	0	0
T94	0	1	0	0
T98	0	1	0	0
T99	0	1	0	0
T100	0	1	0	0
T101	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	611643977	0	0
T1	591666	591652	0	0
T2	49744	49613	0	0
T3	324465	324383	0	0
T4	221678	221667	0	0
T5	83487	83394	0	0
T6	981140	981047	0	0
T7	347355	347345	0	0
T8	33516	33441	0	0
T25	143180	143170	0	0
T55	26585	26506	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	611643977	0	0
T1	591666	591652	0	0
T2	49744	49613	0	0
T3	324465	324383	0	0
T4	221678	221667	0	0
T5	83487	83394	0	0
T6	981140	981047	0	0
T7	347355	347345	0	0
T8	33516	33441	0	0
T25	143180	143170	0	0
T55	26585	26506	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	97	96.04
CONT_ASSIGN	83	1	1	100.00
ALWAYS	132	89	85	95.51
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
ALWAYS	303	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
83	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
142	1	1
146	1	1
147	1	1
149	1	1
150	1	1
151	1	1
152	1	1
155	1	1
156	1	1
157	1	1
			MISSING_ELSE
167	1	1
169	1	1
170	1	1
171	1	1
172	1	1
173	1	1
176	1	1
177	1	1
179	1	1
180	1	1
185	1	1
186	1	1
187	1	1
188	1	1
189	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
			MISSING_ELSE
202	1	1
203	1	1
204	1	1
205	1	1
206	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
			MISSING_ELSE
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
226	1	1
227	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
			MISSING_ELSE
236	1	1
237	1	1
238	1	1
239	1	1
240	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
			MISSING_ELSE
256	1	1
257	1	1
258	1	1
259	1	1
			MISSING_ELSE
266	0	1
267	0	1
281	1	1
282	0	1
283	0	1
			MISSING_ELSE
290	4	4
293	4	4
303	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	35	77.78
Logical	45	35	77.78
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       64
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       149
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T4

 LINE       155
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T16,T85
1	0	1	Covered	T1,T3,T7
1	1	0	Covered	T1,T4,T16
1	1	1	Covered	T1,T16,T20

 LINE       169
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T16,T20
0	1	Covered	T30,T87,T43
1	0	Covered	T1,T16,T21

 LINE       169
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T16,T20
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T16,T21

 LINE       169
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T20
1	0	Not Covered
1	1	Covered	T30,T87,T43

 LINE       189
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T16
1	Covered	T7,T25,T16

 LINE       206
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T7
1	Covered	T1,T16,T17

 LINE       223
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T7,T25
1	Covered	T1,T4,T16

 LINE       240
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T7
1	Covered	T16,T68,T15

 LINE       281
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       293
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T16,T17

 LINE       293
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T16,T30

 LINE       293
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T7,T16

 LINE       293
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T4,T25

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	7	87.50	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	282	Not Covered
IdleSt	179	Covered	T1,T2,T3
Phase0St	150	Covered	T1,T4,T7
Phase1St	196	Covered	T1,T4,T7
Phase2St	213	Covered	T1,T4,T7
Phase3St	231	Covered	T1,T4,T7
TerminalSt	247	Covered	T1,T4,T7
TimeoutSt	157	Covered	T1,T16,T20

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	282	Not Covered
IdleSt->Phase0St	150	Covered	T1,T4,T7
IdleSt->TimeoutSt	157	Covered	T1,T16,T20
Phase0St->FsmErrorSt	282	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	192	Covered	T27,T10,T72
Phase0St->Phase1St	196	Covered	T1,T4,T7
Phase1St->FsmErrorSt	282	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	209	Covered	T16,T49,T19
Phase1St->Phase2St	213	Covered	T1,T4,T7
Phase2St->FsmErrorSt	282	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	227	Covered	T27,T67,T45
Phase2St->Phase3St	231	Covered	T1,T4,T7
Phase3St->FsmErrorSt	282	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	243	Covered	T16,T15,T22
Phase3St->TerminalSt	247	Covered	T1,T4,T7
TerminalSt->FsmErrorSt	282	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	259	Covered	T1,T4,T16
TimeoutSt->FsmErrorSt	282	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	179	Covered	T1,T16,T20
TimeoutSt->Phase0St	170	Covered	T1,T16,T30

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	23	88.46
CASE	142	22	20	90.91
IF	281	2	1	50.00
IF	303	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	142	case (state_q)
-2-:	149	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	155	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	169	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	176	if (timeout_en_i)
-6-:	191	if (clr_i)
-7-:	195	if (cnt_ge)
-8-:	208	if (clr_i)
-9-:	212	if (cnt_ge)
-10-:	226	if (clr_i)
-11-:	230	if (cnt_ge)
-12-:	242	if (clr_i)
-13-:	246	if (cnt_ge)
-14-:	258	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T16,T20
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T16,T30
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T16,T20
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T16,T20,T87
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T27,T10,T107
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T4,T7
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T4,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T16,T49,T19
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T4,T7
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T4,T7
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T27,T67,T45
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T4,T7
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T4,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T16,T15,T22
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T4,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T4,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T16,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T4,T7
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	281	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	303	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	14	82.35
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	14	82.35

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	611713173	0	0	0
CheckAccumTrig0_A	611713173	509	0	0
CheckAccumTrig1_A	611713173	25	0	0
CheckClr_A	611713173	257	0	0
CheckEn_A	611713173	266682475	0	0
CheckPhase0_A	611713173	580	0	0
CheckPhase1_A	611713173	569	0	0
CheckPhase2_A	611713173	556	0	0
CheckPhase3_A	611713173	544	0	0
CheckTimeout0_A	611713173	1104	0	0
CheckTimeoutSt1_A	611713173	119305	0	0
CheckTimeoutSt2_A	611713173	1025	0	0
CheckTimeoutStTrig_A	611713173	52	0	0
ErrorStAllEscAsserted_A	611713173	0	0	0
ErrorStIsTerminal_A	611713173	0	0	0
EscStateOut_A	611713173	611643977	0	0
u_state_regs_A	611713173	611643977	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	509	0	0
T1	591666	6	0	0
T2	49744	0	0	0
T3	324465	0	0	0
T4	221678	1	0	0
T5	83487	0	0	0
T6	981140	0	0	0
T7	347355	1	0	0
T8	33516	0	0	0
T15	0	6	0	0
T16	0	7	0	0
T17	0	1	0	0
T25	143180	1	0	0
T55	26585	0	0	0
T56	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	25	0	0
T1	591666	1	0	0
T2	49744	0	0	0
T3	324465	0	0	0
T4	221678	0	0	0
T5	83487	0	0	0
T6	981140	0	0	0
T7	347355	0	0	0
T8	33516	0	0	0
T9	0	1	0	0
T10	0	1	0	0
T16	0	1	0	0
T21	0	1	0	0
T25	143180	0	0	0
T52	0	1	0	0
T55	26585	0	0	0
T73	0	1	0	0
T75	0	4	0	0
T77	0	1	0	0
T79	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	257	0	0
T1	591666	3	0	0
T2	49744	0	0	0
T3	324465	0	0	0
T4	221678	0	0	0
T5	83487	0	0	0
T6	981140	0	0	0
T7	347355	0	0	0
T8	33516	0	0	0
T15	0	4	0	0
T16	0	4	0	0
T18	0	2	0	0
T21	0	2	0	0
T22	0	3	0	0
T25	143180	0	0	0
T27	0	3	0	0
T43	0	1	0	0
T49	0	2	0	0
T55	26585	0	0	0
T84	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	266682475	0	0
T1	591666	458457	0	0
T2	49744	3091	0	0
T3	324465	35645	0	0
T4	221678	139674	0	0
T5	83487	83393	0	0
T6	981140	981046	0	0
T7	347355	6055	0	0
T8	33516	33440	0	0
T25	143180	7093	0	0
T55	26585	26505	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	580	0	0
T1	591666	7	0	0
T2	49744	0	0	0
T3	324465	0	0	0
T4	221678	1	0	0
T5	83487	0	0	0
T6	981140	0	0	0
T7	347355	1	0	0
T8	33516	0	0	0
T16	0	8	0	0
T17	0	1	0	0
T25	143180	1	0	0
T30	0	1	0	0
T55	26585	0	0	0
T68	0	1	0	0
T69	0	1	0	0
T87	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	569	0	0
T1	591666	7	0	0
T2	49744	0	0	0
T3	324465	0	0	0
T4	221678	1	0	0
T5	83487	0	0	0
T6	981140	0	0	0
T7	347355	1	0	0
T8	33516	0	0	0
T16	0	7	0	0
T17	0	1	0	0
T25	143180	1	0	0
T30	0	1	0	0
T55	26585	0	0	0
T68	0	1	0	0
T69	0	1	0	0
T87	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	556	0	0
T1	591666	7	0	0
T2	49744	0	0	0
T3	324465	0	0	0
T4	221678	1	0	0
T5	83487	0	0	0
T6	981140	0	0	0
T7	347355	1	0	0
T8	33516	0	0	0
T16	0	7	0	0
T17	0	1	0	0
T25	143180	1	0	0
T30	0	1	0	0
T55	26585	0	0	0
T68	0	1	0	0
T69	0	1	0	0
T87	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	544	0	0
T1	591666	7	0	0
T2	49744	0	0	0
T3	324465	0	0	0
T4	221678	1	0	0
T5	83487	0	0	0
T6	981140	0	0	0
T7	347355	1	0	0
T8	33516	0	0	0
T16	0	6	0	0
T17	0	1	0	0
T25	143180	1	0	0
T30	0	1	0	0
T55	26585	0	0	0
T68	0	1	0	0
T69	0	1	0	0
T87	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	1104	0	0
T1	591666	2	0	0
T2	49744	0	0	0
T3	324465	0	0	0
T4	221678	0	0	0
T5	83487	0	0	0
T6	981140	0	0	0
T7	347355	0	0	0
T8	33516	0	0	0
T16	0	2	0	0
T20	0	2	0	0
T21	0	2	0	0
T25	143180	0	0	0
T27	0	1	0	0
T30	0	1	0	0
T49	0	1	0	0
T55	26585	0	0	0
T63	0	2	0	0
T69	0	1	0	0
T87	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	119305	0	0
T1	591666	81	0	0
T2	49744	0	0	0
T3	324465	0	0	0
T4	221678	0	0	0
T5	83487	0	0	0
T6	981140	0	0	0
T7	347355	0	0	0
T8	33516	0	0	0
T16	0	183	0	0
T20	0	294	0	0
T21	0	79	0	0
T25	143180	0	0	0
T27	0	31	0	0
T30	0	186	0	0
T49	0	37	0	0
T55	26585	0	0	0
T63	0	271	0	0
T69	0	31	0	0
T87	0	238	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	1025	0	0
T16	366536	1	0	0
T17	553329	0	0	0
T20	22959	2	0	0
T21	0	1	0	0
T26	3556	0	0	0
T27	0	1	0	0
T28	0	4	0	0
T30	562633	0	0	0
T49	0	1	0	0
T54	121393	0	0	0
T63	0	2	0	0
T68	29780	0	0	0
T69	0	1	0	0
T85	74182	0	0	0
T86	3629	0	0	0
T87	0	1	0	0
T88	2271	0	0	0
T89	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	52	0	0
T15	373490	0	0	0
T19	0	1	0	0
T30	562633	1	0	0
T31	0	1	0	0
T43	0	2	0	0
T45	0	1	0	0
T48	334298	0	0	0
T54	121393	0	0	0
T56	180786	0	0	0
T66	21935	0	0	0
T69	40765	0	0	0
T84	0	1	0	0
T87	11062	1	0	0
T93	27303	0	0	0
T95	0	1	0	0
T96	0	2	0	0
T97	0	1	0	0
T102	4458	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	611643977	0	0
T1	591666	591652	0	0
T2	49744	49613	0	0
T3	324465	324383	0	0
T4	221678	221667	0	0
T5	83487	83394	0	0
T6	981140	981047	0	0
T7	347355	347345	0	0
T8	33516	33441	0	0
T25	143180	143170	0	0
T55	26585	26506	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	611643977	0	0
T1	591666	591652	0	0
T2	49744	49613	0	0
T3	324465	324383	0	0
T4	221678	221667	0	0
T5	83487	83394	0	0
T6	981140	981047	0	0
T7	347355	347345	0	0
T8	33516	33441	0	0
T25	143180	143170	0	0
T55	26585	26506	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	97	96.04
CONT_ASSIGN	83	1	1	100.00
ALWAYS	132	89	85	95.51
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
ALWAYS	303	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
83	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
142	1	1
146	1	1
147	1	1
149	1	1
150	1	1
151	1	1
152	1	1
155	1	1
156	1	1
157	1	1
			MISSING_ELSE
167	1	1
169	1	1
170	1	1
171	1	1
172	1	1
173	1	1
176	1	1
177	1	1
179	1	1
180	1	1
185	1	1
186	1	1
187	1	1
188	1	1
189	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
			MISSING_ELSE
202	1	1
203	1	1
204	1	1
205	1	1
206	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
			MISSING_ELSE
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
226	1	1
227	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
			MISSING_ELSE
236	1	1
237	1	1
238	1	1
239	1	1
240	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
			MISSING_ELSE
256	1	1
257	1	1
258	1	1
259	1	1
			MISSING_ELSE
266	0	1
267	0	1
281	1	1
282	0	1
283	0	1
			MISSING_ELSE
290	4	4
293	4	4
303	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	35	77.78
Logical	45	35	77.78
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T8
1	1	Covered	T1,T2,T3

 LINE       64
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T8

 LINE       149
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T8,T7

 LINE       155
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T16,T85
1	0	1	Covered	T1,T4,T6
1	1	0	Covered	T1,T4,T16
1	1	1	Covered	T1,T16,T20

 LINE       169
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T16,T20
0	1	Covered	T1,T16,T20
1	0	Covered	T22,T45,T19

 LINE       169
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T16,T20
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T22,T45,T19

 LINE       169
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T20
1	0	Not Covered
1	1	Covered	T1,T16,T20

 LINE       189
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T8
1	Covered	T16,T54,T69

 LINE       206
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T8,T7
1	Covered	T1,T61,T21

 LINE       223
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T25
1	Covered	T4,T8,T7

 LINE       240
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T8
1	Covered	T4,T25,T60

 LINE       281
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       293
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T4,T8,T16

 LINE       293
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T25,T16

 LINE       293
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T8,T7

 LINE       293
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T4,T7,T25

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	7	87.50	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	282	Not Covered
IdleSt	179	Covered	T1,T2,T3
Phase0St	150	Covered	T1,T4,T8
Phase1St	196	Covered	T1,T4,T8
Phase2St	213	Covered	T1,T4,T8
Phase3St	231	Covered	T1,T4,T8
TerminalSt	247	Covered	T1,T4,T8
TimeoutSt	157	Covered	T1,T16,T20

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	282	Not Covered
IdleSt->Phase0St	150	Covered	T4,T8,T7
IdleSt->TimeoutSt	157	Covered	T1,T16,T20
Phase0St->FsmErrorSt	282	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	192	Covered	T20,T70,T108
Phase0St->Phase1St	196	Covered	T1,T4,T8
Phase1St->FsmErrorSt	282	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	209	Covered	T109,T35,T110
Phase1St->Phase2St	213	Covered	T1,T4,T8
Phase2St->FsmErrorSt	282	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	227	Covered	T33,T111,T112
Phase2St->Phase3St	231	Covered	T1,T4,T8
Phase3St->FsmErrorSt	282	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	243	Covered	T113,T114,T115
Phase3St->TerminalSt	247	Covered	T1,T4,T8
TerminalSt->FsmErrorSt	282	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	259	Covered	T1,T4,T25
TimeoutSt->FsmErrorSt	282	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	179	Covered	T1,T20,T88
TimeoutSt->Phase0St	170	Covered	T1,T16,T20

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	23	88.46
CASE	142	22	20	90.91
IF	281	2	1	50.00
IF	303	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	142	case (state_q)
-2-:	149	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	155	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	169	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	176	if (timeout_en_i)
-6-:	191	if (clr_i)
-7-:	195	if (cnt_ge)
-8-:	208	if (clr_i)
-9-:	212	if (cnt_ge)
-10-:	226	if (clr_i)
-11-:	230	if (cnt_ge)
-12-:	242	if (clr_i)
-13-:	246	if (cnt_ge)
-14-:	258	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T8,T7
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T16,T20
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T16,T20
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T16,T20
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T20,T88,T21
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T20,T108,T35
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T4,T8
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T4,T8
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T109,T35,T110
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T4,T8
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T4,T8
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T33,T111,T112
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T4,T8
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T4,T8
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T113,T114,T115
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T4,T8
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T4,T8
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T25,T69,T56
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T4,T8
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	281	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	303	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	14	82.35
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	14	82.35

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	611713173	0	0	0
CheckAccumTrig0_A	611713173	476	0	0
CheckAccumTrig1_A	611713173	31	0	0
CheckClr_A	611713173	225	0	0
CheckEn_A	611713173	285686337	0	0
CheckPhase0_A	611713173	553	0	0
CheckPhase1_A	611713173	540	0	0
CheckPhase2_A	611713173	529	0	0
CheckPhase3_A	611713173	522	0	0
CheckTimeout0_A	611713173	711	0	0
CheckTimeoutSt1_A	611713173	70949	0	0
CheckTimeoutSt2_A	611713173	618	0	0
CheckTimeoutStTrig_A	611713173	59	0	0
ErrorStAllEscAsserted_A	611713173	0	0	0
ErrorStIsTerminal_A	611713173	0	0	0
EscStateOut_A	611713173	611643977	0	0
u_state_regs_A	611713173	611643977	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	476	0	0
T4	221678	2	0	0
T5	83487	0	0	0
T6	981140	0	0	0
T7	347355	1	0	0
T8	33516	1	0	0
T16	366536	2	0	0
T17	0	1	0	0
T25	143180	1	0	0
T30	0	1	0	0
T54	0	1	0	0
T55	26585	0	0	0
T56	0	2	0	0
T65	91383	0	0	0
T68	29780	0	0	0
T69	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	31	0	0
T10	0	1	0	0
T19	0	1	0	0
T22	749110	1	0	0
T23	270290	0	0	0
T27	145557	0	0	0
T45	0	2	0	0
T49	469963	0	0	0
T52	0	1	0	0
T62	761635	0	0	0
T63	229444	0	0	0
T70	0	2	0	0
T80	290772	0	0	0
T81	60746	0	0	0
T82	2708	0	0	0
T97	0	1	0	0
T98	0	1	0	0
T116	0	1	0	0
T117	0	1	0	0
T118	58442	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	225	0	0
T16	366536	0	0	0
T17	553329	0	0	0
T20	22959	1	0	0
T22	0	8	0	0
T25	143180	1	0	0
T26	3556	0	0	0
T55	26585	0	0	0
T56	0	1	0	0
T60	0	1	0	0
T61	0	3	0	0
T63	0	1	0	0
T64	0	3	0	0
T65	91383	0	0	0
T68	29780	0	0	0
T69	0	1	0	0
T83	0	2	0	0
T85	74182	0	0	0
T86	3629	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	285686337	0	0
T1	591666	583687	0	0
T2	49744	3103	0	0
T3	324465	324382	0	0
T4	221678	130383	0	0
T5	83487	83393	0	0
T6	981140	59308	0	0
T7	347355	2158	0	0
T8	33516	590	0	0
T25	143180	142288	0	0
T55	26585	26505	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	553	0	0
T1	591666	1	0	0
T2	49744	0	0	0
T3	324465	0	0	0
T4	221678	2	0	0
T5	83487	0	0	0
T6	981140	0	0	0
T7	347355	1	0	0
T8	33516	1	0	0
T16	0	3	0	0
T17	0	1	0	0
T25	143180	1	0	0
T30	0	1	0	0
T54	0	1	0	0
T55	26585	0	0	0
T69	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	540	0	0
T1	591666	1	0	0
T2	49744	0	0	0
T3	324465	0	0	0
T4	221678	2	0	0
T5	83487	0	0	0
T6	981140	0	0	0
T7	347355	1	0	0
T8	33516	1	0	0
T16	0	3	0	0
T17	0	1	0	0
T25	143180	1	0	0
T30	0	1	0	0
T54	0	1	0	0
T55	26585	0	0	0
T69	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	529	0	0
T1	591666	1	0	0
T2	49744	0	0	0
T3	324465	0	0	0
T4	221678	2	0	0
T5	83487	0	0	0
T6	981140	0	0	0
T7	347355	1	0	0
T8	33516	1	0	0
T16	0	3	0	0
T17	0	1	0	0
T25	143180	1	0	0
T30	0	1	0	0
T54	0	1	0	0
T55	26585	0	0	0
T69	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	522	0	0
T1	591666	1	0	0
T2	49744	0	0	0
T3	324465	0	0	0
T4	221678	2	0	0
T5	83487	0	0	0
T6	981140	0	0	0
T7	347355	1	0	0
T8	33516	1	0	0
T16	0	3	0	0
T17	0	1	0	0
T25	143180	1	0	0
T30	0	1	0	0
T54	0	1	0	0
T55	26585	0	0	0
T69	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	711	0	0
T1	591666	2	0	0
T2	49744	0	0	0
T3	324465	0	0	0
T4	221678	0	0	0
T5	83487	0	0	0
T6	981140	0	0	0
T7	347355	0	0	0
T8	33516	0	0	0
T16	0	1	0	0
T20	0	3	0	0
T21	0	3	0	0
T22	0	1	0	0
T25	143180	0	0	0
T50	0	3	0	0
T55	26585	0	0	0
T83	0	2	0	0
T88	0	1	0	0
T89	0	2	0	0
T91	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	70949	0	0
T1	591666	718	0	0
T2	49744	0	0	0
T3	324465	0	0	0
T4	221678	0	0	0
T5	83487	0	0	0
T6	981140	0	0	0
T7	347355	0	0	0
T8	33516	0	0	0
T16	0	359	0	0
T18	0	322	0	0
T20	0	269	0	0
T21	0	206	0	0
T25	143180	0	0	0
T50	0	687	0	0
T55	26585	0	0	0
T83	0	272	0	0
T88	0	134	0	0
T89	0	376	0	0
T91	0	208	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	618	0	0
T17	553329	0	0	0
T18	0	3	0	0
T19	0	3	0	0
T20	22959	2	0	0
T21	0	3	0	0
T30	562633	0	0	0
T43	0	6	0	0
T45	0	2	0	0
T48	334298	0	0	0
T50	0	3	0	0
T54	121393	0	0	0
T69	40765	0	0	0
T83	0	1	0	0
T86	3629	0	0	0
T87	11062	0	0	0
T88	2271	1	0	0
T89	0	2	0	0
T93	27303	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	59	0	0
T1	591666	1	0	0
T2	49744	0	0	0
T3	324465	0	0	0
T4	221678	0	0	0
T5	83487	0	0	0
T6	981140	0	0	0
T7	347355	0	0	0
T8	33516	0	0	0
T16	0	1	0	0
T19	0	1	0	0
T20	0	1	0	0
T25	143180	0	0	0
T43	0	1	0	0
T45	0	1	0	0
T55	26585	0	0	0
T83	0	1	0	0
T91	0	2	0	0
T119	0	1	0	0
T120	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	611643977	0	0
T1	591666	591652	0	0
T2	49744	49613	0	0
T3	324465	324383	0	0
T4	221678	221667	0	0
T5	83487	83394	0	0
T6	981140	981047	0	0
T7	347355	347345	0	0
T8	33516	33441	0	0
T25	143180	143170	0	0
T55	26585	26506	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	611643977	0	0
T1	591666	591652	0	0
T2	49744	49613	0	0
T3	324465	324383	0	0
T4	221678	221667	0	0
T5	83487	83394	0	0
T6	981140	981047	0	0
T7	347355	347345	0	0
T8	33516	33441	0	0
T25	143180	143170	0	0
T55	26585	26506	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	97	96.04
CONT_ASSIGN	83	1	1	100.00
ALWAYS	132	89	85	95.51
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
ALWAYS	303	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
83	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
142	1	1
146	1	1
147	1	1
149	1	1
150	1	1
151	1	1
152	1	1
155	1	1
156	1	1
157	1	1
			MISSING_ELSE
167	1	1
169	1	1
170	1	1
171	1	1
172	1	1
173	1	1
176	1	1
177	1	1
179	1	1
180	1	1
185	1	1
186	1	1
187	1	1
188	1	1
189	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
			MISSING_ELSE
202	1	1
203	1	1
204	1	1
205	1	1
206	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
			MISSING_ELSE
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
226	1	1
227	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
			MISSING_ELSE
236	1	1
237	1	1
238	1	1
239	1	1
240	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
			MISSING_ELSE
256	1	1
257	1	1
258	1	1
259	1	1
			MISSING_ELSE
266	0	1
267	0	1
281	1	1
282	0	1
283	0	1
			MISSING_ELSE
290	4	4
293	4	4
303	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	36	80.00
Logical	45	36	80.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T8
1	1	Covered	T1,T2,T3

 LINE       64
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T8

 LINE       149
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T8

 LINE       155
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T65
1	0	1	Covered	T1,T6,T16
1	1	0	Covered	T1,T4,T16
1	1	1	Covered	T1,T16,T20

 LINE       169
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T16,T20
0	1	Covered	T16,T89,T28
1	0	Covered	T16,T15,T22

 LINE       169
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T16,T20
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T16,T15,T22

 LINE       169
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T20
1	0	Covered	T53
1	1	Covered	T16,T89,T28

 LINE       189
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T8
1	Covered	T1,T4,T16

 LINE       206
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T6
1	Covered	T1,T8,T16

 LINE       223
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T8
1	Covered	T4,T25,T16

 LINE       240
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T8
1	Covered	T6,T16,T68

 LINE       281
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       293
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T4,T6

 LINE       293
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T4,T25

 LINE       293
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T4,T16

 LINE       293
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T4,T8

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	7	87.50	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	282	Not Covered
IdleSt	179	Covered	T1,T2,T3
Phase0St	150	Covered	T1,T4,T8
Phase1St	196	Covered	T1,T4,T8
Phase2St	213	Covered	T1,T4,T8
Phase3St	231	Covered	T1,T4,T8
TerminalSt	247	Covered	T1,T4,T8
TimeoutSt	157	Covered	T1,T16,T20

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	282	Not Covered
IdleSt->Phase0St	150	Covered	T1,T4,T8
IdleSt->TimeoutSt	157	Covered	T1,T16,T20
Phase0St->FsmErrorSt	282	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	192	Covered	T1,T4,T16
Phase0St->Phase1St	196	Covered	T1,T4,T8
Phase1St->FsmErrorSt	282	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	209	Covered	T4,T98,T121
Phase1St->Phase2St	213	Covered	T1,T4,T8
Phase2St->FsmErrorSt	282	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	227	Covered	T28,T122,T123
Phase2St->Phase3St	231	Covered	T1,T4,T8
Phase3St->FsmErrorSt	282	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	243	Covered	T4,T27,T124
Phase3St->TerminalSt	247	Covered	T1,T4,T8
TerminalSt->FsmErrorSt	282	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	259	Covered	T1,T4,T16
TimeoutSt->FsmErrorSt	282	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	179	Covered	T1,T16,T20
TimeoutSt->Phase0St	170	Covered	T16,T15,T22

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	23	88.46
CASE	142	22	20	90.91
IF	281	2	1	50.00
IF	303	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	142	case (state_q)
-2-:	149	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	155	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	169	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	176	if (timeout_en_i)
-6-:	191	if (clr_i)
-7-:	195	if (cnt_ge)
-8-:	208	if (clr_i)
-9-:	212	if (cnt_ge)
-10-:	226	if (clr_i)
-11-:	230	if (cnt_ge)
-12-:	242	if (clr_i)
-13-:	246	if (cnt_ge)
-14-:	258	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T8
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T16,T20
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T16,T15,T22
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T16,T20
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T16,T20
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T4,T16,T56
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T4,T8
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T4,T8
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T4,T121,T125
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T4,T8
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T4,T8
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T28,T122,T123
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T4,T8
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T4,T8
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T4,T27,T124
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T4,T8
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T4,T8
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T16,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T4,T8
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	281	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	303	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	14	82.35
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	14	82.35

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	611713173	0	0	0
CheckAccumTrig0_A	611713173	481	0	0
CheckAccumTrig1_A	611713173	18	0	0
CheckClr_A	611713173	220	0	0
CheckEn_A	611713173	278108389	0	0
CheckPhase0_A	611713173	550	0	0
CheckPhase1_A	611713173	539	0	0
CheckPhase2_A	611713173	529	0	0
CheckPhase3_A	611713173	521	0	0
CheckTimeout0_A	611713173	1008	0	0
CheckTimeoutSt1_A	611713173	102530	0	0
CheckTimeoutSt2_A	611713173	926	0	0
CheckTimeoutStTrig_A	611713173	63	0	0
ErrorStAllEscAsserted_A	611713173	0	0	0
ErrorStIsTerminal_A	611713173	0	0	0
EscStateOut_A	611713173	611643977	0	0
u_state_regs_A	611713173	611643977	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	481	0	0
T1	591666	3	0	0
T2	49744	0	0	0
T3	324465	0	0	0
T4	221678	19	0	0
T5	83487	0	0	0
T6	981140	1	0	0
T7	347355	0	0	0
T8	33516	1	0	0
T16	0	4	0	0
T25	143180	1	0	0
T26	0	1	0	0
T48	0	1	0	0
T55	26585	0	0	0
T56	0	2	0	0
T68	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	18	0	0
T10	0	1	0	0
T12	0	1	0	0
T15	0	1	0	0
T16	366536	1	0	0
T17	553329	0	0	0
T20	22959	0	0	0
T22	0	1	0	0
T26	3556	0	0	0
T27	0	1	0	0
T30	562633	0	0	0
T54	121393	0	0	0
T68	29780	0	0	0
T85	74182	0	0	0
T86	3629	0	0	0
T88	2271	0	0	0
T107	0	1	0	0
T116	0	1	0	0
T126	0	1	0	0
T127	0	2	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	220	0	0
T4	221678	16	0	0
T5	83487	0	0	0
T6	981140	0	0	0
T7	347355	0	0	0
T8	33516	0	0	0
T15	0	1	0	0
T16	366536	2	0	0
T21	0	1	0	0
T25	143180	0	0	0
T27	0	4	0	0
T28	0	1	0	0
T55	26585	0	0	0
T56	0	1	0	0
T60	0	1	0	0
T65	91383	0	0	0
T68	29780	0	0	0
T89	0	1	0	0
T122	0	4	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	278108389	0	0
T1	591666	519102	0	0
T2	49744	3122	0	0
T3	324465	289336	0	0
T4	221678	128940	0	0
T5	83487	83393	0	0
T6	981140	2434	0	0
T7	347355	346526	0	0
T8	33516	594	0	0
T25	143180	4281	0	0
T55	26585	26505	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	550	0	0
T1	591666	2	0	0
T2	49744	0	0	0
T3	324465	0	0	0
T4	221678	16	0	0
T5	83487	0	0	0
T6	981140	1	0	0
T7	347355	0	0	0
T8	33516	1	0	0
T16	0	5	0	0
T25	143180	1	0	0
T26	0	1	0	0
T48	0	1	0	0
T55	26585	0	0	0
T56	0	1	0	0
T68	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	539	0	0
T1	591666	2	0	0
T2	49744	0	0	0
T3	324465	0	0	0
T4	221678	13	0	0
T5	83487	0	0	0
T6	981140	1	0	0
T7	347355	0	0	0
T8	33516	1	0	0
T16	0	5	0	0
T25	143180	1	0	0
T26	0	1	0	0
T48	0	1	0	0
T55	26585	0	0	0
T56	0	1	0	0
T68	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	529	0	0
T1	591666	2	0	0
T2	49744	0	0	0
T3	324465	0	0	0
T4	221678	13	0	0
T5	83487	0	0	0
T6	981140	1	0	0
T7	347355	0	0	0
T8	33516	1	0	0
T16	0	5	0	0
T25	143180	1	0	0
T26	0	1	0	0
T48	0	1	0	0
T55	26585	0	0	0
T56	0	1	0	0
T68	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	521	0	0
T1	591666	2	0	0
T2	49744	0	0	0
T3	324465	0	0	0
T4	221678	12	0	0
T5	83487	0	0	0
T6	981140	1	0	0
T7	347355	0	0	0
T8	33516	1	0	0
T16	0	5	0	0
T25	143180	1	0	0
T26	0	1	0	0
T48	0	1	0	0
T55	26585	0	0	0
T56	0	1	0	0
T68	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	1008	0	0
T1	591666	4	0	0
T2	49744	0	0	0
T3	324465	0	0	0
T4	221678	0	0	0
T5	83487	0	0	0
T6	981140	0	0	0
T7	347355	0	0	0
T8	33516	0	0	0
T15	0	1	0	0
T16	0	5	0	0
T20	0	3	0	0
T21	0	1	0	0
T22	0	3	0	0
T25	143180	0	0	0
T27	0	3	0	0
T28	0	1	0	0
T55	26585	0	0	0
T88	0	1	0	0
T89	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	102530	0	0
T1	591666	889	0	0
T2	49744	0	0	0
T3	324465	0	0	0
T4	221678	0	0	0
T5	83487	0	0	0
T6	981140	0	0	0
T7	347355	0	0	0
T8	33516	0	0	0
T15	0	4	0	0
T16	0	216	0	0
T20	0	410	0	0
T21	0	81	0	0
T22	0	101	0	0
T25	143180	0	0	0
T27	0	74	0	0
T28	0	228	0	0
T55	26585	0	0	0
T88	0	134	0	0
T89	0	84	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	926	0	0
T1	591666	4	0	0
T2	49744	0	0	0
T3	324465	0	0	0
T4	221678	0	0	0
T5	83487	0	0	0
T6	981140	0	0	0
T7	347355	0	0	0
T8	33516	0	0	0
T16	0	3	0	0
T20	0	3	0	0
T21	0	1	0	0
T22	0	2	0	0
T24	0	1	0	0
T25	143180	0	0	0
T27	0	2	0	0
T50	0	3	0	0
T55	26585	0	0	0
T88	0	1	0	0
T128	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	63	0	0
T9	0	1	0	0
T16	366536	1	0	0
T17	553329	0	0	0
T20	22959	0	0	0
T26	3556	0	0	0
T28	0	1	0	0
T30	562633	0	0	0
T32	0	1	0	0
T43	0	1	0	0
T45	0	2	0	0
T54	121393	0	0	0
T68	29780	0	0	0
T85	74182	0	0	0
T86	3629	0	0	0
T88	2271	0	0	0
T89	0	2	0	0
T91	0	1	0	0
T95	0	2	0	0
T96	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	611643977	0	0
T1	591666	591652	0	0
T2	49744	49613	0	0
T3	324465	324383	0	0
T4	221678	221667	0	0
T5	83487	83394	0	0
T6	981140	981047	0	0
T7	347355	347345	0	0
T8	33516	33441	0	0
T25	143180	143170	0	0
T55	26585	26506	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	611643977	0	0
T1	591666	591652	0	0
T2	49744	49613	0	0
T3	324465	324383	0	0
T4	221678	221667	0	0
T5	83487	83394	0	0
T6	981140	981047	0	0
T7	347355	347345	0	0
T8	33516	33441	0	0
T25	143180	143170	0	0
T55	26585	26506	0	0