Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.62	100.00	100.00	86.49			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
81.27	100.00		96.95			46.88	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	86.49			86.49

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.95	100.00	100.00	83.78			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
81.27	100.00		96.95			46.88	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	83.78			83.78

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.95	100.00	100.00	83.78			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
81.27	100.00		96.95			46.88	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	83.78			83.78

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.95	100.00	100.00	83.78			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
81.27	100.00		96.95			46.88	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	83.78			83.78

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T86,T102,T82
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	15119	0	0
DisabledNoTrigBkwd_A	2147483647	830030	0	0
DisabledNoTrigFwd_A	2147483647	1348465215	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15119	0	0
T17	553329	0	0	0
T30	562633	0	0	0
T48	334298	0	0	0
T51	642191	0	0	0
T54	121393	0	0	0
T66	21935	0	0	0
T69	40765	0	0	0
T73	47821	0	0	0
T82	2708	338	0	0
T86	3629	686	0	0
T87	11062	0	0	0
T88	2271	0	0	0
T93	27303	0	0	0
T99	145458	0	0	0
T102	0	1259	0	0
T204	0	1050	0	0
T205	0	336	0	0
T206	0	425	0	0
T207	4280	866	0	0
T208	0	921	0	0
T209	0	345	0	0
T210	0	421	0	0
T211	0	922	0	0
T212	0	885	0	0
T213	0	1234	0	0
T214	0	715	0	0
T215	0	180	0	0
T216	0	608	0	0
T217	0	594	0	0
T218	0	718	0	0
T219	0	1730	0	0
T220	0	886	0	0
T221	9567	0	0	0
T222	234042	0	0	0
T223	30914	0	0	0
T224	195349	0	0	0
T225	42256	0	0	0
T226	481132	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	830030	0	0
T1	2366664	907	0	0
T2	198976	0	0	0
T3	1297860	0	0	0
T4	886712	1551	0	0
T5	333948	4	0	0
T6	3924560	8	0	0
T7	1389420	808	0	0
T8	134064	43	0	0
T15	0	1900	0	0
T16	0	7446	0	0
T17	0	2	0	0
T25	572720	737	0	0
T26	0	1	0	0
T30	0	28	0	0
T48	0	27	0	0
T54	0	30	0	0
T55	106340	19	0	0
T56	0	1464	0	0
T65	0	5	0	0
T68	0	39	0	0
T69	0	11	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1348465215	0	0
T1	2366664	2107171	0	0
T2	198976	12390	0	0
T3	1297860	937816	0	0
T4	886712	506119	0	0
T5	333948	320179	0	0
T6	3924560	2023836	0	0
T7	1389420	1041304	0	0
T8	134064	95206	0	0
T25	572720	290937	0	0
T55	106340	89829	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T4,T5

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T86,T102,T205
1	1	Covered	T1,T4,T5

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	611713173	5030	0	0
DisabledNoTrigBkwd_A	611713173	247047	0	0
DisabledNoTrigFwd_A	611713173	312636045	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	5030	0	0
T17	553329	0	0	0
T30	562633	0	0	0
T48	334298	0	0	0
T54	121393	0	0	0
T66	21935	0	0	0
T69	40765	0	0	0
T86	3629	686	0	0
T87	11062	0	0	0
T88	2271	0	0	0
T93	27303	0	0	0
T102	0	1259	0	0
T205	0	336	0	0
T206	0	425	0	0
T217	0	594	0	0
T219	0	1730	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	247047	0	0
T1	591666	478	0	0
T2	49744	0	0	0
T3	324465	0	0	0
T4	221678	1455	0	0
T5	83487	4	0	0
T6	981140	0	0	0
T7	347355	4	0	0
T8	33516	8	0	0
T16	0	243	0	0
T25	143180	1	0	0
T55	26585	19	0	0
T65	0	5	0	0
T68	0	16	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	312636045	0	0
T1	591666	514041	0	0
T2	49744	3071	0	0
T3	324465	288451	0	0
T4	221678	103825	0	0
T5	83487	69997	0	0
T6	981140	981047	0	0
T7	347355	344580	0	0
T8	33516	28997	0	0
T25	143180	582	0	0
T55	26585	10311	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T8
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T207,T211,T216
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	611713173	3114	0	0
DisabledNoTrigBkwd_A	611713173	191985	0	0
DisabledNoTrigFwd_A	611713173	337234634	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	3114	0	0
T51	642191	0	0	0
T73	47821	0	0	0
T99	145458	0	0	0
T207	4280	866	0	0
T211	0	922	0	0
T216	0	608	0	0
T218	0	718	0	0
T221	9567	0	0	0
T222	234042	0	0	0
T223	30914	0	0	0
T224	195349	0	0	0
T225	42256	0	0	0
T226	481132	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	191985	0	0
T1	591666	271	0	0
T2	49744	0	0	0
T3	324465	0	0	0
T4	221678	4	0	0
T5	83487	0	0	0
T6	981140	0	0	0
T7	347355	791	0	0
T8	33516	0	0	0
T15	0	1900	0	0
T16	0	3317	0	0
T17	0	1	0	0
T25	143180	734	0	0
T55	26585	0	0	0
T56	0	1	0	0
T68	0	11	0	0
T69	0	7	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	337234634	0	0
T1	591666	485378	0	0
T2	49744	3092	0	0
T3	324465	35645	0	0
T4	221678	140984	0	0
T5	83487	83394	0	0
T6	981140	981047	0	0
T7	347355	6055	0	0
T8	33516	33441	0	0
T25	143180	7093	0	0
T55	26585	26506	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T4,T8

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T82,T209,T212
1	1	Covered	T1,T4,T8

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T8

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	611713173	1568	0	0
DisabledNoTrigBkwd_A	611713173	235852	0	0
DisabledNoTrigFwd_A	611713173	342594576	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	1568	0	0
T23	270290	0	0	0
T27	145557	0	0	0
T49	469963	0	0	0
T62	761635	0	0	0
T63	229444	0	0	0
T64	125347	0	0	0
T82	2708	338	0	0
T118	58442	0	0	0
T209	0	345	0	0
T212	0	885	0	0
T227	356758	0	0	0
T228	14261	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	235852	0	0
T1	591666	2	0	0
T2	49744	0	0	0
T3	324465	0	0	0
T4	221678	40	0	0
T5	83487	0	0	0
T6	981140	0	0	0
T7	347355	13	0	0
T8	33516	1	0	0
T16	0	2728	0	0
T17	0	1	0	0
T25	143180	1	0	0
T30	0	28	0	0
T54	0	30	0	0
T55	26585	0	0	0
T69	0	4	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	342594576	0	0
T1	591666	588650	0	0
T2	49744	3104	0	0
T3	324465	324383	0	0
T4	221678	131693	0	0
T5	83487	83394	0	0
T6	981140	59308	0	0
T7	347355	344143	0	0
T8	33516	32174	0	0
T25	143180	142288	0	0
T55	26585	26506	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T4,T8

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T204,T208,T210
1	1	Covered	T1,T4,T8

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T8

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	611713173	5407	0	0
DisabledNoTrigBkwd_A	611713173	155146	0	0
DisabledNoTrigFwd_A	611713173	355999960	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	5407	0	0
T9	511287	0	0	0
T32	54215	0	0	0
T94	15936	0	0	0
T204	3414	1050	0	0
T208	0	921	0	0
T210	0	421	0	0
T213	0	1234	0	0
T214	0	715	0	0
T215	0	180	0	0
T220	0	886	0	0
T229	34225	0	0	0
T230	10575	0	0	0
T231	16914	0	0	0
T232	19407	0	0	0
T233	33149	0	0	0
T234	117778	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	155146	0	0
T1	591666	156	0	0
T2	49744	0	0	0
T3	324465	0	0	0
T4	221678	52	0	0
T5	83487	0	0	0
T6	981140	8	0	0
T7	347355	0	0	0
T8	33516	34	0	0
T16	0	1158	0	0
T25	143180	1	0	0
T26	0	1	0	0
T48	0	27	0	0
T55	26585	0	0	0
T56	0	1463	0	0
T68	0	12	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611713173	355999960	0	0
T1	591666	519102	0	0
T2	49744	3123	0	0
T3	324465	289337	0	0
T4	221678	129617	0	0
T5	83487	83394	0	0
T6	981140	2434	0	0
T7	347355	346526	0	0
T8	33516	594	0	0
T25	143180	140974	0	0
T55	26585	26506	0	0