Unified Coverage Report :: Module :: prim_count

Module : prim_count

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
66.95			66.95

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_count_0/rtl/prim_count.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_ping_timer.u_prim_count_esc_cnt	21.62			21.62
tb.dut.gen_classes[0].u_esc_timer.u_prim_count	35.71			35.71
tb.dut.gen_classes[1].u_esc_timer.u_prim_count	35.71			35.71
tb.dut.gen_classes[2].u_esc_timer.u_prim_count	35.71			35.71
tb.dut.gen_classes[3].u_esc_timer.u_prim_count	35.71			35.71
tb.dut.gen_classes[1].u_accu.u_prim_count	83.78			83.78
tb.dut.gen_classes[2].u_accu.u_prim_count	83.78			83.78
tb.dut.gen_classes[3].u_accu.u_prim_count	83.78			83.78
tb.dut.gen_classes[0].u_accu.u_prim_count	86.49			86.49
tb.dut.u_ping_timer.u_prim_count_cnt	98.11			98.11

---

Module Instance : tb.dut.u_ping_timer.u_prim_count_esc_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
21.62			21.62

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
21.62			21.62

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.02	91.94	89.19		83.33	90.62	100.00	u_ping_timer

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
35.71			35.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
35.71			35.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.50	96.04	77.78		92.86	88.46	82.35	gen_classes[0].u_esc_timer

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
35.71			35.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
35.71			35.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.50	96.04	77.78		92.86	88.46	82.35	gen_classes[1].u_esc_timer

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
35.71			35.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
35.71			35.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.50	96.04	77.78		92.86	88.46	82.35	gen_classes[2].u_esc_timer

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
35.71			35.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
35.71			35.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.94	96.04	80.00		92.86	88.46	82.35	gen_classes[3].u_esc_timer

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_classes[1].u_accu.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.78			83.78

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.78			83.78

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	gen_classes[1].u_accu

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_classes[2].u_accu.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.78			83.78

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.78			83.78

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	gen_classes[2].u_accu

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_classes[3].u_accu.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.78			83.78

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.78			83.78

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	gen_classes[3].u_accu

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_classes[0].u_accu.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.49			86.49

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.49			86.49

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	gen_classes[0].u_accu

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ping_timer.u_prim_count_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.11			98.11

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.11			98.11

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.02	91.94	89.19		83.33	90.62	100.00	u_ping_timer

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_count ( parameter Width=16,ResetValue=0,EnableAlertTriggerSVA=0,DecrNeverTrue=0,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
21.62	21.62

tb.dut.u_ping_timer.u_prim_count_esc_cnt

SCORE	TOGGLE
98.11	98.11

tb.dut.u_ping_timer.u_prim_count_cnt

SCORE	TOGGLE
86.49	86.49

tb.dut.gen_classes[0].u_accu.u_prim_count

SCORE	TOGGLE
83.78	83.78

tb.dut.gen_classes[1].u_accu.u_prim_count

SCORE	TOGGLE
83.78	83.78

tb.dut.gen_classes[2].u_accu.u_prim_count

SCORE	TOGGLE
83.78	83.78

tb.dut.gen_classes[3].u_accu.u_prim_count

	Total	Covered	Percent
Totals	10	9	90.00
Total Bits	110	108	98.18
Total Bits 0->1	55	54	98.18
Total Bits 1->0	55	54	98.18

Ports	10	9	90.00
Port Bits	110	108	98.18
Port Bits 0->1	55	54	98.18
Port Bits 1->0	55	54	98.18

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
set_cnt_i[15:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
incr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
decr_en_i	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
step_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[15:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cnt_after_commit_o[15:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
err_o	No	No		No		OUTPUT

---

Toggle Coverage for Module : prim_count ( parameter Width=32,ResetValue=0,EnableAlertTriggerSVA=0,DecrNeverTrue=1,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
35.71	35.71

tb.dut.gen_classes[0].u_esc_timer.u_prim_count

SCORE	TOGGLE
35.71	35.71

tb.dut.gen_classes[1].u_esc_timer.u_prim_count

SCORE	TOGGLE
35.71	35.71

tb.dut.gen_classes[2].u_esc_timer.u_prim_count

SCORE	TOGGLE
35.71	35.71

tb.dut.gen_classes[3].u_esc_timer.u_prim_count

	Total	Covered	Percent
Totals	8	5	62.50
Total Bits	140	50	35.71
Total Bits 0->1	70	25	35.71
Total Bits 1->0	70	25	35.71

Ports	8	5	62.50
Port Bits	140	50	35.71
Port Bits 0->1	70	25	35.71
Port Bits 1->0	70	25	35.71

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
set_i	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
set_cnt_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[9:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
cnt_o[31:10]	No	No		No		OUTPUT
cnt_after_commit_o[9:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
cnt_after_commit_o[31:10]	No	No		No		OUTPUT
err_o	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.u_ping_timer.u_prim_count_esc_cnt

	Total	Covered	Percent
Totals	7	4	57.14
Total Bits	74	16	21.62
Total Bits 0->1	37	8	21.62
Total Bits 1->0	37	8	21.62

Ports	7	4	57.14
Port Bits	74	16	21.62
Port Bits 0->1	37	8	21.62
Port Bits 1->0	37	8	21.62

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T2,T3,T6	Yes	T2,T3,T6	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[1:0]	Yes	Yes	T2,T3,*T4	Yes	T2,T3,T4	OUTPUT
cnt_o[15:2]	No	No		No		OUTPUT
cnt_after_commit_o[1:0]	Yes	Yes	T2,T3,*T4	Yes	T2,T3,T4	OUTPUT
cnt_after_commit_o[15:2]	No	No		No		OUTPUT
err_o	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer.u_prim_count

	Total	Covered	Percent
Totals	8	5	62.50
Total Bits	140	50	35.71
Total Bits 0->1	70	25	35.71
Total Bits 1->0	70	25	35.71

Ports	8	5	62.50
Port Bits	140	50	35.71
Port Bits 0->1	70	25	35.71
Port Bits 1->0	70	25	35.71

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
set_i	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
set_cnt_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[9:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
cnt_o[31:10]	No	No		No		OUTPUT
cnt_after_commit_o[9:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
cnt_after_commit_o[31:10]	No	No		No		OUTPUT
err_o	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer.u_prim_count

	Total	Covered	Percent
Totals	8	5	62.50
Total Bits	140	50	35.71
Total Bits 0->1	70	25	35.71
Total Bits 1->0	70	25	35.71

Ports	8	5	62.50
Port Bits	140	50	35.71
Port Bits 0->1	70	25	35.71
Port Bits 1->0	70	25	35.71

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T4,T7	Yes	T1,T4,T7	INPUT
set_i	Yes	Yes	T1,T4,T7	Yes	T1,T4,T7	INPUT
set_cnt_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T4,T7	Yes	T1,T4,T7	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[9:0]	Yes	Yes	*T1,*T4,*T7	Yes	T1,T4,T7	OUTPUT
cnt_o[31:10]	No	No		No		OUTPUT
cnt_after_commit_o[9:0]	Yes	Yes	*T1,*T4,*T7	Yes	T1,T4,T7	OUTPUT
cnt_after_commit_o[31:10]	No	No		No		OUTPUT
err_o	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer.u_prim_count

	Total	Covered	Percent
Totals	8	5	62.50
Total Bits	140	50	35.71
Total Bits 0->1	70	25	35.71
Total Bits 1->0	70	25	35.71

Ports	8	5	62.50
Port Bits	140	50	35.71
Port Bits 0->1	70	25	35.71
Port Bits 1->0	70	25	35.71

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T4,T8	Yes	T1,T4,T8	INPUT
set_i	Yes	Yes	T1,T4,T8	Yes	T1,T4,T8	INPUT
set_cnt_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T4,T8	Yes	T1,T4,T8	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[9:0]	Yes	Yes	T1,*T4,*T8	Yes	T1,T4,T8	OUTPUT
cnt_o[31:10]	No	No		No		OUTPUT
cnt_after_commit_o[9:0]	Yes	Yes	T1,*T4,*T8	Yes	T1,T4,T8	OUTPUT
cnt_after_commit_o[31:10]	No	No		No		OUTPUT
err_o	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer.u_prim_count

	Total	Covered	Percent
Totals	8	5	62.50
Total Bits	140	50	35.71
Total Bits 0->1	70	25	35.71
Total Bits 1->0	70	25	35.71

Ports	8	5	62.50
Port Bits	140	50	35.71
Port Bits 0->1	70	25	35.71
Port Bits 1->0	70	25	35.71

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T4,T8	Yes	T1,T4,T8	INPUT
set_i	Yes	Yes	T1,T4,T8	Yes	T1,T4,T8	INPUT
set_cnt_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T4,T8	Yes	T1,T4,T8	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[9:0]	Yes	Yes	T1,T4,*T8	Yes	T1,T4,T8	OUTPUT
cnt_o[31:10]	No	No		No		OUTPUT
cnt_after_commit_o[9:0]	Yes	Yes	T1,T4,*T8	Yes	T1,T4,T8	OUTPUT
cnt_after_commit_o[31:10]	No	No		No		OUTPUT
err_o	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_classes[1].u_accu.u_prim_count

	Total	Covered	Percent
Totals	7	4	57.14
Total Bits	74	62	83.78
Total Bits 0->1	37	32	86.49
Total Bits 1->0	37	30	81.08

Ports	7	4	57.14
Port Bits	74	62	83.78
Port Bits 0->1	37	32	86.49
Port Bits 1->0	37	30	81.08

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[12:0]	Yes	Yes	*T1,*T3,*T4	Yes	T1,T3,T4	OUTPUT
cnt_o[13]	No	No		Yes	T9,T10	OUTPUT
cnt_o[15:14]	No	No		No		OUTPUT
cnt_after_commit_o[12:0]	Yes	Yes	*T1,*T3,*T4	Yes	T1,T3,T4	OUTPUT
cnt_after_commit_o[13]	No	No		Yes	T9,T10	OUTPUT
cnt_after_commit_o[15:14]	No	No		No		OUTPUT
err_o	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_classes[2].u_accu.u_prim_count

	Total	Covered	Percent
Totals	7	4	57.14
Total Bits	74	62	83.78
Total Bits 0->1	37	32	86.49
Total Bits 1->0	37	30	81.08

Ports	7	4	57.14
Port Bits	74	62	83.78
Port Bits 0->1	37	32	86.49
Port Bits 1->0	37	30	81.08

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T4,T6	Yes	T1,T4,T6	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T4,T8	Yes	T1,T4,T8	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[12:0]	Yes	Yes	*T1,*T4,*T8	Yes	T1,T4,T8	OUTPUT
cnt_o[13]	No	No		Yes	T11,T12,T13	OUTPUT
cnt_o[15:14]	No	No		No		OUTPUT
cnt_after_commit_o[12:0]	Yes	Yes	*T1,*T4,*T8	Yes	T1,T4,T8	OUTPUT
cnt_after_commit_o[13]	No	No		Yes	T11,T12,T13	OUTPUT
cnt_after_commit_o[15:14]	No	No		No		OUTPUT
err_o	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_classes[3].u_accu.u_prim_count

	Total	Covered	Percent
Totals	7	4	57.14
Total Bits	74	62	83.78
Total Bits 0->1	37	32	86.49
Total Bits 1->0	37	30	81.08

Ports	7	4	57.14
Port Bits	74	62	83.78
Port Bits 0->1	37	32	86.49
Port Bits 1->0	37	30	81.08

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T4,T8	Yes	T1,T4,T8	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[12:0]	Yes	Yes	*T1,*T4,*T8	Yes	T1,T4,T8	OUTPUT
cnt_o[13]	No	No		Yes	T14	OUTPUT
cnt_o[15:14]	No	No		No		OUTPUT
cnt_after_commit_o[12:0]	Yes	Yes	*T1,*T4,*T8	Yes	T1,T4,T8	OUTPUT
cnt_after_commit_o[13]	No	No		Yes	T14	OUTPUT
cnt_after_commit_o[15:14]	No	No		No		OUTPUT
err_o	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_classes[0].u_accu.u_prim_count

	Total	Covered	Percent
Totals	7	4	57.14
Total Bits	74	64	86.49
Total Bits 0->1	37	32	86.49
Total Bits 1->0	37	32	86.49

Ports	7	4	57.14
Port Bits	74	64	86.49
Port Bits 0->1	37	32	86.49
Port Bits 1->0	37	32	86.49

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[13:0]	Yes	Yes	*T1,*T4,*T5	Yes	T1,T4,T5	OUTPUT
cnt_o[15:14]	No	No		No		OUTPUT
cnt_after_commit_o[13:0]	Yes	Yes	*T1,*T4,*T5	Yes	T1,T4,T5	OUTPUT
cnt_after_commit_o[15:14]	No	No		No		OUTPUT
err_o	No	No		No		OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_ping_timer.u_prim_count_cnt

	Total	Covered	Percent
Totals	8	7	87.50
Total Bits	106	104	98.11
Total Bits 0->1	53	52	98.11
Total Bits 1->0	53	52	98.11

Ports	8	7	87.50
Port Bits	106	104	98.11
Port Bits 0->1	53	52	98.11
Port Bits 1->0	53	52	98.11

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
clr_i	Unreachable	Unreachable		Unreachable		INPUT
set_i	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
set_cnt_i[15:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
incr_en_i	Unreachable	Unreachable		Unreachable		INPUT
decr_en_i	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
step_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[15:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
cnt_after_commit_o[15:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
err_o	No	No		No		OUTPUT