Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_mubi4_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[0].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[1].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[2].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[3].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[4].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[5].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[6].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[7].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[8].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[9].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[10].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[11].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[12].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[13].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[14].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[15].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[16].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[17].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[18].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[19].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[20].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[21].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[22].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[23].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[24].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[25].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[26].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[27].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[28].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[29].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[30].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[31].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[32].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[33].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[34].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[35].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[36].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[37].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[38].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[39].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[40].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[41].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[42].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[43].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[44].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[45].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[46].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[47].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[48].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[49].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[50].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[51].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[52].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[53].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[54].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[55].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[56].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[57].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[58].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[59].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[60].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[61].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[62].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[63].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[64].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_cg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_rst_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00
gen_flops.u_prim_flop_2sync 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[0].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[1].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[2].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[3].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[4].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[5].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[6].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[7].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[8].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[9].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[10].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[11].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[12].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[13].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[14].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[15].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[16].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[17].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[18].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[19].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[20].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[21].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[22].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[23].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[24].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[25].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[26].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[27].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[28].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[29].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[30].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[31].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[32].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[33].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[34].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[35].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[36].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[37].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[38].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[39].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[40].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[41].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[42].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[43].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[44].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[45].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[46].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[47].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[48].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[49].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[50].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[51].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[52].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[53].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[54].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[55].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[56].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[57].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[58].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[59].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[60].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[61].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[62].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[63].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[64].u_prim_mubi4_sync_lpg_en

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_alert_handler_lpg_ctrl


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_buffs[0].gen_bits[0].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[1].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[2].u_prim_buf 100.00 100.00
gen_buffs[0].gen_bits[3].u_prim_buf 100.00 100.00

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=6 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_rst_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_cg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_rst_en

Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[0].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[1].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[2].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[3].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[4].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[5].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[6].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[7].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[8].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[9].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[10].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[11].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[12].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[13].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[14].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[15].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[16].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[17].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[18].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[19].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[20].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[21].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[22].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[23].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[24].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[25].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[26].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[27].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[28].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[29].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[30].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[31].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[32].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[33].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[34].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[35].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[36].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[37].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[38].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[39].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[40].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[41].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[42].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[43].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[44].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[45].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[46].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[47].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[48].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[49].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[50].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[51].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[52].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[53].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[54].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[55].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[56].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[57].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[58].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[59].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[60].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[61].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[62].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[63].u_prim_mubi4_sync_lpg_en

SCORELINE
100.00 100.00
tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[64].u_prim_mubi4_sync_lpg_en

Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Module : prim_mubi4_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 70512 70512 0 0
OutputsKnown_A 2147483647 2147483647 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 2147483647 2147483647 0 89856
gen_no_flops.OutputDelay_A 2147483647 2147483647 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 70512 70512 0 0
T1 113 113 0 0
T2 113 113 0 0
T3 113 113 0 0
T7 113 113 0 0
T8 113 113 0 0
T9 113 113 0 0
T10 113 113 0 0
T15 113 113 0 0
T16 113 113 0 0
T19 113 113 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 39975897 39968326 0 0
T2 2736295 2729628 0 0
T3 1645506 1637596 0 0
T7 58080983 58080192 0 0
T8 53339051 53338034 0 0
T9 8855697 8848465 0 0
T10 47011616 47010712 0 0
T15 6746326 6737399 0 0
T16 4941942 4931207 0 0
T19 12290784 12279936 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 89856
T1 16980912 16977552 0 144
T2 1162320 1159344 0 144
T3 698976 695472 0 144
T7 24671568 24671184 0 144
T8 22657296 22656816 0 144
T9 3761712 3758496 0 144
T10 19969536 19969104 0 144
T15 2865696 2861760 0 144
T16 2099232 2094528 0 144
T19 5220864 5216112 0 144

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 22994985 22990630 0 0
T2 1573975 1570140 0 0
T3 946530 941980 0 0
T7 33409415 33408960 0 0
T8 30681755 30681170 0 0
T9 5093985 5089825 0 0
T10 27042080 27041560 0 0
T15 3880630 3875495 0 0
T16 2842710 2836535 0 0
T19 7069920 7063680 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[0].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[1].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[2].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[3].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[4].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[5].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[6].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[7].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[8].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[9].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[10].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[11].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[12].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[13].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[14].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[15].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[16].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[17].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[18].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[19].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[20].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[21].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[22].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_cg_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_cg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_rst_en
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN12411100.00
ALWAYS12811100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
124 1 1
128 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_lpgs[23].u_prim_mubi4_sync_rst_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_flops.gen_no_stable_chks.OutputDelay_A 709906063 709831388 0 1872


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_flops.gen_no_stable_chks.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709831388 0 1872
T1 353769 353699 0 3
T2 24215 24153 0 3
T3 14562 14489 0 3
T7 513991 513983 0 3
T8 472027 472017 0 3
T9 78369 78302 0 3
T10 416032 416023 0 3
T15 59702 59620 0 3
T16 43734 43636 0 3
T19 108768 108669 0 3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[0].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[0].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[1].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[1].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[2].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[2].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[3].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[3].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[4].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[4].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[5].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[5].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[6].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[6].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[7].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[7].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[8].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[8].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[9].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[9].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[10].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[10].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[11].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[11].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[12].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[12].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[13].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[13].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[14].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[14].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[15].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[15].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[16].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[16].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[17].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[17].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[18].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[18].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[19].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[19].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[20].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[20].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[21].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[21].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[22].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[22].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[23].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[23].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[24].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[24].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[25].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[25].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[26].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[26].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[27].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[27].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[28].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[28].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[29].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[29].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[30].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[30].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[31].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[31].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[32].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[32].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[33].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[33].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[34].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[34].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[35].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[35].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[36].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[36].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[37].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[37].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[38].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[38].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[39].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[39].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[40].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[40].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[41].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[41].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[42].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[42].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[43].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[43].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[44].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[44].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[45].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[45].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[46].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[46].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[47].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[47].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[48].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[48].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[49].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[49].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[50].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[50].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[51].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[51].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[52].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[52].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[53].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[53].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[54].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[54].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[55].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[55].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[56].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[56].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[57].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[57].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[58].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[58].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[59].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[59].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[60].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[60].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[61].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[61].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[62].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[62].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[63].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[63].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[64].u_prim_mubi4_sync_lpg_en
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS14500
CONT_ASSIGN15511100.00
CONT_ASSIGN16811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
145 unreachable
146 unreachable
148 unreachable
155 1 1
168 1 1


Assert Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl.gen_alert_map[64].u_prim_mubi4_sync_lpg_en
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 624 624 0 0
OutputsKnown_A 709906063 709834722 0 0
gen_no_flops.OutputDelay_A 709906063 709834722 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 624 624 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T19 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 709906063 709834722 0 0
T1 353769 353702 0 0
T2 24215 24156 0 0
T3 14562 14492 0 0
T7 513991 513984 0 0
T8 472027 472018 0 0
T9 78369 78305 0 0
T10 416032 416024 0 0
T15 59702 59623 0 0
T16 43734 43639 0 0
T19 108768 108672 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%