Module Definition
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Module : alert_handler_lpg_ctrl
SCORELINECONDTOGGLEFSMBRANCHASSERT
73.39 96.77 50.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_lpg_ctrl.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_alert_handler_lpg_ctrl 100.00 100.00 100.00



Module Instance : tb.dut.u_alert_handler_lpg_ctrl

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
81.19 100.00 96.69 46.88 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_alert_map[0].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[10].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[11].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[12].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[13].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[14].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[15].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[16].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[17].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[18].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[19].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[1].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[20].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[21].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[22].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[23].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[24].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[25].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[26].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[27].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[28].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[29].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[2].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[30].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[31].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[32].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[33].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[34].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[35].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[36].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[37].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[38].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[39].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[3].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[40].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[41].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[42].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[43].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[44].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[45].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[46].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[47].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[48].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[49].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[4].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[50].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[51].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[52].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[53].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[54].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[55].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[56].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[57].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[58].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[59].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[5].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[60].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[61].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[62].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[63].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[64].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[6].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[7].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[8].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_alert_map[9].u_prim_mubi4_sync_lpg_en 100.00 100.00 100.00
gen_lpgs[0].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[0].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[10].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[10].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[11].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[11].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[12].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[12].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[13].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[13].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[14].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[14].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[15].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[15].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[16].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[16].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[17].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[17].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[18].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[18].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[19].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[19].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[1].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[1].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[20].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[20].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[21].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[21].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[22].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[22].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[23].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[23].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[2].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[2].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[3].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[3].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[4].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[4].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[5].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[5].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[6].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[6].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[7].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[7].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[8].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[8].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00
gen_lpgs[9].u_prim_mubi4_sync_cg_en 100.00 100.00 100.00 100.00
gen_lpgs[9].u_prim_mubi4_sync_rst_en 100.00 100.00 100.00 100.00

Line Coverage for Module : alert_handler_lpg_ctrl
Line No.TotalCoveredPercent
TOTAL313096.77
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
ALWAYS787685.71
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_lpg_ctrl.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_lpg_ctrl.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 24 24
78 1 1
79 1 1
80 1 1
81 1 1
83 1 1
84 1 1
85 0 1
MISSING_ELSE


Branch Coverage for Module : alert_handler_lpg_ctrl
Line No.TotalCoveredPercent
Branches 2 1 50.00
IF 84 2 1 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_lpg_ctrl.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_lpg_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 84 if ((!lpg_used))

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl
Line No.TotalCoveredPercent
TOTAL3030100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
ALWAYS7866100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_lpg_ctrl.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_lpg_ctrl.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
54 24 24
78 1 1
79 1 1
80 1 1
81 1 1
83 1 1
84 1 1
85 excluded
Exclude Annotation: VC_COV_UNR
MISSING_ELSE


Branch Coverage for Instance : tb.dut.u_alert_handler_lpg_ctrl
Line No.TotalCoveredPercent
Branches 1 1 100.00
IF 84 1 1 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_lpg_ctrl.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_lpg_ctrl.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 84 if ((!lpg_used))

Branches:
-1-StatusTestsExclude Annotation
1 Excluded VC_COV_UNR
0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%