Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.41	100.00	93.33	37.14	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.77	100.00		96.31			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	37.14			37.14
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.41	100.00	93.33	37.14	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.77	100.00		96.31			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	37.14			37.14
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.78	100.00	95.56	37.14	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.77	100.00		96.31			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	37.14			37.14
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.78	100.00	95.56	37.14	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.77	100.00		96.31			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	37.14			37.14
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T2,T12
1	1	0	Covered	T1,T4,T14
1	1	1	Covered	T1,T4,T14

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T14
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T8,T17

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T14
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T4,T8,T17

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T14
1	0	Covered	T27,T28,T29
1	1	Covered	T4,T5,T8

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T12,T6
1	Covered	T1,T2,T3

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T14

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T12,T4

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T24,T13

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T3

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T1,T4,T14

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T1,T4,T14
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T4,T8,T30
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T5,T31,T30
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T8,T19,T16
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T17,T32,T33
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T1,T4,T14
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T1,T4,T5
TimeoutSt->Phase0St	172	Covered	T4,T5,T8

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T14
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T8
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T14
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T4,T8,T22
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T12
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T5,T31,T30
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T12,T6
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T8,T19,T16
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T17,T32,T33
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T12
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T4,T14
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	989	0	0
CheckAccumTrig0_A	2147483647	2381	0	0
CheckAccumTrig1_A	2147483647	103	0	0
CheckClr_A	2147483647	1021	0	0
CheckEn_A	2147483647	1280188104	0	0
CheckPhase0_A	2147483647	2704	0	0
CheckPhase1_A	2147483647	2665	0	0
CheckPhase2_A	2147483647	2620	0	0
CheckPhase3_A	2147483647	2574	0	0
CheckTimeout0_A	2147483647	3102	0	0
CheckTimeoutSt1_A	2147483647	400717	0	0
CheckTimeoutSt2_A	2147483647	2727	0	0
CheckTimeoutStTrig_A	2147483647	268	0	0
ErrorStAllEscAsserted_A	2147483647	5028	0	0
ErrorStIsTerminal_A	2147483647	4188	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	989	0	0
T9	93784	156	0	0
T10	0	313	0	0
T11	0	124	0	0
T34	0	275	0	0
T35	0	121	0	0
T36	2139548	0	0	0
T37	301580	0	0	0
T38	259512	0	0	0
T39	869388	0	0	0
T40	41504	0	0	0
T41	180172	0	0	0
T42	859556	0	0	0
T43	2176480	0	0	0
T44	577880	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2381	0	0
T1	599664	7	0	0
T2	8874	1	0	0
T3	103752	1	0	0
T4	2643664	20	0	0
T5	273899	6	0	0
T6	1724463	1	0	0
T7	125594	2	0	0
T8	615279	9	0	0
T12	184008	1	0	0
T13	1887564	4	0	0
T14	99488	2	0	0
T17	351907	6	0	0
T19	0	2	0	0
T22	0	4	0	0
T24	481200	1	0	0
T25	16512	0	0	0
T26	21641	0	0	0
T45	0	3	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	103	0	0
T8	615279	1	0	0
T16	414148	1	0	0
T17	703814	1	0	0
T18	241178	0	0	0
T19	1233444	0	0	0
T20	640312	0	0	0
T22	468004	0	0	0
T23	955140	0	0	0
T30	320264	2	0	0
T33	111132	0	0	0
T44	0	1	0	0
T45	286270	0	0	0
T46	116214	0	0	0
T50	0	1	0	0
T51	50682	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	4	0	0
T58	0	1	0	0
T59	0	2	0	0
T60	0	4	0	0
T61	0	1	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	39914	0	0	0
T67	89668	0	0	0
T68	41871	0	0	0
T69	955391	0	0	0
T70	442495	0	0	0
T71	792498	0	0	0
T72	329069	0	0	0
T73	313076	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1021	0	0
T1	599664	2	0	0
T2	8874	0	0	0
T3	103752	0	0	0
T4	2643664	10	0	0
T5	273899	1	0	0
T6	1724463	0	0	0
T7	125594	0	0	0
T8	615279	6	0	0
T12	184008	0	0	0
T13	1887564	0	0	0
T14	99488	1	0	0
T17	351907	2	0	0
T19	0	1	0	0
T22	0	2	0	0
T23	0	3	0	0
T24	481200	0	0	0
T25	16512	0	0	0
T26	21641	0	0	0
T30	0	8	0	0
T31	0	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T51	0	4	0	0
T66	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1280188104	0	0
T1	799552	1106106	0	0
T2	11832	8604	0	0
T3	138336	100211	0	0
T4	2643664	1970722	0	0
T6	2299284	1020200	0	0
T12	245344	120568	0	0
T13	1887564	47639	0	0
T14	99488	47807	0	0
T24	481200	358748	0	0
T25	16512	13257	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2704	0	0
T1	599664	8	0	0
T2	8874	1	0	0
T3	103752	1	0	0
T4	2643664	21	0	0
T5	273899	10	0	0
T6	1724463	1	0	0
T7	125594	2	0	0
T8	615279	10	0	0
T12	184008	1	0	0
T13	1887564	4	0	0
T14	99488	3	0	0
T17	351907	7	0	0
T19	0	1	0	0
T22	0	2	0	0
T24	481200	1	0	0
T25	16512	0	0	0
T26	21641	0	0	0
T45	0	3	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T66	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2665	0	0
T1	599664	8	0	0
T2	8874	1	0	0
T3	103752	1	0	0
T4	2643664	21	0	0
T5	273899	9	0	0
T6	1724463	1	0	0
T7	125594	2	0	0
T8	615279	10	0	0
T12	184008	1	0	0
T13	1887564	4	0	0
T14	99488	3	0	0
T17	351907	7	0	0
T19	0	1	0	0
T22	0	2	0	0
T24	481200	1	0	0
T25	16512	0	0	0
T26	21641	0	0	0
T45	0	3	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T66	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2620	0	0
T1	599664	8	0	0
T2	8874	1	0	0
T3	103752	1	0	0
T4	2643664	21	0	0
T5	273899	9	0	0
T6	1724463	1	0	0
T7	125594	2	0	0
T8	615279	8	0	0
T12	184008	1	0	0
T13	1887564	4	0	0
T14	99488	3	0	0
T17	351907	7	0	0
T19	0	1	0	0
T22	0	2	0	0
T24	481200	1	0	0
T25	16512	0	0	0
T26	21641	0	0	0
T45	0	3	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T66	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2574	0	0
T1	599664	8	0	0
T2	8874	1	0	0
T3	103752	1	0	0
T4	2643664	21	0	0
T5	273899	9	0	0
T6	1724463	1	0	0
T7	125594	2	0	0
T8	615279	8	0	0
T12	184008	1	0	0
T13	1887564	4	0	0
T14	99488	3	0	0
T17	351907	6	0	0
T19	0	1	0	0
T22	0	2	0	0
T24	481200	1	0	0
T25	16512	0	0	0
T26	21641	0	0	0
T45	0	3	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T66	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3102	0	0
T1	399776	11	0	0
T2	5916	0	0	0
T3	69168	0	0	0
T4	2643664	47	0	0
T5	547798	21	0	0
T6	1149642	0	0	0
T7	251188	0	0	0
T8	1230558	15	0	0
T12	122672	0	0	0
T13	1887564	0	0	0
T14	99488	1	0	0
T16	0	2	0	0
T17	703814	4	0	0
T24	481200	0	0	0
T25	16512	0	0	0
T26	43282	8	0	0
T30	0	2	0	0
T33	0	6	0	0
T50	0	4	0	0
T51	0	1	0	0
T66	0	13	0	0
T68	0	2	0	0
T72	0	1	0	0
T75	0	1	0	0
T80	0	4	0	0
T81	0	2	0	0
T82	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	400717	0	0
T1	399776	714	0	0
T2	5916	0	0	0
T3	69168	0	0	0
T4	2643664	6554	0	0
T5	547798	4026	0	0
T6	1149642	0	0	0
T7	251188	0	0	0
T8	1230558	2314	0	0
T12	122672	0	0	0
T13	1887564	0	0	0
T14	99488	28	0	0
T16	0	85	0	0
T17	703814	522	0	0
T24	481200	0	0	0
T25	16512	0	0	0
T26	43282	691	0	0
T30	0	7	0	0
T33	0	222	0	0
T50	0	145	0	0
T51	0	8	0	0
T66	0	1226	0	0
T68	0	197	0	0
T72	0	130	0	0
T75	0	697	0	0
T80	0	260	0	0
T81	0	286	0	0
T82	0	8	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2727	0	0
T1	199888	10	0	0
T2	2958	0	0	0
T3	34584	0	0	0
T4	2643664	45	0	0
T5	821697	16	0	0
T6	574821	0	0	0
T7	376782	0	0	0
T8	1845837	13	0	0
T12	61336	0	0	0
T13	1887564	0	0	0
T14	99488	0	0	0
T16	0	1	0	0
T17	1055721	3	0	0
T24	481200	0	0	0
T25	16512	0	0	0
T26	64923	8	0	0
T27	0	6	0	0
T30	0	4	0	0
T33	0	4	0	0
T50	0	1	0	0
T66	0	12	0	0
T68	0	2	0	0
T72	0	1	0	0
T75	0	1	0	0
T80	0	3	0	0
T81	0	2	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	2	0	0
T86	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	268	0	0
T1	199888	0	0	0
T2	2958	0	0	0
T3	34584	0	0	0
T4	1321832	2	0	0
T5	821697	4	0	0
T6	574821	0	0	0
T7	376782	0	0	0
T8	1845837	1	0	0
T12	61336	0	0	0
T13	943782	0	0	0
T14	49744	0	0	0
T17	1055721	0	0	0
T18	241178	0	0	0
T19	1233444	0	0	0
T24	240600	0	0	0
T25	8256	0	0	0
T26	64923	0	0	0
T27	0	1	0	0
T28	0	2	0	0
T37	0	1	0	0
T38	0	2	0	0
T45	286270	0	0	0
T46	116214	0	0	0
T66	39914	1	0	0
T75	0	1	0	0
T79	0	1	0	0
T82	0	2	0	0
T87	0	1	0	0
T88	0	2	0	0
T89	0	1	0	0
T90	0	1	0	0
T91	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0
T94	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5028	0	0
T9	93784	754	0	0
T10	0	1492	0	0
T11	0	700	0	0
T34	0	1407	0	0
T35	0	675	0	0
T36	2139548	0	0	0
T37	301580	0	0	0
T38	259512	0	0	0
T39	869388	0	0	0
T40	41504	0	0	0
T41	180172	0	0	0
T42	859556	0	0	0
T43	2176480	0	0	0
T44	577880	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4188	0	0
T9	93784	634	0	0
T10	0	1252	0	0
T11	0	580	0	0
T34	0	1167	0	0
T35	0	555	0	0
T36	2139548	0	0	0
T37	301580	0	0	0
T38	259512	0	0	0
T39	869388	0	0	0
T40	41504	0	0	0
T41	180172	0	0	0
T42	859556	0	0	0
T43	2176480	0	0	0
T44	577880	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	799552	799304	0	0
T2	11832	11580	0	0
T3	138336	138132	0	0
T4	2643664	2643440	0	0
T6	2299284	2298932	0	0
T12	245344	245076	0	0
T13	1887564	1887220	0	0
T14	99488	99184	0	0
T24	481200	480948	0	0
T25	16512	16172	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	799552	799304	0	0
T2	11832	11580	0	0
T3	138336	138132	0	0
T4	2643664	2643440	0	0
T6	2299284	2298932	0	0
T12	245344	245076	0	0
T13	1887564	1887220	0	0
T14	99488	99184	0	0
T24	481200	480948	0	0
T25	16512	16172	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T12

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T12
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T12

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T24
1	0	1	Covered	T2,T12,T4
1	1	0	Covered	T1,T4,T5
1	1	1	Covered	T4,T5,T26

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T26
0	1	Covered	T5,T66,T88
1	0	Covered	T4,T51,T16

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T4,T5,T26
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T51,T16

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T26
1	0	Not Covered
1	1	Covered	T5,T66,T88

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T12,T4
1	Covered	T2,T14,T13

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T12
1	Covered	T1,T4,T5

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T12,T5

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T12
1	Covered	T4,T5,T22

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T2,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T2,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T12
Phase1St	198	Covered	T1,T2,T12
Phase2St	215	Covered	T1,T2,T12
Phase3St	233	Covered	T1,T2,T12
TerminalSt	249	Covered	T1,T2,T12
TimeoutSt	159	Covered	T4,T5,T26

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T1,T2,T12
IdleSt->TimeoutSt	159	Covered	T4,T5,T26
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T97,T44,T59
Phase0St->Phase1St	198	Covered	T1,T2,T12
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T98,T99,T100
Phase1St->Phase2St	215	Covered	T1,T2,T12
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T101,T102,T103
Phase2St->Phase3St	233	Covered	T1,T2,T12
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T104,T76,T105
Phase3St->TerminalSt	249	Covered	T1,T2,T12
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T4,T5
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T4,T5,T26
TimeoutSt->Phase0St	172	Covered	T5,T66,T51

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T12
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T26
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T66
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T26
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T26
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T97,T44,T59
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T12
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T12,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T98,T99,T100
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T12
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T12,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T101,T102,T103
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T12
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T12,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T104,T76,T105
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T12,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T4,T66
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T12
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	719502818	272	0	0
CheckAccumTrig0_A	719502818	478	0	0
CheckAccumTrig1_A	719502818	20	0	0
CheckClr_A	719502818	198	0	0
CheckEn_A	719363146	374282905	0	0
CheckPhase0_A	719502818	561	0	0
CheckPhase1_A	719502818	558	0	0
CheckPhase2_A	719502818	550	0	0
CheckPhase3_A	719502818	536	0	0
CheckTimeout0_A	719502818	687	0	0
CheckTimeoutSt1_A	719502818	89056	0	0
CheckTimeoutSt2_A	719502818	596	0	0
CheckTimeoutStTrig_A	719502818	70	0	0
ErrorStAllEscAsserted_A	719502818	1271	0	0
ErrorStIsTerminal_A	719502818	1061	0	0
EscStateOut_A	719361440	719289953	0	0
u_state_regs_A	719502818	719342415	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	272	0	0
T9	23446	29	0	0
T10	0	81	0	0
T11	0	27	0	0
T34	0	93	0	0
T35	0	42	0	0
T36	534887	0	0	0
T37	75395	0	0	0
T38	64878	0	0	0
T39	217347	0	0	0
T40	10376	0	0	0
T41	45043	0	0	0
T42	214889	0	0	0
T43	544120	0	0	0
T44	144470	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	478	0	0
T1	199888	2	0	0
T2	2958	1	0	0
T3	34584	0	0	0
T4	660916	4	0	0
T5	0	2	0	0
T6	574821	0	0	0
T7	0	1	0	0
T12	61336	1	0	0
T13	471891	1	0	0
T14	24872	1	0	0
T22	0	2	0	0
T24	120300	0	0	0
T25	4128	0	0	0
T45	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	20	0	0
T16	414148	1	0	0
T30	320264	0	0	0
T33	111132	0	0	0
T51	50682	1	0	0
T58	0	1	0	0
T68	41871	0	0	0
T69	955391	0	0	0
T70	442495	0	0	0
T71	792498	0	0	0
T72	329069	0	0	0
T73	313076	0	0	0
T91	0	1	0	0
T94	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0
T110	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	198	0	0
T1	199888	1	0	0
T2	2958	0	0	0
T3	34584	0	0	0
T4	660916	2	0	0
T6	574821	0	0	0
T12	61336	0	0	0
T13	471891	0	0	0
T14	24872	0	0	0
T22	0	1	0	0
T24	120300	0	0	0
T25	4128	0	0	0
T51	0	4	0	0
T66	0	1	0	0
T75	0	1	0	0
T87	0	3	0	0
T88	0	1	0	0
T104	0	2	0	0
T111	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719363146	374282905	0	0
T1	199888	458364	0	0
T2	2958	2157	0	0
T3	34584	34532	0	0
T4	660916	594386	0	0
T6	574821	152738	0	0
T12	61336	2669	0	0
T13	471891	9176	0	0
T14	24872	720	0	0
T24	120300	115320	0	0
T25	4128	1604	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	561	0	0
T1	199888	2	0	0
T2	2958	1	0	0
T3	34584	0	0	0
T4	660916	4	0	0
T5	0	4	0	0
T6	574821	0	0	0
T7	0	1	0	0
T12	61336	1	0	0
T13	471891	1	0	0
T14	24872	1	0	0
T24	120300	0	0	0
T25	4128	0	0	0
T45	0	1	0	0
T66	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	558	0	0
T1	199888	2	0	0
T2	2958	1	0	0
T3	34584	0	0	0
T4	660916	4	0	0
T5	0	4	0	0
T6	574821	0	0	0
T7	0	1	0	0
T12	61336	1	0	0
T13	471891	1	0	0
T14	24872	1	0	0
T24	120300	0	0	0
T25	4128	0	0	0
T45	0	1	0	0
T66	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	550	0	0
T1	199888	2	0	0
T2	2958	1	0	0
T3	34584	0	0	0
T4	660916	4	0	0
T5	0	4	0	0
T6	574821	0	0	0
T7	0	1	0	0
T12	61336	1	0	0
T13	471891	1	0	0
T14	24872	1	0	0
T24	120300	0	0	0
T25	4128	0	0	0
T45	0	1	0	0
T66	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	536	0	0
T1	199888	2	0	0
T2	2958	1	0	0
T3	34584	0	0	0
T4	660916	4	0	0
T5	0	4	0	0
T6	574821	0	0	0
T7	0	1	0	0
T12	61336	1	0	0
T13	471891	1	0	0
T14	24872	1	0	0
T24	120300	0	0	0
T25	4128	0	0	0
T45	0	1	0	0
T66	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	687	0	0
T4	660916	16	0	0
T5	273899	9	0	0
T7	125594	0	0	0
T8	615279	10	0	0
T13	471891	0	0	0
T14	24872	0	0	0
T16	0	2	0	0
T17	351907	1	0	0
T24	120300	0	0	0
T25	4128	0	0	0
T26	21641	1	0	0
T33	0	2	0	0
T51	0	1	0	0
T66	0	2	0	0
T80	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	89056	0	0
T4	660916	2289	0	0
T5	273899	2678	0	0
T7	125594	0	0	0
T8	615279	1678	0	0
T13	471891	0	0	0
T14	24872	0	0	0
T16	0	85	0	0
T17	351907	190	0	0
T24	120300	0	0	0
T25	4128	0	0	0
T26	21641	76	0	0
T33	0	108	0	0
T51	0	8	0	0
T66	0	212	0	0
T80	0	111	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	596	0	0
T4	660916	16	0	0
T5	273899	7	0	0
T7	125594	0	0	0
T8	615279	10	0	0
T13	471891	0	0	0
T14	24872	0	0	0
T16	0	1	0	0
T17	351907	1	0	0
T24	120300	0	0	0
T25	4128	0	0	0
T26	21641	1	0	0
T33	0	2	0	0
T66	0	1	0	0
T75	0	1	0	0
T80	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	70	0	0
T5	273899	2	0	0
T7	125594	0	0	0
T8	615279	0	0	0
T17	351907	0	0	0
T18	120589	0	0	0
T19	616722	0	0	0
T26	21641	0	0	0
T37	0	1	0	0
T45	143135	0	0	0
T46	58107	0	0	0
T66	19957	1	0	0
T88	0	1	0	0
T91	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0
T108	0	1	0	0
T112	0	1	0	0
T113	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	1271	0	0
T9	23446	203	0	0
T10	0	366	0	0
T11	0	186	0	0
T34	0	346	0	0
T35	0	170	0	0
T36	534887	0	0	0
T37	75395	0	0	0
T38	64878	0	0	0
T39	217347	0	0	0
T40	10376	0	0	0
T41	45043	0	0	0
T42	214889	0	0	0
T43	544120	0	0	0
T44	144470	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	1061	0	0
T9	23446	173	0	0
T10	0	306	0	0
T11	0	156	0	0
T34	0	286	0	0
T35	0	140	0	0
T36	534887	0	0	0
T37	75395	0	0	0
T38	64878	0	0	0
T39	217347	0	0	0
T40	10376	0	0	0
T41	45043	0	0	0
T42	214889	0	0	0
T43	544120	0	0	0
T44	144470	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719361440	719289953	0	0
T1	199888	199826	0	0
T2	2958	2895	0	0
T3	34584	34533	0	0
T4	660916	660860	0	0
T6	574821	574733	0	0
T12	61336	61269	0	0
T13	471891	471805	0	0
T14	24872	24796	0	0
T24	120300	120237	0	0
T25	4128	4043	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	719342415	0	0
T1	199888	199826	0	0
T2	2958	2895	0	0
T3	34584	34533	0	0
T4	660916	660860	0	0
T6	574821	574733	0	0
T12	61336	61269	0	0
T13	471891	471805	0	0
T14	24872	24796	0	0
T24	120300	120237	0	0
T25	4128	4043	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T6,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T12
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T6,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T14
1	0	1	Covered	T12,T6,T4
1	1	0	Covered	T1,T4,T5
1	1	1	Covered	T1,T4,T14

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T14
0	1	Covered	T1,T14,T114
1	0	Covered	T80,T50,T33

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T14
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T80,T50,T33

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T14
1	0	Not Covered
1	1	Covered	T1,T14,T114

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T6,T4
1	Covered	T4,T14,T8

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T6,T4
1	Covered	T13,T17,T80

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T6,T4
1	Covered	T1,T4,T46

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T14
1	Covered	T1,T6,T5

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T6,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T4,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T6,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T4,T14,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T6,T4
Phase1St	198	Covered	T1,T6,T4
Phase2St	215	Covered	T1,T6,T4
Phase3St	233	Covered	T1,T6,T4
TerminalSt	249	Covered	T1,T6,T4
TimeoutSt	159	Covered	T1,T4,T14

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T1,T6,T4
IdleSt->TimeoutSt	159	Covered	T1,T4,T14
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T22,T115,T116
Phase0St->Phase1St	198	Covered	T1,T6,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T117,T118,T98
Phase1St->Phase2St	215	Covered	T1,T6,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T119,T120
Phase2St->Phase3St	233	Covered	T1,T6,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T80,T121,T122
Phase3St->TerminalSt	249	Covered	T1,T6,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T4,T5
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T4,T5,T8
TimeoutSt->Phase0St	172	Covered	T1,T14,T80

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T6,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T14
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T14,T80
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T14
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T8
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T22,T115,T116
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T6,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T6,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T117,T118,T98
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T6,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T6,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T119,T120
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T6,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T6,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T80,T121,T122
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T6,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T6,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T4,T45
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T6,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	719502818	223	0	0
CheckAccumTrig0_A	719502818	528	0	0
CheckAccumTrig1_A	719502818	23	0	0
CheckClr_A	719502818	207	0	0
CheckEn_A	719363146	313169246	0	0
CheckPhase0_A	719502818	606	0	0
CheckPhase1_A	719502818	600	0	0
CheckPhase2_A	719502818	597	0	0
CheckPhase3_A	719502818	591	0	0
CheckTimeout0_A	719502818	792	0	0
CheckTimeoutSt1_A	719502818	100825	0	0
CheckTimeoutSt2_A	719502818	700	0	0
CheckTimeoutStTrig_A	719502818	68	0	0
ErrorStAllEscAsserted_A	719502818	1219	0	0
ErrorStIsTerminal_A	719502818	1009	0	0
EscStateOut_A	719361440	719289953	0	0
u_state_regs_A	719502818	719342415	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	223	0	0
T9	23446	35	0	0
T10	0	79	0	0
T11	0	30	0	0
T34	0	61	0	0
T35	0	18	0	0
T36	534887	0	0	0
T37	75395	0	0	0
T38	64878	0	0	0
T39	217347	0	0	0
T40	10376	0	0	0
T41	45043	0	0	0
T42	214889	0	0	0
T43	544120	0	0	0
T44	144470	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	528	0	0
T1	199888	2	0	0
T2	2958	0	0	0
T3	34584	0	0	0
T4	660916	6	0	0
T5	0	1	0	0
T6	574821	1	0	0
T8	0	2	0	0
T12	61336	0	0	0
T13	471891	1	0	0
T14	24872	0	0	0
T17	0	1	0	0
T19	0	1	0	0
T24	120300	0	0	0
T25	4128	0	0	0
T45	0	1	0	0
T46	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	23	0	0
T21	521522	0	0	0
T28	0	2	0	0
T32	6281	0	0	0
T33	0	2	0	0
T47	372172	0	0	0
T48	545127	0	0	0
T49	165601	0	0	0
T50	0	2	0	0
T59	0	1	0	0
T62	0	1	0	0
T74	1880	0	0	0
T75	0	1	0	0
T80	330719	1	0	0
T87	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	127631	0	0	0
T126	806480	0	0	0
T127	29718	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	207	0	0
T1	199888	1	0	0
T2	2958	0	0	0
T3	34584	0	0	0
T4	660916	5	0	0
T6	574821	0	0	0
T12	61336	0	0	0
T13	471891	0	0	0
T14	24872	0	0	0
T22	0	1	0	0
T24	120300	0	0	0
T25	4128	0	0	0
T33	0	6	0	0
T45	0	1	0	0
T50	0	5	0	0
T80	0	1	0	0
T87	0	1	0	0
T121	0	3	0	0
T128	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719363146	313169246	0	0
T1	199888	274897	0	0
T2	2958	2168	0	0
T3	34584	34532	0	0
T4	660916	646250	0	0
T6	574821	74874	0	0
T12	61336	56020	0	0
T13	471891	9193	0	0
T14	24872	724	0	0
T24	120300	120236	0	0
T25	4128	3569	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	606	0	0
T1	199888	3	0	0
T2	2958	0	0	0
T3	34584	0	0	0
T4	660916	6	0	0
T5	0	1	0	0
T6	574821	1	0	0
T8	0	2	0	0
T12	61336	0	0	0
T13	471891	1	0	0
T14	24872	1	0	0
T17	0	1	0	0
T24	120300	0	0	0
T25	4128	0	0	0
T45	0	1	0	0
T46	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	600	0	0
T1	199888	3	0	0
T2	2958	0	0	0
T3	34584	0	0	0
T4	660916	6	0	0
T5	0	1	0	0
T6	574821	1	0	0
T8	0	2	0	0
T12	61336	0	0	0
T13	471891	1	0	0
T14	24872	1	0	0
T17	0	1	0	0
T24	120300	0	0	0
T25	4128	0	0	0
T45	0	1	0	0
T46	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	597	0	0
T1	199888	3	0	0
T2	2958	0	0	0
T3	34584	0	0	0
T4	660916	6	0	0
T5	0	1	0	0
T6	574821	1	0	0
T8	0	2	0	0
T12	61336	0	0	0
T13	471891	1	0	0
T14	24872	1	0	0
T17	0	1	0	0
T24	120300	0	0	0
T25	4128	0	0	0
T45	0	1	0	0
T46	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	591	0	0
T1	199888	3	0	0
T2	2958	0	0	0
T3	34584	0	0	0
T4	660916	6	0	0
T5	0	1	0	0
T6	574821	1	0	0
T8	0	2	0	0
T12	61336	0	0	0
T13	471891	1	0	0
T14	24872	1	0	0
T17	0	1	0	0
T24	120300	0	0	0
T25	4128	0	0	0
T45	0	1	0	0
T46	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	792	0	0
T1	199888	1	0	0
T2	2958	0	0	0
T3	34584	0	0	0
T4	660916	6	0	0
T5	0	3	0	0
T6	574821	0	0	0
T8	0	1	0	0
T12	61336	0	0	0
T13	471891	0	0	0
T14	24872	1	0	0
T24	120300	0	0	0
T25	4128	0	0	0
T33	0	2	0	0
T50	0	3	0	0
T66	0	4	0	0
T68	0	2	0	0
T80	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	100825	0	0
T1	199888	9	0	0
T2	2958	0	0	0
T3	34584	0	0	0
T4	660916	980	0	0
T5	0	345	0	0
T6	574821	0	0	0
T8	0	230	0	0
T12	61336	0	0	0
T13	471891	0	0	0
T14	24872	28	0	0
T24	120300	0	0	0
T25	4128	0	0	0
T33	0	3	0	0
T50	0	122	0	0
T66	0	364	0	0
T68	0	197	0	0
T80	0	4	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	700	0	0
T4	660916	6	0	0
T5	273899	2	0	0
T7	125594	0	0	0
T8	615279	1	0	0
T13	471891	0	0	0
T14	24872	0	0	0
T17	351907	0	0	0
T24	120300	0	0	0
T25	4128	0	0	0
T26	21641	0	0	0
T30	0	4	0	0
T50	0	1	0	0
T55	0	1	0	0
T66	0	4	0	0
T68	0	2	0	0
T86	0	2	0	0
T87	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	68	0	0
T1	199888	1	0	0
T2	2958	0	0	0
T3	34584	0	0	0
T4	660916	0	0	0
T6	574821	0	0	0
T12	61336	0	0	0
T13	471891	0	0	0
T14	24872	1	0	0
T24	120300	0	0	0
T25	4128	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T38	0	1	0	0
T89	0	1	0	0
T90	0	1	0	0
T91	0	1	0	0
T112	0	1	0	0
T114	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	1219	0	0
T9	23446	172	0	0
T10	0	341	0	0
T11	0	171	0	0
T34	0	350	0	0
T35	0	185	0	0
T36	534887	0	0	0
T37	75395	0	0	0
T38	64878	0	0	0
T39	217347	0	0	0
T40	10376	0	0	0
T41	45043	0	0	0
T42	214889	0	0	0
T43	544120	0	0	0
T44	144470	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	1009	0	0
T9	23446	142	0	0
T10	0	281	0	0
T11	0	141	0	0
T34	0	290	0	0
T35	0	155	0	0
T36	534887	0	0	0
T37	75395	0	0	0
T38	64878	0	0	0
T39	217347	0	0	0
T40	10376	0	0	0
T41	45043	0	0	0
T42	214889	0	0	0
T43	544120	0	0	0
T44	144470	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719361440	719289953	0	0
T1	199888	199826	0	0
T2	2958	2895	0	0
T3	34584	34533	0	0
T4	660916	660860	0	0
T6	574821	574733	0	0
T12	61336	61269	0	0
T13	471891	471805	0	0
T14	24872	24796	0	0
T24	120300	120237	0	0
T25	4128	4043	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	719342415	0	0
T1	199888	199826	0	0
T2	2958	2895	0	0
T3	34584	34533	0	0
T4	660916	660860	0	0
T6	574821	574733	0	0
T12	61336	61269	0	0
T13	471891	471805	0	0
T14	24872	24796	0	0
T24	120300	120237	0	0
T25	4128	4043	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T14
1	0	1	Covered	T1,T12,T4
1	1	0	Covered	T1,T4,T14
1	1	1	Covered	T1,T4,T5

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T5,T8,T82
1	0	Covered	T17,T50,T30

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T4,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T17,T50,T30

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T27
1	1	Covered	T5,T8,T82

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T24
1	Covered	T1,T3,T4

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T14,T5,T45

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T4,T17

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T4,T24,T13

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T4,T24

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T4,T24,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T1,T3,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T4
Phase1St	198	Covered	T1,T3,T4
Phase2St	215	Covered	T1,T3,T4
Phase3St	233	Covered	T1,T3,T4
TerminalSt	249	Covered	T1,T3,T4
TimeoutSt	159	Covered	T1,T4,T5

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T1,T3,T4
IdleSt->TimeoutSt	159	Covered	T1,T4,T5
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T30,T129,T130
Phase0St->Phase1St	198	Covered	T1,T3,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T5,T30,T97
Phase1St->Phase2St	215	Covered	T1,T3,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T19,T16,T83
Phase2St->Phase3St	233	Covered	T1,T3,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T17,T32,T33
Phase3St->TerminalSt	249	Covered	T1,T3,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T4,T14
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T4,T5
TimeoutSt->Phase0St	172	Covered	T5,T8,T17

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T8,T17
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T30,T129,T130
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T5,T30,T97
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T4,T24
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T19,T16,T83
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T17,T32,T33
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T4,T14
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	719502818	254	0	0
CheckAccumTrig0_A	719502818	817	0	0
CheckAccumTrig1_A	719502818	38	0	0
CheckClr_A	719502818	357	0	0
CheckEn_A	719363146	271949284	0	0
CheckPhase0_A	719502818	900	0	0
CheckPhase1_A	719502818	881	0	0
CheckPhase2_A	719502818	865	0	0
CheckPhase3_A	719502818	847	0	0
CheckTimeout0_A	719502818	957	0	0
CheckTimeoutSt1_A	719502818	125763	0	0
CheckTimeoutSt2_A	719502818	858	0	0
CheckTimeoutStTrig_A	719502818	61	0	0
ErrorStAllEscAsserted_A	719502818	1263	0	0
ErrorStIsTerminal_A	719502818	1053	0	0
EscStateOut_A	719361440	719289953	0	0
u_state_regs_A	719502818	719342415	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	254	0	0
T9	23446	46	0	0
T10	0	88	0	0
T11	0	30	0	0
T34	0	65	0	0
T35	0	25	0	0
T36	534887	0	0	0
T37	75395	0	0	0
T38	64878	0	0	0
T39	217347	0	0	0
T40	10376	0	0	0
T41	45043	0	0	0
T42	214889	0	0	0
T43	544120	0	0	0
T44	144470	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	817	0	0
T1	199888	3	0	0
T2	2958	0	0	0
T3	34584	1	0	0
T4	660916	7	0	0
T5	0	2	0	0
T6	574821	0	0	0
T8	0	1	0	0
T12	61336	0	0	0
T13	471891	1	0	0
T14	24872	1	0	0
T17	0	5	0	0
T24	120300	1	0	0
T25	4128	0	0	0
T45	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	38	0	0
T17	351907	1	0	0
T18	120589	0	0	0
T19	616722	0	0	0
T20	320156	0	0	0
T22	234002	0	0	0
T23	477570	0	0	0
T30	0	1	0	0
T44	0	1	0	0
T45	143135	0	0	0
T46	58107	0	0	0
T50	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T57	0	4	0	0
T59	0	1	0	0
T61	0	1	0	0
T63	0	1	0	0
T66	19957	0	0	0
T67	89668	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	357	0	0
T1	199888	1	0	0
T2	2958	0	0	0
T3	34584	0	0	0
T4	660916	5	0	0
T5	0	1	0	0
T6	574821	0	0	0
T8	0	1	0	0
T12	61336	0	0	0
T13	471891	0	0	0
T14	24872	1	0	0
T17	0	2	0	0
T19	0	1	0	0
T23	0	3	0	0
T24	120300	0	0	0
T25	4128	0	0	0
T32	0	2	0	0
T74	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719363146	271949284	0	0
T1	199888	173020	0	0
T2	2958	2131	0	0
T3	34584	616	0	0
T4	660916	97623	0	0
T6	574821	514669	0	0
T12	61336	611	0	0
T13	471891	9139	0	0
T14	24872	21568	0	0
T24	120300	2956	0	0
T25	4128	4042	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	900	0	0
T1	199888	3	0	0
T2	2958	0	0	0
T3	34584	1	0	0
T4	660916	7	0	0
T5	0	3	0	0
T6	574821	0	0	0
T8	0	2	0	0
T12	61336	0	0	0
T13	471891	1	0	0
T14	24872	1	0	0
T17	0	6	0	0
T24	120300	1	0	0
T25	4128	0	0	0
T45	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	881	0	0
T1	199888	3	0	0
T2	2958	0	0	0
T3	34584	1	0	0
T4	660916	7	0	0
T5	0	2	0	0
T6	574821	0	0	0
T8	0	2	0	0
T12	61336	0	0	0
T13	471891	1	0	0
T14	24872	1	0	0
T17	0	6	0	0
T24	120300	1	0	0
T25	4128	0	0	0
T45	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	865	0	0
T1	199888	3	0	0
T2	2958	0	0	0
T3	34584	1	0	0
T4	660916	7	0	0
T5	0	2	0	0
T6	574821	0	0	0
T8	0	2	0	0
T12	61336	0	0	0
T13	471891	1	0	0
T14	24872	1	0	0
T17	0	6	0	0
T24	120300	1	0	0
T25	4128	0	0	0
T45	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	847	0	0
T1	199888	3	0	0
T2	2958	0	0	0
T3	34584	1	0	0
T4	660916	7	0	0
T5	0	2	0	0
T6	574821	0	0	0
T8	0	2	0	0
T12	61336	0	0	0
T13	471891	1	0	0
T14	24872	1	0	0
T17	0	5	0	0
T24	120300	1	0	0
T25	4128	0	0	0
T45	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	957	0	0
T1	199888	10	0	0
T2	2958	0	0	0
T3	34584	0	0	0
T4	660916	18	0	0
T5	0	2	0	0
T6	574821	0	0	0
T8	0	2	0	0
T12	61336	0	0	0
T13	471891	0	0	0
T14	24872	0	0	0
T17	0	3	0	0
T24	120300	0	0	0
T25	4128	0	0	0
T30	0	1	0	0
T50	0	1	0	0
T66	0	2	0	0
T72	0	1	0	0
T80	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	125763	0	0
T1	199888	705	0	0
T2	2958	0	0	0
T3	34584	0	0	0
T4	660916	2407	0	0
T5	0	127	0	0
T6	574821	0	0	0
T8	0	364	0	0
T12	61336	0	0	0
T13	471891	0	0	0
T14	24872	0	0	0
T17	0	332	0	0
T24	120300	0	0	0
T25	4128	0	0	0
T30	0	5	0	0
T50	0	23	0	0
T66	0	219	0	0
T72	0	130	0	0
T80	0	145	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	858	0	0
T1	199888	10	0	0
T2	2958	0	0	0
T3	34584	0	0	0
T4	660916	18	0	0
T5	0	1	0	0
T6	574821	0	0	0
T8	0	1	0	0
T12	61336	0	0	0
T13	471891	0	0	0
T14	24872	0	0	0
T17	0	2	0	0
T24	120300	0	0	0
T25	4128	0	0	0
T66	0	2	0	0
T72	0	1	0	0
T80	0	2	0	0
T84	0	1	0	0
T85	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	61	0	0
T5	273899	1	0	0
T7	125594	0	0	0
T8	615279	1	0	0
T17	351907	0	0	0
T18	120589	0	0	0
T19	616722	0	0	0
T26	21641	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T38	0	1	0	0
T45	143135	0	0	0
T46	58107	0	0	0
T66	19957	0	0	0
T82	0	1	0	0
T88	0	1	0	0
T94	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	1263	0	0
T9	23446	207	0	0
T10	0	395	0	0
T11	0	158	0	0
T34	0	353	0	0
T35	0	150	0	0
T36	534887	0	0	0
T37	75395	0	0	0
T38	64878	0	0	0
T39	217347	0	0	0
T40	10376	0	0	0
T41	45043	0	0	0
T42	214889	0	0	0
T43	544120	0	0	0
T44	144470	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	1053	0	0
T9	23446	177	0	0
T10	0	335	0	0
T11	0	128	0	0
T34	0	293	0	0
T35	0	120	0	0
T36	534887	0	0	0
T37	75395	0	0	0
T38	64878	0	0	0
T39	217347	0	0	0
T40	10376	0	0	0
T41	45043	0	0	0
T42	214889	0	0	0
T43	544120	0	0	0
T44	144470	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719361440	719289953	0	0
T1	199888	199826	0	0
T2	2958	2895	0	0
T3	34584	34533	0	0
T4	660916	660860	0	0
T6	574821	574733	0	0
T12	61336	61269	0	0
T13	471891	471805	0	0
T14	24872	24796	0	0
T24	120300	120237	0	0
T25	4128	4043	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	719342415	0	0
T1	199888	199826	0	0
T2	2958	2895	0	0
T3	34584	34533	0	0
T4	660916	660860	0	0
T6	574821	574733	0	0
T12	61336	61269	0	0
T13	471891	471805	0	0
T14	24872	24796	0	0
T24	120300	120237	0	0
T25	4128	4043	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T10,T11
1	0	Covered	T4,T13,T5
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T13,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T13,T5

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T6
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T13,T5

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Covered	T13,T5,T7
1	1	0	Covered	T1,T4,T14
1	1	1	Covered	T4,T5,T26

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T26
0	1	Covered	T4,T5,T75
1	0	Covered	T8,T30,T83

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T4,T5,T26
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T8,T30,T83

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T26
1	0	Covered	T28,T29
1	1	Covered	T4,T5,T75

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T13,T5
1	Covered	T4,T19,T48

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T13,T5
1	Covered	T4,T8,T31

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T13,T8
1	Covered	T5,T7,T8

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T7
1	Covered	T4,T13,T22

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T9,T10,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T4,T13,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T4,T5,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T4,T5,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T11
1	0	Covered	T5,T7,T8

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T9,T10,T11
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T4,T13,T5
Phase1St	198	Covered	T4,T13,T5
Phase2St	215	Covered	T4,T13,T5
Phase3St	233	Covered	T4,T13,T5
TerminalSt	249	Covered	T4,T13,T5
TimeoutSt	159	Covered	T4,T5,T26

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T9,T10,T11
IdleSt->Phase0St	152	Covered	T4,T13,T5
IdleSt->TimeoutSt	159	Covered	T4,T5,T26
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T4,T8,T30
Phase0St->Phase1St	198	Covered	T4,T13,T5
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T31,T30,T91
Phase1St->Phase2St	215	Covered	T4,T13,T5
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T8,T131,T59
Phase2St->Phase3St	233	Covered	T4,T13,T5
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T132,T133,T134
Phase3St->TerminalSt	249	Covered	T4,T13,T5
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T4,T5,T8
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T4,T5,T26
TimeoutSt->Phase0St	172	Covered	T4,T5,T8

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T13,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T26
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T8
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T26
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T26
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T4,T8,T30
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T4,T13,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T4,T13,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T31,T30,T91
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T4,T13,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T4,T13,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T8,T131,T59
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T4,T13,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T4,T13,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T132,T133,T134
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T4,T13,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T4,T13,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T8,T22
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T13,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	719502818	240	0	0
CheckAccumTrig0_A	719502818	558	0	0
CheckAccumTrig1_A	719502818	22	0	0
CheckClr_A	719502818	259	0	0
CheckEn_A	719363146	320786669	0	0
CheckPhase0_A	719502818	637	0	0
CheckPhase1_A	719502818	626	0	0
CheckPhase2_A	719502818	608	0	0
CheckPhase3_A	719502818	600	0	0
CheckTimeout0_A	719502818	666	0	0
CheckTimeoutSt1_A	719502818	85073	0	0
CheckTimeoutSt2_A	719502818	573	0	0
CheckTimeoutStTrig_A	719502818	69	0	0
ErrorStAllEscAsserted_A	719502818	1275	0	0
ErrorStIsTerminal_A	719502818	1065	0	0
EscStateOut_A	719361440	719289953	0	0
u_state_regs_A	719502818	719342415	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	240	0	0
T9	23446	46	0	0
T10	0	65	0	0
T11	0	37	0	0
T34	0	56	0	0
T35	0	36	0	0
T36	534887	0	0	0
T37	75395	0	0	0
T38	64878	0	0	0
T39	217347	0	0	0
T40	10376	0	0	0
T41	45043	0	0	0
T42	214889	0	0	0
T43	544120	0	0	0
T44	144470	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	558	0	0
T4	660916	3	0	0
T5	273899	1	0	0
T7	125594	1	0	0
T8	615279	6	0	0
T13	471891	1	0	0
T14	24872	0	0	0
T17	351907	0	0	0
T19	0	1	0	0
T22	0	2	0	0
T24	120300	0	0	0
T25	4128	0	0	0
T26	21641	0	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	22	0	0
T8	615279	1	0	0
T17	351907	0	0	0
T18	120589	0	0	0
T19	616722	0	0	0
T20	320156	0	0	0
T22	234002	0	0	0
T23	477570	0	0	0
T30	0	1	0	0
T45	143135	0	0	0
T46	58107	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T56	0	1	0	0
T59	0	1	0	0
T60	0	4	0	0
T62	0	2	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	19957	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	259	0	0
T4	660916	3	0	0
T5	273899	0	0	0
T7	125594	0	0	0
T8	615279	5	0	0
T13	471891	0	0	0
T14	24872	0	0	0
T17	351907	0	0	0
T22	0	1	0	0
T24	120300	0	0	0
T25	4128	0	0	0
T26	21641	0	0	0
T30	0	8	0	0
T31	0	2	0	0
T33	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719363146	320786669	0	0
T1	199888	199825	0	0
T2	2958	2148	0	0
T3	34584	30531	0	0
T4	660916	632463	0	0
T6	574821	277919	0	0
T12	61336	61268	0	0
T13	471891	20131	0	0
T14	24872	24795	0	0
T24	120300	120236	0	0
T25	4128	4042	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	637	0	0
T4	660916	4	0	0
T5	273899	2	0	0
T7	125594	1	0	0
T8	615279	6	0	0
T13	471891	1	0	0
T14	24872	0	0	0
T17	351907	0	0	0
T19	0	1	0	0
T22	0	2	0	0
T24	120300	0	0	0
T25	4128	0	0	0
T26	21641	0	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	626	0	0
T4	660916	4	0	0
T5	273899	2	0	0
T7	125594	1	0	0
T8	615279	6	0	0
T13	471891	1	0	0
T14	24872	0	0	0
T17	351907	0	0	0
T19	0	1	0	0
T22	0	2	0	0
T24	120300	0	0	0
T25	4128	0	0	0
T26	21641	0	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	608	0	0
T4	660916	4	0	0
T5	273899	2	0	0
T7	125594	1	0	0
T8	615279	4	0	0
T13	471891	1	0	0
T14	24872	0	0	0
T17	351907	0	0	0
T19	0	1	0	0
T22	0	2	0	0
T24	120300	0	0	0
T25	4128	0	0	0
T26	21641	0	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	600	0	0
T4	660916	4	0	0
T5	273899	2	0	0
T7	125594	1	0	0
T8	615279	4	0	0
T13	471891	1	0	0
T14	24872	0	0	0
T17	351907	0	0	0
T19	0	1	0	0
T22	0	2	0	0
T24	120300	0	0	0
T25	4128	0	0	0
T26	21641	0	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	666	0	0
T4	660916	7	0	0
T5	273899	7	0	0
T7	125594	0	0	0
T8	615279	2	0	0
T13	471891	0	0	0
T14	24872	0	0	0
T17	351907	0	0	0
T24	120300	0	0	0
T25	4128	0	0	0
T26	21641	7	0	0
T30	0	1	0	0
T33	0	2	0	0
T66	0	5	0	0
T75	0	1	0	0
T81	0	2	0	0
T82	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	85073	0	0
T4	660916	878	0	0
T5	273899	876	0	0
T7	125594	0	0	0
T8	615279	42	0	0
T13	471891	0	0	0
T14	24872	0	0	0
T17	351907	0	0	0
T24	120300	0	0	0
T25	4128	0	0	0
T26	21641	615	0	0
T30	0	2	0	0
T33	0	111	0	0
T66	0	431	0	0
T75	0	697	0	0
T81	0	286	0	0
T82	0	8	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	573	0	0
T4	660916	5	0	0
T5	273899	6	0	0
T7	125594	0	0	0
T8	615279	1	0	0
T13	471891	0	0	0
T14	24872	0	0	0
T17	351907	0	0	0
T24	120300	0	0	0
T25	4128	0	0	0
T26	21641	7	0	0
T27	0	6	0	0
T33	0	2	0	0
T66	0	5	0	0
T81	0	2	0	0
T83	0	1	0	0
T86	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	69	0	0
T4	660916	2	0	0
T5	273899	1	0	0
T7	125594	0	0	0
T8	615279	0	0	0
T13	471891	0	0	0
T14	24872	0	0	0
T17	351907	0	0	0
T24	120300	0	0	0
T25	4128	0	0	0
T26	21641	0	0	0
T28	0	1	0	0
T38	0	1	0	0
T75	0	1	0	0
T79	0	1	0	0
T82	0	1	0	0
T87	0	1	0	0
T89	0	1	0	0
T90	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	1275	0	0
T9	23446	172	0	0
T10	0	390	0	0
T11	0	185	0	0
T34	0	358	0	0
T35	0	170	0	0
T36	534887	0	0	0
T37	75395	0	0	0
T38	64878	0	0	0
T39	217347	0	0	0
T40	10376	0	0	0
T41	45043	0	0	0
T42	214889	0	0	0
T43	544120	0	0	0
T44	144470	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	1065	0	0
T9	23446	142	0	0
T10	0	330	0	0
T11	0	155	0	0
T34	0	298	0	0
T35	0	140	0	0
T36	534887	0	0	0
T37	75395	0	0	0
T38	64878	0	0	0
T39	217347	0	0	0
T40	10376	0	0	0
T41	45043	0	0	0
T42	214889	0	0	0
T43	544120	0	0	0
T44	144470	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719361440	719289953	0	0
T1	199888	199826	0	0
T2	2958	2895	0	0
T3	34584	34533	0	0
T4	660916	660860	0	0
T6	574821	574733	0	0
T12	61336	61269	0	0
T13	471891	471805	0	0
T14	24872	24796	0	0
T24	120300	120237	0	0
T25	4128	4043	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	719342415	0	0
T1	199888	199826	0	0
T2	2958	2895	0	0
T3	34584	34533	0	0
T4	660916	660860	0	0
T6	574821	574733	0	0
T12	61336	61269	0	0
T13	471891	471805	0	0
T14	24872	24796	0	0
T24	120300	120237	0	0
T25	4128	4043	0	0