Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.62	100.00	100.00	86.49			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.77	100.00		96.31			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	86.49			86.49

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.30	100.00	100.00	89.19			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.77	100.00		96.31			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	89.19			89.19

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.97	100.00	100.00	91.89			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.77	100.00		96.31			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	91.89			91.89

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.30	100.00	100.00	89.19			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.77	100.00		96.31			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	89.19			89.19

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T12,T6
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T231,T232
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	13521	0	0
DisabledNoTrigBkwd_A	2147483647	792555	0	0
DisabledNoTrigFwd_A	2147483647	1612397378	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13521	0	0
T2	2958	533	0	0
T58	356377	0	0	0
T61	16482	0	0	0
T231	908	198	0	0
T232	883	197	0	0
T233	2486	266	0	0
T234	1289	520	0	0
T235	4310	864	0	0
T236	0	1020	0	0
T237	0	1449	0	0
T238	0	377	0	0
T239	0	720	0	0
T240	0	757	0	0
T241	0	237	0	0
T242	0	659	0	0
T243	0	391	0	0
T244	0	1218	0	0
T245	0	198	0	0
T246	0	1193	0	0
T247	0	940	0	0
T248	0	1053	0	0
T249	0	731	0	0
T250	53212	0	0	0
T251	48285	0	0	0
T252	56518	0	0	0
T253	332298	0	0	0
T254	22063	0	0	0
T255	71892	0	0	0
T256	344552	0	0	0
T257	77572	0	0	0
T258	24580	0	0	0
T259	570056	0	0	0
T260	165199	0	0	0
T261	588863	0	0	0
T262	8347	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	792555	0	0
T1	599664	671	0	0
T2	8874	8	0	0
T3	103752	78	0	0
T4	2643664	7498	0	0
T5	273899	1537	0	0
T6	1724463	2	0	0
T7	125594	4761	0	0
T8	615279	2000	0	0
T12	184008	37	0	0
T13	1887564	580	0	0
T14	99488	795	0	0
T17	351907	3089	0	0
T19	0	9	0	0
T22	0	19	0	0
T24	481200	6	0	0
T25	16512	0	0	0
T26	21641	0	0	0
T45	0	179	0	0
T46	0	100	0	0
T47	0	2803	0	0
T48	0	130	0	0
T49	0	108	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1612397378	0	0
T1	799552	1118309	0	0
T2	11832	8604	0	0
T3	138336	100214	0	0
T4	2643664	1978895	0	0
T6	2299284	1371368	0	0
T12	245344	122616	0	0
T13	1887564	47639	0	0
T14	99488	47809	0	0
T24	481200	432170	0	0
T25	16512	13259	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T24
1	1	Covered	T1,T3,T12

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T235,T240,T244
1	1	Covered	T1,T3,T12

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	719502818	5816	0	0
DisabledNoTrigBkwd_A	719502818	255089	0	0
DisabledNoTrigFwd_A	719502818	367837345	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	5816	0	0
T61	16482	0	0	0
T235	4310	864	0	0
T240	0	757	0	0
T244	0	1218	0	0
T246	0	1193	0	0
T248	0	1053	0	0
T249	0	731	0	0
T255	71892	0	0	0
T256	344552	0	0	0
T257	77572	0	0	0
T258	24580	0	0	0
T259	570056	0	0	0
T260	165199	0	0	0
T261	588863	0	0	0
T262	8347	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	255089	0	0
T1	199888	642	0	0
T2	2958	0	0	0
T3	34584	78	0	0
T4	660916	7369	0	0
T5	0	1238	0	0
T6	574821	0	0	0
T8	0	299	0	0
T12	61336	0	0	0
T13	471891	142	0	0
T14	24872	1	0	0
T17	0	3088	0	0
T24	120300	6	0	0
T25	4128	0	0	0
T45	0	109	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	367837345	0	0
T1	199888	173020	0	0
T2	2958	2131	0	0
T3	34584	616	0	0
T4	660916	101774	0	0
T6	574821	514670	0	0
T12	61336	611	0	0
T13	471891	9139	0	0
T14	24872	21569	0	0
T24	120300	76375	0	0
T25	4128	4043	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T12,T4
1	1	Covered	T4,T13,T5

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T231,T236,T237
1	1	Covered	T4,T13,T5

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T13,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T13,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	719502818	2667	0	0
DisabledNoTrigBkwd_A	719502818	202829	0	0
DisabledNoTrigFwd_A	719502818	409948132	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	2667	0	0
T58	356377	0	0	0
T231	908	198	0	0
T232	883	0	0	0
T233	2486	0	0	0
T234	1289	0	0	0
T236	0	1020	0	0
T237	0	1449	0	0
T250	53212	0	0	0
T251	48285	0	0	0
T252	56518	0	0	0
T253	332298	0	0	0
T254	22063	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	202829	0	0
T4	660916	9	0	0
T5	273899	1	0	0
T7	125594	2372	0	0
T8	615279	1693	0	0
T13	471891	164	0	0
T14	24872	0	0	0
T17	351907	0	0	0
T19	0	9	0	0
T22	0	15	0	0
T24	120300	0	0	0
T25	4128	0	0	0
T26	21641	0	0	0
T47	0	2803	0	0
T48	0	130	0	0
T49	0	108	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	409948132	0	0
T1	199888	199826	0	0
T2	2958	2148	0	0
T3	34584	30532	0	0
T4	660916	636484	0	0
T6	574821	277920	0	0
T12	61336	61269	0	0
T13	471891	20131	0	0
T14	24872	24796	0	0
T24	120300	120237	0	0
T25	4128	4043	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T12
1	0	Covered	T1,T12,T4
1	1	Covered	T1,T2,T12

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T243,T245
1	1	Covered	T1,T2,T12

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T12

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	719502818	2062	0	0
DisabledNoTrigBkwd_A	719502818	159150	0	0
DisabledNoTrigFwd_A	719502818	454121651	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	2062	0	0
T2	2958	533	0	0
T3	34584	0	0	0
T4	660916	0	0	0
T5	273899	0	0	0
T6	574821	0	0	0
T12	61336	0	0	0
T13	471891	0	0	0
T14	24872	0	0	0
T24	120300	0	0	0
T25	4128	0	0	0
T243	0	391	0	0
T245	0	198	0	0
T247	0	940	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	159150	0	0
T1	199888	15	0	0
T2	2958	8	0	0
T3	34584	0	0	0
T4	660916	92	0	0
T5	0	111	0	0
T6	574821	0	0	0
T7	0	2389	0	0
T12	61336	37	0	0
T13	471891	149	0	0
T14	24872	770	0	0
T22	0	4	0	0
T24	120300	0	0	0
T25	4128	0	0	0
T45	0	69	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	454121651	0	0
T1	199888	463723	0	0
T2	2958	2157	0	0
T3	34584	34533	0	0
T4	660916	594386	0	0
T6	574821	152738	0	0
T12	61336	4715	0	0
T13	471891	9176	0	0
T14	24872	720	0	0
T24	120300	115321	0	0
T25	4128	1604	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T12
1	0	Covered	T1,T12,T6
1	1	Covered	T1,T12,T6

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T232,T233,T234
1	1	Covered	T1,T12,T6

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	719502818	2976	0	0
DisabledNoTrigBkwd_A	719502818	175487	0	0
DisabledNoTrigFwd_A	719502818	380490250	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	2976	0	0
T58	356377	0	0	0
T105	844478	0	0	0
T232	883	197	0	0
T233	2486	266	0	0
T234	1289	520	0	0
T238	0	377	0	0
T239	0	720	0	0
T241	0	237	0	0
T242	0	659	0	0
T250	53212	0	0	0
T251	48285	0	0	0
T252	56518	0	0	0
T253	332298	0	0	0
T254	22063	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	175487	0	0
T1	199888	14	0	0
T2	2958	0	0	0
T3	34584	0	0	0
T4	660916	28	0	0
T5	0	187	0	0
T6	574821	2	0	0
T8	0	8	0	0
T12	61336	0	0	0
T13	471891	125	0	0
T14	24872	24	0	0
T17	0	1	0	0
T24	120300	0	0	0
T25	4128	0	0	0
T45	0	1	0	0
T46	0	100	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	719502818	380490250	0	0
T1	199888	281740	0	0
T2	2958	2168	0	0
T3	34584	34533	0	0
T4	660916	646251	0	0
T6	574821	426040	0	0
T12	61336	56021	0	0
T13	471891	9193	0	0
T14	24872	724	0	0
T24	120300	120237	0	0
T25	4128	3569	0	0