Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.gen_classes[0].u_esc_timer.u_prim_count

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
37.14 37.14


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
37.14 37.14


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.11 100.00 95.56 100.00 100.00 100.00 gen_classes[0].u_esc_timer


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_classes[1].u_esc_timer.u_prim_count

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
37.14 37.14


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
37.14 37.14


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.11 100.00 95.56 100.00 100.00 100.00 gen_classes[1].u_esc_timer


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_classes[2].u_esc_timer.u_prim_count

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
37.14 37.14


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
37.14 37.14


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.67 100.00 93.33 100.00 100.00 100.00 gen_classes[2].u_esc_timer


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_classes[3].u_esc_timer.u_prim_count

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
37.14 37.14


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
37.14 37.14


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.67 100.00 93.33 100.00 100.00 100.00 gen_classes[3].u_esc_timer


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_classes[0].u_accu.u_prim_count

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.49 86.49


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.49 86.49


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 gen_classes[0].u_accu


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_classes[1].u_accu.u_prim_count

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.19 89.19


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.19 89.19


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 gen_classes[1].u_accu


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_classes[3].u_accu.u_prim_count

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.19 89.19


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.19 89.19


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 gen_classes[3].u_accu


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_classes[2].u_accu.u_prim_count

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.89 91.89


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.89 91.89


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 gen_classes[2].u_accu


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_ping_timer.u_prim_count_esc_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.46 100.00 97.30 100.00 100.00 100.00 u_ping_timer


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_ping_timer.u_prim_count_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.46 100.00 97.30 100.00 100.00 100.00 u_ping_timer


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_count ( parameter Width=2,ResetValue=0,EnableAlertTriggerSVA=0,PossibleActions=5,NumCnt=2 )
Toggle Coverage for Module self-instances :
SCORETOGGLE
100.00 100.00
tb.dut.u_ping_timer.u_prim_count_esc_cnt

TotalCoveredPercent
Totals 7 7 100.00
Total Bits 18 18 100.00
Total Bits 0->1 9 9 100.00
Total Bits 1->0 9 9 100.00

Ports 7 7 100.00
Port Bits 18 18 100.00
Port Bits 0->1 9 9 100.00
Port Bits 1->0 9 9 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
clr_i Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[1:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T6,T5,T7 Yes T6,T5,T7 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[1:0] Yes Yes T6,T5,T7 Yes T6,T5,T7 OUTPUT
cnt_after_commit_o[1:0] Yes Yes T6,T5,T7 Yes T6,T5,T7 OUTPUT
err_o Yes Yes T9,T10,T11 Yes T9,T10,T11 OUTPUT


Toggle Coverage for Module : prim_count ( parameter Width=16,ResetValue=0,EnableAlertTriggerSVA=0,PossibleActions=10,NumCnt=2 + Width=16,ResetValue=0,EnableAlertTriggerSVA=0,PossibleActions=15,NumCnt=2 )
Toggle Coverage for Module self-instances :
SCORETOGGLE
100.00 100.00
tb.dut.u_ping_timer.u_prim_count_cnt

SCORETOGGLE
86.49 86.49
tb.dut.gen_classes[0].u_accu.u_prim_count

SCORETOGGLE
89.19 89.19
tb.dut.gen_classes[1].u_accu.u_prim_count

SCORETOGGLE
91.89 91.89
tb.dut.gen_classes[2].u_accu.u_prim_count

SCORETOGGLE
89.19 89.19
tb.dut.gen_classes[3].u_accu.u_prim_count

TotalCoveredPercent
Totals 9 9 100.00
Total Bits 108 108 100.00
Total Bits 0->1 54 54 100.00
Total Bits 1->0 54 54 100.00

Ports 9 9 100.00
Port Bits 108 108 100.00
Port Bits 0->1 54 54 100.00
Port Bits 1->0 54 54 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT
set_i Yes Yes T1,T3,T6 Yes T1,T3,T6 INPUT
set_cnt_i[15:0] Yes Yes T1,T3,T6 Yes T1,T3,T12 INPUT
incr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[15:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[15:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cnt_after_commit_o[15:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
err_o Yes Yes T9,T10,T11 Yes T9,T10,T11 OUTPUT


Toggle Coverage for Module : prim_count ( parameter Width=32,ResetValue=0,EnableAlertTriggerSVA=0,PossibleActions=7,NumCnt=2 )
Toggle Coverage for Module self-instances :
SCORETOGGLE
37.14 37.14
tb.dut.gen_classes[0].u_esc_timer.u_prim_count

SCORETOGGLE
37.14 37.14
tb.dut.gen_classes[1].u_esc_timer.u_prim_count

SCORETOGGLE
37.14 37.14
tb.dut.gen_classes[2].u_esc_timer.u_prim_count

SCORETOGGLE
37.14 37.14
tb.dut.gen_classes[3].u_esc_timer.u_prim_count

TotalCoveredPercent
Totals 8 6 75.00
Total Bits 140 52 37.14
Total Bits 0->1 70 26 37.14
Total Bits 1->0 70 26 37.14

Ports 8 6 75.00
Port Bits 140 52 37.14
Port Bits 0->1 70 26 37.14
Port Bits 1->0 70 26 37.14

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
set_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
set_cnt_i[31:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[31:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[9:0] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
cnt_o[31:10] No No No OUTPUT
cnt_after_commit_o[9:0] Yes Yes T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
cnt_after_commit_o[31:10] No No No OUTPUT
err_o Yes Yes T9,T10,T11 Yes T9,T10,T11 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer.u_prim_count
TotalCoveredPercent
Totals 8 6 75.00
Total Bits 140 52 37.14
Total Bits 0->1 70 26 37.14
Total Bits 1->0 70 26 37.14

Ports 8 6 75.00
Port Bits 140 52 37.14
Port Bits 0->1 70 26 37.14
Port Bits 1->0 70 26 37.14

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
set_i Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
set_cnt_i[31:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[31:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[9:0] Yes Yes *T1,*T3,T4 Yes T1,T3,T4 OUTPUT
cnt_o[31:10] No No No OUTPUT
cnt_after_commit_o[9:0] Yes Yes *T1,*T3,T4 Yes T1,T3,T4 OUTPUT
cnt_after_commit_o[31:10] No No No OUTPUT
err_o Yes Yes T9,T10,T11 Yes T9,T10,T11 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer.u_prim_count
TotalCoveredPercent
Totals 8 6 75.00
Total Bits 140 52 37.14
Total Bits 0->1 70 26 37.14
Total Bits 1->0 70 26 37.14

Ports 8 6 75.00
Port Bits 140 52 37.14
Port Bits 0->1 70 26 37.14
Port Bits 1->0 70 26 37.14

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
clr_i Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
set_i Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
set_cnt_i[31:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[31:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[9:0] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
cnt_o[31:10] No No No OUTPUT
cnt_after_commit_o[9:0] Yes Yes T4,T13,T5 Yes T4,T13,T5 OUTPUT
cnt_after_commit_o[31:10] No No No OUTPUT
err_o Yes Yes T9,T10,T11 Yes T9,T10,T11 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer.u_prim_count
TotalCoveredPercent
Totals 8 6 75.00
Total Bits 140 52 37.14
Total Bits 0->1 70 26 37.14
Total Bits 1->0 70 26 37.14

Ports 8 6 75.00
Port Bits 140 52 37.14
Port Bits 0->1 70 26 37.14
Port Bits 1->0 70 26 37.14

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T2,T12 Yes T1,T2,T12 INPUT
set_i Yes Yes T1,T2,T12 Yes T1,T2,T12 INPUT
set_cnt_i[31:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T2,T12 Yes T1,T2,T12 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[31:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[9:0] Yes Yes T1,*T2,*T12 Yes T1,T2,T12 OUTPUT
cnt_o[31:10] No No No OUTPUT
cnt_after_commit_o[9:0] Yes Yes T1,*T2,*T12 Yes T1,T2,T12 OUTPUT
cnt_after_commit_o[31:10] No No No OUTPUT
err_o Yes Yes T9,T10,T11 Yes T9,T10,T11 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer.u_prim_count
TotalCoveredPercent
Totals 8 6 75.00
Total Bits 140 52 37.14
Total Bits 0->1 70 26 37.14
Total Bits 1->0 70 26 37.14

Ports 8 6 75.00
Port Bits 140 52 37.14
Port Bits 0->1 70 26 37.14
Port Bits 1->0 70 26 37.14

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T6,T4 Yes T1,T6,T4 INPUT
set_i Yes Yes T1,T6,T4 Yes T1,T6,T4 INPUT
set_cnt_i[31:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T6,T4 Yes T1,T6,T4 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[31:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[9:0] Yes Yes T1,T6,T4 Yes T1,T6,T4 OUTPUT
cnt_o[31:10] No No No OUTPUT
cnt_after_commit_o[9:0] Yes Yes T1,T6,T4 Yes T1,T6,T4 OUTPUT
cnt_after_commit_o[31:10] No No No OUTPUT
err_o Yes Yes T9,T10,T11 Yes T9,T10,T11 OUTPUT

Toggle Coverage for Instance : tb.dut.gen_classes[0].u_accu.u_prim_count
TotalCoveredPercent
Totals 7 5 71.43
Total Bits 74 64 86.49
Total Bits 0->1 37 33 89.19
Total Bits 1->0 37 31 83.78

Ports 7 5 71.43
Port Bits 74 64 86.49
Port Bits 0->1 37 33 89.19
Port Bits 1->0 37 31 83.78

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T4,T14 Yes T1,T4,T14 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[15:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T3,T12 Yes T1,T3,T12 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[15:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[12:0] Yes Yes *T1,*T3,*T12 Yes T1,T3,T12 OUTPUT
cnt_o[13] No No Yes T15 OUTPUT
cnt_o[15:14] No No No OUTPUT
cnt_after_commit_o[12:0] Yes Yes *T1,*T3,*T12 Yes T1,T3,T12 OUTPUT
cnt_after_commit_o[13] No No Yes T15 OUTPUT
cnt_after_commit_o[15:14] No No No OUTPUT
err_o Yes Yes T9,T10,T11 Yes T9,T10,T11 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_classes[1].u_accu.u_prim_count
TotalCoveredPercent
Totals 7 5 71.43
Total Bits 74 66 89.19
Total Bits 0->1 37 33 89.19
Total Bits 1->0 37 33 89.19

Ports 7 5 71.43
Port Bits 74 66 89.19
Port Bits 0->1 37 33 89.19
Port Bits 1->0 37 33 89.19

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T12,T6 Yes T1,T12,T6 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[15:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T4,T13,T5 Yes T4,T13,T5 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[15:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[13:0] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 OUTPUT
cnt_o[15:14] No No No OUTPUT
cnt_after_commit_o[13:0] Yes Yes *T4,*T13,*T5 Yes T4,T13,T5 OUTPUT
cnt_after_commit_o[15:14] No No No OUTPUT
err_o Yes Yes T9,T10,T11 Yes T9,T10,T11 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_classes[3].u_accu.u_prim_count
TotalCoveredPercent
Totals 7 5 71.43
Total Bits 74 66 89.19
Total Bits 0->1 37 33 89.19
Total Bits 1->0 37 33 89.19

Ports 7 5 71.43
Port Bits 74 66 89.19
Port Bits 0->1 37 33 89.19
Port Bits 1->0 37 33 89.19

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[15:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T12,T6 Yes T1,T12,T6 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[15:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[13:0] Yes Yes *T1,*T12,*T6 Yes T1,T12,T6 OUTPUT
cnt_o[15:14] No No No OUTPUT
cnt_after_commit_o[13:0] Yes Yes *T1,*T12,*T6 Yes T1,T12,T6 OUTPUT
cnt_after_commit_o[15:14] No No No OUTPUT
err_o Yes Yes T9,T10,T11 Yes T9,T10,T11 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.gen_classes[2].u_accu.u_prim_count
TotalCoveredPercent
Totals 7 5 71.43
Total Bits 74 68 91.89
Total Bits 0->1 37 35 94.59
Total Bits 1->0 37 33 89.19

Ports 7 5 71.43
Port Bits 74 68 91.89
Port Bits 0->1 37 35 94.59
Port Bits 1->0 37 33 89.19

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T3,T6 Yes T1,T3,T6 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[15:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T1,T2,T12 Yes T1,T2,T12 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[15:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[13:0] Yes Yes *T1,*T2,*T12 Yes T1,T2,T12 OUTPUT
cnt_o[14] No No Yes T16 OUTPUT
cnt_o[15] No No No OUTPUT
cnt_after_commit_o[13:0] Yes Yes *T1,*T2,*T12 Yes T1,T2,T12 OUTPUT
cnt_after_commit_o[14] No No Yes T16 OUTPUT
cnt_after_commit_o[15] No No No OUTPUT
err_o Yes Yes T9,T10,T11 Yes T9,T10,T11 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_ping_timer.u_prim_count_esc_cnt
TotalCoveredPercent
Totals 7 7 100.00
Total Bits 18 18 100.00
Total Bits 0->1 9 9 100.00
Total Bits 1->0 9 9 100.00

Ports 7 7 100.00
Port Bits 18 18 100.00
Port Bits 0->1 9 9 100.00
Port Bits 1->0 9 9 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
clr_i Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
set_i Unreachable Unreachable Unreachable INPUT
set_cnt_i[1:0] Unreachable Unreachable Unreachable INPUT
incr_en_i Yes Yes T6,T5,T7 Yes T6,T5,T7 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[1:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[1:0] Yes Yes T6,T5,T7 Yes T6,T5,T7 OUTPUT
cnt_after_commit_o[1:0] Yes Yes T6,T5,T7 Yes T6,T5,T7 OUTPUT
err_o Yes Yes T9,T10,T11 Yes T9,T10,T11 OUTPUT

Toggle Coverage for Instance : tb.dut.u_ping_timer.u_prim_count_cnt
TotalCoveredPercent
Totals 7 7 100.00
Total Bits 104 104 100.00
Total Bits 0->1 52 52 100.00
Total Bits 1->0 52 52 100.00

Ports 7 7 100.00
Port Bits 104 104 100.00
Port Bits 0->1 52 52 100.00
Port Bits 1->0 52 52 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Yes Yes T1,T3,T6 Yes T1,T3,T6 INPUT
set_cnt_i[15:0] Yes Yes T1,T3,T6 Yes T1,T3,T12 INPUT
incr_en_i Unreachable Unreachable Unreachable INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[15:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[15:0] Yes Yes T1,T3,T6 Yes T1,T3,T6 OUTPUT
cnt_after_commit_o[15:0] Yes Yes T1,T3,T6 Yes T1,T3,T6 OUTPUT
err_o Yes Yes T9,T10,T11 Yes T9,T10,T11 OUTPUT

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%