Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	52017831	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

24574471

1

T1

144

T2

130

T3

270

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	12181621	1			T1	66		T2	73		T3	105
values[0x0]	32168892	1			T1	178		T2	167		T3	412
values[0x1]	32241789	1			T1	172		T2	213		T3	448

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45277539	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

31314763

1

T1

190

T2

181

T3

345

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	235949	1			T1	2		T2	4		T3	4
valid_sources[0x01]	232132	1			T1	1		T3	8		T10	33
valid_sources[0x02]	230295	1			T1	3		T3	3		T10	26
valid_sources[0x03]	238254	1			T1	1		T2	11		T3	3
valid_sources[0x04]	231636	1			T3	10		T10	18		T12	18
valid_sources[0x05]	230850	1			T1	2		T2	1		T3	7
valid_sources[0x06]	231905	1			T1	1		T3	9		T10	20
valid_sources[0x07]	501946	1			T1	2		T3	4		T10	27
valid_sources[0x08]	240219	1			T1	2		T2	1		T3	5
valid_sources[0x09]	234248	1			T3	3		T10	12		T22	40
valid_sources[0x0a]	239552	1			T1	4		T3	10		T10	20
valid_sources[0x0b]	239067	1			T1	3		T2	7		T10	16
valid_sources[0x0c]	231535	1			T1	2		T2	6		T3	1
valid_sources[0x0d]	244125	1			T2	7		T3	3		T10	26
valid_sources[0x0e]	230452	1			T1	2		T2	3		T3	3
valid_sources[0x0f]	529698	1			T1	1		T3	9		T10	19
valid_sources[0x10]	234602	1			T1	2		T3	7		T10	22
valid_sources[0x11]	232727	1			T1	2		T3	4		T10	10
valid_sources[0x12]	242684	1			T1	1		T3	3		T10	23
valid_sources[0x13]	232528	1			T3	10		T10	12		T12	11
valid_sources[0x14]	233288	1			T1	3		T3	6		T10	41
valid_sources[0x15]	232698	1			T1	4		T10	17		T22	40
valid_sources[0x16]	535980	1			T2	2		T3	4		T10	22
valid_sources[0x17]	235367	1			T1	6		T10	11		T22	40
valid_sources[0x18]	233716	1			T3	8		T10	29		T22	38
valid_sources[0x19]	248519	1			T1	1		T2	15		T3	3
valid_sources[0x1a]	232950	1			T1	3		T3	11		T10	18
valid_sources[0x1b]	273270	1			T3	3		T10	20		T12	34
valid_sources[0x1c]	244640	1			T3	3		T10	40		T12	33
valid_sources[0x1d]	230009	1			T1	1		T2	5		T3	4
valid_sources[0x1e]	233180	1			T1	4		T2	1		T3	2
valid_sources[0x1f]	231599	1			T1	3		T2	1		T3	4
valid_sources[0x20]	648536	1			T1	2		T2	3		T3	7
valid_sources[0x21]	246668	1			T1	3		T3	5		T10	25
valid_sources[0x22]	235255	1			T10	18		T22	36		T42	30
valid_sources[0x23]	233494	1			T2	2		T3	6		T10	32
valid_sources[0x24]	236767	1			T1	1		T2	2		T3	4
valid_sources[0x25]	236187	1			T1	1		T2	2		T3	7
valid_sources[0x26]	233520	1			T1	1		T3	3		T10	20
valid_sources[0x27]	232426	1			T1	5		T2	7		T3	1
valid_sources[0x28]	232948	1			T1	2		T3	2		T10	27
valid_sources[0x29]	230657	1			T1	1		T2	1		T3	11
valid_sources[0x2a]	714367	1			T1	3		T2	6		T3	4
valid_sources[0x2b]	232565	1			T1	3		T3	10		T10	16
valid_sources[0x2c]	235574	1			T1	1		T3	5		T10	16
valid_sources[0x2d]	581334	1			T3	7		T10	24		T22	43
valid_sources[0x2e]	233458	1			T1	1		T3	2		T10	29
valid_sources[0x2f]	233459	1			T1	6		T10	18		T22	34
valid_sources[0x30]	232629	1			T1	1		T2	6		T3	4
valid_sources[0x31]	269512	1			T1	1		T2	4		T3	3
valid_sources[0x32]	241620	1			T3	7		T10	46		T22	42
valid_sources[0x33]	228649	1			T1	5		T3	1		T10	22
valid_sources[0x34]	232964	1			T1	2		T2	1		T3	4
valid_sources[0x35]	231299	1			T1	2		T2	5		T10	27
valid_sources[0x36]	232827	1			T1	1		T2	5		T10	15
valid_sources[0x37]	683976	1			T1	1		T2	2		T3	2
valid_sources[0x38]	233476	1			T3	4		T10	24		T22	34
valid_sources[0x39]	236740	1			T3	4		T10	26		T22	50
valid_sources[0x3a]	688540	1			T1	2		T2	3		T3	1
valid_sources[0x3b]	231537	1			T1	3		T3	1		T10	14
valid_sources[0x3c]	229524	1			T1	4		T3	2		T10	11
valid_sources[0x3d]	232127	1			T1	2		T3	1		T10	33
valid_sources[0x3e]	462498	1			T3	2		T10	13		T22	43
valid_sources[0x3f]	231788	1			T1	2		T3	3		T10	33
valid_sources[0x40]	618556	1			T1	1		T2	5		T3	3
valid_sources[0x41]	244983	1			T1	1		T3	7		T10	13
valid_sources[0x42]	232826	1			T1	2		T3	3		T10	26
valid_sources[0x43]	231687	1			T3	6		T10	18		T22	41
valid_sources[0x44]	234100	1			T1	4		T2	1		T3	3
valid_sources[0x45]	234215	1			T1	1		T3	9		T10	16
valid_sources[0x46]	274465	1			T1	5		T2	13		T3	5
valid_sources[0x47]	232642	1			T1	2		T3	4		T10	28
valid_sources[0x48]	237965	1			T1	9		T3	5		T10	15
valid_sources[0x49]	241562	1			T3	7		T9	6233		T10	19
valid_sources[0x4a]	234875	1			T1	3		T3	6		T10	32
valid_sources[0x4b]	229090	1			T1	1		T2	9		T10	16
valid_sources[0x4c]	1019914	1			T1	3		T3	2		T10	28
valid_sources[0x4d]	231772	1			T1	1		T3	4		T10	21
valid_sources[0x4e]	231378	1			T1	1		T3	4		T10	18
valid_sources[0x4f]	231595	1			T1	1		T3	7		T10	22
valid_sources[0x50]	231117	1			T1	1		T3	5		T10	19
valid_sources[0x51]	243449	1			T2	2		T10	40		T22	39
valid_sources[0x52]	235193	1			T1	3		T3	3		T10	15
valid_sources[0x53]	230761	1			T1	2		T2	8		T3	3
valid_sources[0x54]	231574	1			T1	1		T2	5		T3	9
valid_sources[0x55]	229402	1			T3	10		T10	11		T22	43
valid_sources[0x56]	231607	1			T1	3		T3	3		T10	44
valid_sources[0x57]	234765	1			T1	2		T2	8		T3	3
valid_sources[0x58]	233308	1			T1	1		T2	6		T3	6
valid_sources[0x59]	805285	1			T1	3		T3	7		T10	30
valid_sources[0x5a]	233067	1			T2	7		T10	21		T22	38
valid_sources[0x5b]	241147	1			T1	3		T2	1		T3	2
valid_sources[0x5c]	233588	1			T1	3		T2	5		T3	5
valid_sources[0x5d]	232164	1			T2	2		T3	4		T10	44
valid_sources[0x5e]	233018	1			T2	4		T3	2		T10	17
valid_sources[0x5f]	255373	1			T10	11		T22	41		T23	2
valid_sources[0x60]	811296	1			T3	1		T10	32		T22	56
valid_sources[0x61]	232371	1			T1	2		T3	4		T10	26
valid_sources[0x62]	234489	1			T1	1		T2	4		T3	2
valid_sources[0x63]	501142	1			T1	3		T3	7		T10	12
valid_sources[0x64]	230958	1			T3	1		T10	25		T12	30
valid_sources[0x65]	235283	1			T1	1		T3	6		T10	12
valid_sources[0x66]	234080	1			T2	4		T3	3		T10	30
valid_sources[0x67]	232825	1			T1	2		T10	21		T12	24
valid_sources[0x68]	240262	1			T1	2		T2	1		T10	30
valid_sources[0x69]	243121	1			T1	4		T2	1		T3	3
valid_sources[0x6a]	233824	1			T1	2		T2	1		T3	1
valid_sources[0x6b]	238375	1			T1	2		T2	7		T3	5
valid_sources[0x6c]	608930	1			T1	5		T3	2		T10	3
valid_sources[0x6d]	244008	1			T1	3		T3	1		T10	20
valid_sources[0x6e]	233581	1			T1	1		T3	4		T10	22
valid_sources[0x6f]	231190	1			T1	2		T2	4		T3	1
valid_sources[0x70]	231049	1			T1	2		T3	7		T10	2
valid_sources[0x71]	609339	1			T1	2		T2	10		T3	1
valid_sources[0x72]	241912	1			T2	2		T3	4		T10	5
valid_sources[0x73]	235197	1			T1	2		T3	1		T10	26
valid_sources[0x74]	230608	1			T1	2		T3	2		T10	16
valid_sources[0x75]	234036	1			T1	2		T3	2		T10	16
valid_sources[0x76]	231993	1			T1	1		T3	5		T10	14
valid_sources[0x77]	233780	1			T1	2		T3	6		T10	28
valid_sources[0x78]	232558	1			T2	5		T3	8		T10	17
valid_sources[0x79]	233190	1			T1	2		T2	7		T3	1
valid_sources[0x7a]	448118	1			T3	4		T10	17		T22	39
valid_sources[0x7b]	512361	1			T2	1		T3	1		T10	13
valid_sources[0x7c]	232644	1			T2	3		T3	4		T10	28
valid_sources[0x7d]	233084	1			T1	1		T2	1		T3	2
valid_sources[0x7e]	234660	1			T1	1		T3	5		T10	15
valid_sources[0x7f]	444585	1			T1	3		T3	7		T10	8
valid_sources[0x80]	240212	1			T1	2		T10	24		T12	56

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5815497

1

T1

34

T2

40

T3

54

values[0x0]

all_enables

biggest_size

11984787

1

T1

67

T2

57

T3

148

values[0x1]

all_enables

biggest_size

6774187

1

T1

43

T2

33

T3

68