Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T2 T3 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T10,T13
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T23,T46
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	16883	0	0
DisabledNoTrigBkwd_A	2147483647	733255	0	0
DisabledNoTrigFwd_A	2147483647	1160471285	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16883	0	0
T1	3625	1156	0	0
T2	17504	0	0	0
T3	2516	0	0	0
T4	34842	0	0	0
T5	15921	0	0	0
T9	23434	0	0	0
T10	21386	0	0	0
T11	29498	0	0	0
T12	4255	0	0	0
T13	44856	0	0	0
T14	26042	0	0	0
T22	24928	0	0	0
T23	4116	480	0	0
T24	14854	0	0	0
T37	11404	0	0	0
T42	20946	0	0	0
T43	46627	0	0	0
T44	15130	0	0	0
T45	22910	0	0	0
T46	3965	1555	0	0
T78	0	932	0	0
T94	8163	0	0	0
T116	0	463	0	0
T127	0	742	0	0
T144	0	326	0	0
T154	0	755	0	0
T242	0	814	0	0
T243	0	865	0	0
T244	0	1050	0	0
T245	0	1004	0	0
T246	0	1392	0	0
T247	0	604	0	0
T248	0	765	0	0
T249	0	506	0	0
T250	0	726	0	0
T251	0	1148	0	0
T252	0	645	0	0
T253	0	955	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	733255	0	0
T1	3625	36	0	0
T2	17504	0	0	0
T3	10064	10	0	0
T4	139368	0	0	0
T9	93736	66	0	0
T10	85544	32	0	0
T11	0	9	0	0
T12	17020	7	0	0
T13	179424	0	0	0
T14	104168	0	0	0
T15	0	3	0	0
T22	99712	1399	0	0
T23	12348	8	0	0
T24	0	11	0	0
T37	0	12	0	0
T42	62838	0	0	0
T43	0	4	0	0
T46	0	40	0	0
T47	0	4	0	0
T48	0	6	0	0
T49	0	87	0	0
T50	0	195	0	0
T51	0	1	0	0
T52	0	57	0	0
T53	0	6	0	0
T144	0	9	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1160471285	0	0
T1	14500	8644	0	0
T2	70016	8709	0	0
T3	10064	4642	0	0
T4	139368	37704	0	0
T9	93736	69171	0	0
T10	85544	38142	0	0
T12	17020	7463	0	0
T13	179424	136395	0	0
T14	104168	78411	0	0
T22	99712	27444	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T2 T3 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T10,T13
1	1	Covered	T1,T3,T9

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T242,T244
1	1	Covered	T1,T3,T9

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T22
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T9

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	574695525	5817	0	0
DisabledNoTrigBkwd_A	574695525	193080	0	0
DisabledNoTrigFwd_A	574695525	280947005	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	5817	0	0
T1	3625	1156	0	0
T2	17504	0	0	0
T3	2516	0	0	0
T4	34842	0	0	0
T9	23434	0	0	0
T10	21386	0	0	0
T12	4255	0	0	0
T13	44856	0	0	0
T14	26042	0	0	0
T22	24928	0	0	0
T242	0	814	0	0
T244	0	1050	0	0
T245	0	1004	0	0
T251	0	1148	0	0
T252	0	645	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	193080	0	0
T1	3625	36	0	0
T2	17504	0	0	0
T3	2516	2	0	0
T4	34842	0	0	0
T9	23434	66	0	0
T10	21386	2	0	0
T11	0	9	0	0
T12	4255	4	0	0
T13	44856	0	0	0
T14	26042	0	0	0
T22	24928	23	0	0
T24	0	11	0	0
T43	0	4	0	0
T47	0	4	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	280947005	0	0
T1	3625	2149	0	0
T2	17504	2158	0	0
T3	2516	1352	0	0
T4	34842	9426	0	0
T9	23434	643	0	0
T10	21386	18190	0	0
T12	4255	582	0	0
T13	44856	44782	0	0
T14	26042	582	0	0
T22	24928	3366	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T2 T3 T9 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T13,T12
1	1	Covered	T2,T3,T10

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T23,T154,T78
1	1	Covered	T2,T3,T10

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T10

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	574695525	3887	0	0
DisabledNoTrigBkwd_A	574695525	189124	0	0
DisabledNoTrigFwd_A	574695525	289851908	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	3887	0	0
T5	15921	0	0	0
T11	29498	0	0	0
T23	4116	480	0	0
T24	14854	0	0	0
T37	11404	0	0	0
T42	20946	0	0	0
T43	46627	0	0	0
T44	15130	0	0	0
T45	22910	0	0	0
T78	0	932	0	0
T94	8163	0	0	0
T154	0	755	0	0
T248	0	765	0	0
T253	0	955	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	189124	0	0
T3	2516	4	0	0
T4	34842	0	0	0
T9	23434	0	0	0
T10	21386	3	0	0
T12	4255	0	0	0
T13	44856	0	0	0
T14	26042	0	0	0
T22	24928	2	0	0
T23	4116	8	0	0
T37	0	2	0	0
T42	20946	0	0	0
T48	0	3	0	0
T49	0	16	0	0
T50	0	89	0	0
T52	0	57	0	0
T53	0	3	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	289851908	0	0
T1	3625	2153	0	0
T2	17504	2162	0	0
T3	2516	586	0	0
T4	34842	9426	0	0
T9	23434	21780	0	0
T10	21386	16284	0	0
T12	4255	2120	0	0
T13	44856	44782	0	0
T14	26042	25943	0	0
T22	24928	15816	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T2 T3 T9 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T10,T13
1	1	Covered	T3,T10,T12

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T46,T116,T246
1	1	Covered	T3,T10,T12

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T22
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T10,T12

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	574695525	3916	0	0
DisabledNoTrigBkwd_A	574695525	173536	0	0
DisabledNoTrigFwd_A	574695525	298228729	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	3916	0	0
T6	17700	0	0	0
T8	17366	0	0	0
T15	407895	0	0	0
T38	19440	0	0	0
T46	3965	1555	0	0
T47	4083	0	0	0
T48	11169	0	0	0
T49	77844	0	0	0
T87	34934	0	0	0
T116	0	463	0	0
T242	1613	0	0	0
T246	0	1392	0	0
T249	0	506	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	173536	0	0
T3	2516	2	0	0
T4	34842	0	0	0
T9	23434	0	0	0
T10	21386	14	0	0
T12	4255	3	0	0
T13	44856	0	0	0
T14	26042	0	0	0
T15	0	3	0	0
T22	24928	16	0	0
T23	4116	0	0	0
T37	0	10	0	0
T42	20946	0	0	0
T46	0	40	0	0
T48	0	2	0	0
T49	0	37	0	0
T50	0	11	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	298228729	0	0
T1	3625	2167	0	0
T2	17504	2185	0	0
T3	2516	1352	0	0
T4	34842	9426	0	0
T9	23434	23374	0	0
T10	21386	1832	0	0
T12	4255	590	0	0
T13	44856	44782	0	0
T14	26042	25943	0	0
T22	24928	3374	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T2 T3 T9 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T10,T12
1	1	Covered	T3,T10,T13

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T144,T243,T127
1	1	Covered	T3,T10,T13

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T42
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T10,T22

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	574695525	3263	0	0
DisabledNoTrigBkwd_A	574695525	177515	0	0
DisabledNoTrigFwd_A	574695525	291443643	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	3263	0	0
T55	96531	0	0	0
T84	930789	0	0	0
T89	100573	0	0	0
T90	98112	0	0	0
T127	0	742	0	0
T144	1139	326	0	0
T146	98090	0	0	0
T159	44749	0	0	0
T160	89375	0	0	0
T243	4387	865	0	0
T247	0	604	0	0
T250	0	726	0	0
T254	21694	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	177515	0	0
T3	2516	2	0	0
T4	34842	0	0	0
T9	23434	0	0	0
T10	21386	13	0	0
T12	4255	0	0	0
T13	44856	0	0	0
T14	26042	0	0	0
T22	24928	1358	0	0
T23	4116	0	0	0
T42	20946	0	0	0
T48	0	1	0	0
T49	0	34	0	0
T50	0	95	0	0
T51	0	1	0	0
T53	0	3	0	0
T144	0	9	0	0
T146	0	82	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	291443643	0	0
T1	3625	2175	0	0
T2	17504	2204	0	0
T3	2516	1352	0	0
T4	34842	9426	0	0
T9	23434	23374	0	0
T10	21386	1836	0	0
T12	4255	4171	0	0
T13	44856	2049	0	0
T14	26042	25943	0	0
T22	24928	4888	0	0