Line Coverage for Module :
prim_subreg_ext
| Line No. | Total | Covered | Percent |
TOTAL | | 5 | 5 | 100.00 |
CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
25 // between qs and ds
26 1/1 assign ds = d;
Tests: T1 T2 T3
27 1/1 assign qs = d;
Tests: T1 T2 T3
28 1/1 assign q = wd;
Tests: T1 T2 T3
29 1/1 assign qe = we;
Tests: T36 T28 T39
30 1/1 assign qre = re;
Tests: T1 T3 T9
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_intr_test_classa
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 26 | 0 | 0 | |
CONT_ASSIGN | 27 | 0 | 0 | |
CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 0 | 0 | |
25 // between qs and ds
26 unreachable assign ds = d;
27 unreachable assign qs = d;
28 1/1 assign q = wd;
Tests: T1 T2 T3
29 1/1 assign qe = we;
Tests: T36 T28 T39
30 unreachable assign qre = re;
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_intr_test_classb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 26 | 0 | 0 | |
CONT_ASSIGN | 27 | 0 | 0 | |
CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 0 | 0 | |
25 // between qs and ds
26 unreachable assign ds = d;
27 unreachable assign qs = d;
28 1/1 assign q = wd;
Tests: T1 T2 T3
29 1/1 assign qe = we;
Tests: T36 T28 T39
30 unreachable assign qre = re;
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_intr_test_classc
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 26 | 0 | 0 | |
CONT_ASSIGN | 27 | 0 | 0 | |
CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 0 | 0 | |
25 // between qs and ds
26 unreachable assign ds = d;
27 unreachable assign qs = d;
28 1/1 assign q = wd;
Tests: T1 T2 T3
29 1/1 assign qe = we;
Tests: T36 T28 T39
30 unreachable assign qre = re;
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_intr_test_classd
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 26 | 0 | 0 | |
CONT_ASSIGN | 27 | 0 | 0 | |
CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 30 | 0 | 0 | |
25 // between qs and ds
26 unreachable assign ds = d;
27 unreachable assign qs = d;
28 1/1 assign q = wd;
Tests: T1 T2 T3
29 1/1 assign qe = we;
Tests: T36 T28 T39
30 unreachable assign qre = re;
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_accum_cnt
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
CONT_ASSIGN | 28 | 0 | 0 | |
CONT_ASSIGN | 29 | 0 | 0 | |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
25 // between qs and ds
26 1/1 assign ds = d;
Tests: T1 T2 T3
27 1/1 assign qs = d;
Tests: T1 T2 T3
28 unreachable assign q = wd;
29 unreachable assign qe = we;
30 1/1 assign qre = re;
Tests: T1 T3 T9
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_esc_cnt
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
CONT_ASSIGN | 28 | 0 | 0 | |
CONT_ASSIGN | 29 | 0 | 0 | |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
25 // between qs and ds
26 1/1 assign ds = d;
Tests: T1 T2 T3
27 1/1 assign qs = d;
Tests: T1 T2 T3
28 unreachable assign q = wd;
29 unreachable assign qe = we;
30 1/1 assign qre = re;
Tests: T3 T9 T10
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_state
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
CONT_ASSIGN | 28 | 0 | 0 | |
CONT_ASSIGN | 29 | 0 | 0 | |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
25 // between qs and ds
26 1/1 assign ds = d;
Tests: T1 T2 T3
27 1/1 assign qs = d;
Tests: T1 T2 T3
28 unreachable assign q = wd;
29 unreachable assign qe = we;
30 1/1 assign qre = re;
Tests: T3 T9 T10
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_accum_cnt
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
CONT_ASSIGN | 28 | 0 | 0 | |
CONT_ASSIGN | 29 | 0 | 0 | |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
25 // between qs and ds
26 1/1 assign ds = d;
Tests: T2 T3 T9
27 1/1 assign qs = d;
Tests: T2 T3 T9
28 unreachable assign q = wd;
29 unreachable assign qe = we;
30 1/1 assign qre = re;
Tests: T1 T3 T9
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_esc_cnt
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
CONT_ASSIGN | 28 | 0 | 0 | |
CONT_ASSIGN | 29 | 0 | 0 | |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
25 // between qs and ds
26 1/1 assign ds = d;
Tests: T1 T2 T3
27 1/1 assign qs = d;
Tests: T1 T2 T3
28 unreachable assign q = wd;
29 unreachable assign qe = we;
30 1/1 assign qre = re;
Tests: T3 T9 T10
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_state
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
CONT_ASSIGN | 28 | 0 | 0 | |
CONT_ASSIGN | 29 | 0 | 0 | |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
25 // between qs and ds
26 1/1 assign ds = d;
Tests: T1 T2 T3
27 1/1 assign qs = d;
Tests: T1 T2 T3
28 unreachable assign q = wd;
29 unreachable assign qe = we;
30 1/1 assign qre = re;
Tests: T3 T9 T10
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_accum_cnt
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
CONT_ASSIGN | 28 | 0 | 0 | |
CONT_ASSIGN | 29 | 0 | 0 | |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
25 // between qs and ds
26 1/1 assign ds = d;
Tests: T2 T3 T9
27 1/1 assign qs = d;
Tests: T2 T3 T9
28 unreachable assign q = wd;
29 unreachable assign qe = we;
30 1/1 assign qre = re;
Tests: T1 T3 T9
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_esc_cnt
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
CONT_ASSIGN | 28 | 0 | 0 | |
CONT_ASSIGN | 29 | 0 | 0 | |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
25 // between qs and ds
26 1/1 assign ds = d;
Tests: T1 T2 T3
27 1/1 assign qs = d;
Tests: T1 T2 T3
28 unreachable assign q = wd;
29 unreachable assign qe = we;
30 1/1 assign qre = re;
Tests: T3 T9 T10
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_state
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
CONT_ASSIGN | 28 | 0 | 0 | |
CONT_ASSIGN | 29 | 0 | 0 | |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
25 // between qs and ds
26 1/1 assign ds = d;
Tests: T1 T2 T3
27 1/1 assign qs = d;
Tests: T1 T2 T3
28 unreachable assign q = wd;
29 unreachable assign qe = we;
30 1/1 assign qre = re;
Tests: T3 T9 T10
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_accum_cnt
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
CONT_ASSIGN | 28 | 0 | 0 | |
CONT_ASSIGN | 29 | 0 | 0 | |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
25 // between qs and ds
26 1/1 assign ds = d;
Tests: T2 T3 T9
27 1/1 assign qs = d;
Tests: T2 T3 T9
28 unreachable assign q = wd;
29 unreachable assign qe = we;
30 1/1 assign qre = re;
Tests: T1 T3 T9
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_esc_cnt
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
CONT_ASSIGN | 28 | 0 | 0 | |
CONT_ASSIGN | 29 | 0 | 0 | |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
25 // between qs and ds
26 1/1 assign ds = d;
Tests: T1 T2 T3
27 1/1 assign qs = d;
Tests: T1 T2 T3
28 unreachable assign q = wd;
29 unreachable assign qe = we;
30 1/1 assign qre = re;
Tests: T3 T9 T10
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_state
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
CONT_ASSIGN | 28 | 0 | 0 | |
CONT_ASSIGN | 29 | 0 | 0 | |
CONT_ASSIGN | 30 | 1 | 1 | 100.00 |
25 // between qs and ds
26 1/1 assign ds = d;
Tests: T1 T2 T3
27 1/1 assign qs = d;
Tests: T1 T2 T3
28 unreachable assign q = wd;
29 unreachable assign qe = we;
30 1/1 assign qre = re;
Tests: T3 T9 T10