Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T1 T2 T3 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T1 T2 T3 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T1 T2 T3 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T10 T13 T12 
159        1/1                    state_d = TimeoutSt;
           Tests:       T10 T13 T12 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T10 T13 T12 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T10 T13 T12 
172        1/1                    state_d    = Phase0St;
           Tests:       T22 T24 T25 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T22 T24 T25 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T22 T24 T25 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T22 T24 T25 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T10 T13 T12 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T10 T13 T12 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T10 T13 T12 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T13 T12 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T3 T9 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T1 T3 T9 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T1 T3 T9 
190        1/1                  esc_state_o = Phase0;
           Tests:       T1 T3 T9 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T1 T3 T9 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T1 T3 T9 
194        1/1                    state_d = IdleSt;
           Tests:       T24 T26 T27 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T24 T26 T27 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T24 T26 T27 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T3 T9 
198        1/1                    state_d = Phase1St;
           Tests:       T1 T3 T9 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T3 T9 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T3 T9 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T3 T9 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T1 T3 T9 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T1 T3 T9 
207        1/1                  esc_state_o = Phase1;
           Tests:       T1 T3 T9 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T1 T3 T9 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T1 T3 T9 
211        1/1                    state_d = IdleSt;
           Tests:       T28 T29 T30 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T28 T29 T30 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T28 T29 T30 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T3 T9 
215        1/1                    state_d = Phase2St;
           Tests:       T1 T3 T9 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T3 T9 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T3 T9 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T3 T9 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T1 T3 T9 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T1 T3 T9 
224        1/1                  esc_state_o = Phase2;
           Tests:       T1 T3 T9 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T1 T3 T9 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T1 T3 T9 
229        1/1                    state_d = IdleSt;
           Tests:       T31 T28 T26 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T31 T28 T26 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T31 T28 T26 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T3 T9 
233        1/1                    state_d = Phase3St;
           Tests:       T1 T3 T9 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T3 T9 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T3 T9 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T1 T3 T9 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T1 T3 T9 
241        1/1                  esc_state_o = Phase3;
           Tests:       T1 T3 T9 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T1 T3 T9 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T1 T3 T9 
245        1/1                    state_d = IdleSt;
           Tests:       T3 T28 T32 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T28 T32 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T3 T28 T32 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T3 T9 
249        1/1                    state_d = TerminalSt;
           Tests:       T1 T3 T9 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T3 T9 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T1 T3 T9 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T3 T9 
259        1/1                  esc_state_o = Terminal;
           Tests:       T1 T3 T9 
260        1/1                  if (clr_i) begin
           Tests:       T1 T3 T9 
261        1/1                    state_d = IdleSt;
           Tests:       T3 T9 T10 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T4 T7 T8 
269        1/1                  fsm_error = 1'b1;
           Tests:       T4 T7 T8 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T4 T7 T8 
285        1/1                fsm_error = 1'b1;
           Tests:       T4 T7 T8 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T33,T34
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T9,T10,T14
1	0	1	Covered	T1,T3,T23
1	1	0	Covered	T10,T13,T12
1	1	1	Covered	T10,T13,T12

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T10,T13,T12
0	1	Covered	T22,T25,T35
1	0	Covered	T22,T24,T36

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T13,T12
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T22,T24,T36

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T12
1	0	Not Covered
1	1	Covered	T22,T25,T35

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T10,T12
1	Covered	T1,T3,T9

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T9
1	Covered	T10,T22,T37

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T9
1	Covered	T3,T12,T38

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T9
1	Covered	T3,T10,T12

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T4,T7,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T3,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T3,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T3,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T3,T10

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T7,T8
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T9
Phase1St	198	Covered	T1,T3,T9
Phase2St	215	Covered	T1,T3,T9
Phase3St	233	Covered	T1,T3,T9
TerminalSt	249	Covered	T1,T3,T9
TimeoutSt	159	Covered	T10,T13,T12

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T4,T7,T8
IdleSt->Phase0St	152	Covered	T1,T3,T9
IdleSt->TimeoutSt	159	Covered	T10,T13,T12
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T24,T36,T39
Phase0St->Phase1St	198	Covered	T1,T3,T9
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T28,T29,T30
Phase1St->Phase2St	215	Covered	T1,T3,T9
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T36,T31,T28
Phase2St->Phase3St	233	Covered	T1,T3,T9
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T3,T28,T32
Phase3St->TerminalSt	249	Covered	T1,T3,T9
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T3,T9,T10
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T10,T13,T12
TimeoutSt->Phase0St	172	Covered	T22,T24,T25

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T13,T12
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T22,T24,T25
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T10,T13,T12
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T10,T13,T12
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T24,T26,T27
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T9
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T10,T12
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T28,T29,T30
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T9
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T10,T12
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T31,T28,T26
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T9
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T10,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T3,T28,T32
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T9
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T10,T12
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T9,T10
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T9
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T8
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T8

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T8
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	792	0	0
CheckAccumTrig0_A	2147483647	2128	0	0
CheckAccumTrig1_A	2147483647	99	0	0
CheckClr_A	2147483647	1043	0	0
CheckEn_A	2147483647	856773914	0	0
CheckPhase0_A	2147483647	2342	0	0
CheckPhase1_A	2147483647	2296	0	0
CheckPhase2_A	2147483647	2236	0	0
CheckPhase3_A	2147483647	2190	0	0
CheckTimeout0_A	2147483647	4659	0	0
CheckTimeoutSt1_A	2147483647	426179	0	0
CheckTimeoutSt2_A	2147483647	4351	0	0
CheckTimeoutStTrig_A	2147483647	196	0	0
ErrorStAllEscAsserted_A	2147483647	4502	0	0
ErrorStIsTerminal_A	2147483647	3662	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	792	0	0
T4	139368	228	0	0
T5	63684	0	0	0
T7	0	210	0	0
T8	0	101	0	0
T11	117992	0	0	0
T22	99712	0	0	0
T23	16464	0	0	0
T37	45616	0	0	0
T40	0	149	0	0
T41	0	104	0	0
T42	83784	0	0	0
T43	186508	0	0	0
T44	60520	0	0	0
T45	91640	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2128	0	0
T1	3625	1	0	0
T2	17504	0	0	0
T3	10064	5	0	0
T4	139368	0	0	0
T9	93736	3	0	0
T10	85544	6	0	0
T11	0	1	0	0
T12	17020	2	0	0
T13	179424	0	0	0
T14	104168	0	0	0
T15	0	1	0	0
T22	99712	4	0	0
T23	12348	1	0	0
T24	0	2	0	0
T37	0	2	0	0
T42	62838	0	0	0
T43	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	3	0	0
T49	0	3	0	0
T50	0	3	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	3	0	0
T54	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	99	0	0
T6	17700	0	0	0
T7	46195	0	0	0
T8	17366	0	0	0
T22	24928	2	0	0
T24	14854	1	0	0
T25	22156	0	0	0
T26	0	1	0	0
T36	0	1	0	0
T38	19440	0	0	0
T46	3965	0	0	0
T47	4083	0	0	0
T48	11169	0	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	25795	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	6	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	2	0	0
T72	14932	0	0	0
T73	67665	0	0	0
T74	89372	0	0	0
T75	34761	0	0	0
T76	122573	0	0	0
T77	17544	0	0	0
T78	1721	0	0	0
T79	113162	0	0	0
T80	42026	0	0	0
T81	110592	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1043	0	0
T3	10064	4	0	0
T4	139368	0	0	0
T9	93736	2	0	0
T10	85544	2	0	0
T12	17020	1	0	0
T13	179424	0	0	0
T14	104168	0	0	0
T22	99712	3	0	0
T23	16464	0	0	0
T24	0	2	0	0
T28	0	5	0	0
T31	0	1	0	0
T35	0	1	0	0
T36	0	4	0	0
T38	0	1	0	0
T42	83784	0	0	0
T43	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T53	0	1	0	0
T57	0	6	0	0
T82	0	2	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	2	0	0
T86	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	856773914	0	0
T1	14500	8644	0	0
T2	70016	8705	0	0
T3	10064	4639	0	0
T4	848	588	0	0
T9	93736	69168	0	0
T10	85544	25561	0	0
T12	17020	7462	0	0
T13	179424	136392	0	0
T14	104168	78408	0	0
T22	99712	14998	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2342	0	0
T1	3625	1	0	0
T2	17504	0	0	0
T3	10064	5	0	0
T4	139368	0	0	0
T9	93736	3	0	0
T10	85544	6	0	0
T11	0	1	0	0
T12	17020	2	0	0
T13	179424	0	0	0
T14	104168	0	0	0
T15	0	1	0	0
T22	99712	8	0	0
T23	12348	1	0	0
T24	0	2	0	0
T25	0	1	0	0
T35	0	2	0	0
T37	0	2	0	0
T42	62838	0	0	0
T43	0	1	0	0
T46	0	1	0	0
T48	0	3	0	0
T49	0	3	0	0
T50	0	3	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2296	0	0
T1	3625	1	0	0
T2	17504	0	0	0
T3	10064	5	0	0
T4	139368	0	0	0
T9	93736	3	0	0
T10	85544	6	0	0
T11	0	1	0	0
T12	17020	2	0	0
T13	179424	0	0	0
T14	104168	0	0	0
T15	0	1	0	0
T22	99712	8	0	0
T23	12348	1	0	0
T24	0	2	0	0
T25	0	1	0	0
T35	0	2	0	0
T37	0	2	0	0
T42	62838	0	0	0
T43	0	1	0	0
T46	0	1	0	0
T48	0	3	0	0
T49	0	3	0	0
T50	0	3	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2236	0	0
T1	3625	1	0	0
T2	17504	0	0	0
T3	10064	5	0	0
T4	139368	0	0	0
T9	93736	3	0	0
T10	85544	6	0	0
T11	0	1	0	0
T12	17020	2	0	0
T13	179424	0	0	0
T14	104168	0	0	0
T15	0	1	0	0
T22	99712	8	0	0
T23	12348	1	0	0
T24	0	2	0	0
T25	0	1	0	0
T35	0	2	0	0
T37	0	2	0	0
T42	62838	0	0	0
T43	0	1	0	0
T46	0	1	0	0
T48	0	3	0	0
T49	0	3	0	0
T50	0	3	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2190	0	0
T1	3625	1	0	0
T2	17504	0	0	0
T3	10064	4	0	0
T4	139368	0	0	0
T9	93736	3	0	0
T10	85544	6	0	0
T11	0	1	0	0
T12	17020	2	0	0
T13	179424	0	0	0
T14	104168	0	0	0
T15	0	1	0	0
T22	99712	8	0	0
T23	12348	1	0	0
T24	0	2	0	0
T25	0	1	0	0
T35	0	2	0	0
T37	0	2	0	0
T42	62838	0	0	0
T43	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	3	0	0
T49	0	3	0	0
T50	0	3	0	0
T51	0	1	0	0
T52	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4659	0	0
T4	104526	0	0	0
T5	47763	0	0	0
T10	21386	1	0	0
T11	117992	0	0	0
T12	12765	2	0	0
T13	89712	5	0	0
T14	26042	0	0	0
T22	74784	7	0	0
T23	12348	0	0	0
T24	14854	2	0	0
T25	22156	8	0	0
T31	0	1	0	0
T35	0	20	0	0
T36	0	1	0	0
T37	11404	1	0	0
T42	83784	17	0	0
T43	186508	0	0	0
T44	45390	0	0	0
T45	45820	0	0	0
T53	0	1	0	0
T55	0	2	0	0
T87	0	6	0	0
T88	0	2	0	0
T89	0	25	0	0
T90	0	2	0	0
T91	0	2	0	0
T92	0	14	0	0
T93	0	2	0	0
T94	8163	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	426179	0	0
T4	104526	0	0	0
T5	47763	0	0	0
T10	21386	43	0	0
T11	117992	0	0	0
T12	12765	53	0	0
T13	89712	603	0	0
T14	26042	0	0	0
T22	74784	599	0	0
T23	12348	0	0	0
T24	14854	136	0	0
T25	22156	1027	0	0
T31	0	122	0	0
T35	0	3299	0	0
T36	0	6	0	0
T37	11404	186	0	0
T42	83784	1375	0	0
T43	186508	0	0	0
T44	45390	0	0	0
T45	45820	0	0	0
T53	0	11	0	0
T55	0	173	0	0
T87	0	459	0	0
T88	0	556	0	0
T89	0	6142	0	0
T90	0	1562	0	0
T91	0	419	0	0
T92	0	2647	0	0
T93	0	143	0	0
T94	8163	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4351	0	0
T4	104526	0	0	0
T5	47763	0	0	0
T10	21386	1	0	0
T11	117992	0	0	0
T12	12765	2	0	0
T13	89712	5	0	0
T14	26042	0	0	0
T22	74784	3	0	0
T23	12348	0	0	0
T24	14854	1	0	0
T25	22156	7	0	0
T28	0	3	0	0
T35	0	18	0	0
T37	11404	1	0	0
T42	83784	17	0	0
T43	186508	0	0	0
T44	45390	0	0	0
T45	45820	0	0	0
T53	0	1	0	0
T56	0	1	0	0
T87	0	6	0	0
T88	0	2	0	0
T89	0	25	0	0
T91	0	1	0	0
T92	0	14	0	0
T94	8163	0	0	0
T95	0	125	0	0
T96	0	1	0	0
T97	0	2	0	0
T98	0	4	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	196	0	0
T5	15921	0	0	0
T6	17700	0	0	0
T7	46195	0	0	0
T8	17366	0	0	0
T11	29498	0	0	0
T22	24928	2	0	0
T23	4116	0	0	0
T25	22156	1	0	0
T26	0	2	0	0
T28	0	1	0	0
T32	0	3	0	0
T35	0	2	0	0
T37	11404	0	0	0
T38	19440	0	0	0
T42	20946	0	0	0
T43	46627	0	0	0
T44	15130	0	0	0
T45	22910	0	0	0
T46	3965	0	0	0
T47	4083	0	0	0
T48	11169	0	0	0
T55	0	1	0	0
T60	0	1	0	0
T63	0	1	0	0
T67	0	1	0	0
T68	0	3	0	0
T72	14932	0	0	0
T87	34934	0	0	0
T90	0	1	0	0
T91	27862	1	0	0
T93	0	3	0	0
T94	8163	0	0	0
T97	0	1	0	0
T99	0	2	0	0
T100	0	1	0	0
T101	0	1	0	0
T102	0	1	0	0
T103	0	1	0	0
T104	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4502	0	0
T4	139368	1316	0	0
T5	63684	0	0	0
T7	0	1327	0	0
T8	0	631	0	0
T11	117992	0	0	0
T22	99712	0	0	0
T23	16464	0	0	0
T37	45616	0	0	0
T40	0	607	0	0
T41	0	621	0	0
T42	83784	0	0	0
T43	186508	0	0	0
T44	60520	0	0	0
T45	91640	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3662	0	0
T4	139368	1076	0	0
T5	63684	0	0	0
T7	0	1087	0	0
T8	0	511	0	0
T11	117992	0	0	0
T22	99712	0	0	0
T23	16464	0	0	0
T37	45616	0	0	0
T40	0	487	0	0
T41	0	501	0	0
T42	83784	0	0	0
T43	186508	0	0	0
T44	60520	0	0	0
T45	91640	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	14500	14252	0	0
T2	70016	69524	0	0
T3	10064	9684	0	0
T4	336	80	0	0
T9	93736	93496	0	0
T10	85544	85208	0	0
T12	17020	16684	0	0
T13	179424	179128	0	0
T14	104168	103772	0	0
T22	99712	99352	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	14500	14252	0	0
T2	70016	69524	0	0
T3	10064	9684	0	0
T4	139368	37704	0	0
T9	93736	93496	0	0
T10	85544	85208	0	0
T12	17020	16684	0	0
T13	179424	179128	0	0
T14	104168	103772	0	0
T22	99712	99352	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T1 T3 T9 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T1 T3 T9 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T1 T3 T9 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T42 T24 T25 
159        1/1                    state_d = TimeoutSt;
           Tests:       T42 T24 T25 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T42 T24 T25 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T42 T24 T25 
172        1/1                    state_d    = Phase0St;
           Tests:       T24 T25 T36 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T24 T25 T36 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T24 T25 T36 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T24 T25 T36 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T42 T24 T25 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T42 T24 T25 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T42 T24 T87 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T42 T24 T87 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T3 T9 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T1 T3 T9 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T1 T3 T9 
190        1/1                  esc_state_o = Phase0;
           Tests:       T1 T3 T9 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T1 T3 T9 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T1 T3 T9 
194        1/1                    state_d = IdleSt;
           Tests:       T24 T26 T27 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T24 T26 T27 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T24 T26 T27 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T3 T9 
198        1/1                    state_d = Phase1St;
           Tests:       T1 T3 T9 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T3 T9 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T3 T9 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T3 T9 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T1 T3 T9 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T1 T3 T9 
207        1/1                  esc_state_o = Phase1;
           Tests:       T1 T3 T9 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T1 T3 T9 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T1 T3 T9 
211        1/1                    state_d = IdleSt;
           Tests:       T28 T29 T61 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T28 T29 T61 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T28 T29 T61 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T3 T9 
215        1/1                    state_d = Phase2St;
           Tests:       T1 T3 T9 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T3 T9 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T3 T9 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T3 T9 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T1 T3 T9 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T1 T3 T9 
224        1/1                  esc_state_o = Phase2;
           Tests:       T1 T3 T9 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T1 T3 T9 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T1 T3 T9 
229        1/1                    state_d = IdleSt;
           Tests:       T28 T105 T106 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T28 T105 T106 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T28 T105 T106 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T3 T9 
233        1/1                    state_d = Phase3St;
           Tests:       T1 T3 T9 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T3 T9 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T3 T9 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T1 T3 T9 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T1 T3 T9 
241        1/1                  esc_state_o = Phase3;
           Tests:       T1 T3 T9 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T1 T3 T9 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T1 T3 T9 
245        1/1                    state_d = IdleSt;
           Tests:       T3 T32 T63 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T32 T63 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T3 T32 T63 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T3 T9 
249        1/1                    state_d = TerminalSt;
           Tests:       T1 T9 T10 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T9 T10 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T1 T9 T10 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T9 T10 
259        1/1                  esc_state_o = Terminal;
           Tests:       T1 T9 T10 
260        1/1                  if (clr_i) begin
           Tests:       T1 T9 T10 
261        1/1                    state_d = IdleSt;
           Tests:       T9 T10 T43 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T4 T7 T8 
269        1/1                  fsm_error = 1'b1;
           Tests:       T4 T7 T8 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T4 T7 T8 
285        1/1                fsm_error = 1'b1;
           Tests:       T4 T7 T8 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T3,T9
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T9

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T9

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T14,T12,T22
1	0	1	Covered	T1,T44,T45
1	1	0	Covered	T10,T13,T37
1	1	1	Covered	T42,T24,T25

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T42,T24,T25
0	1	Covered	T25,T55,T93
1	0	Covered	T24,T36,T55

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T42,T24,T25
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T24,T36,T55

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T42,T24,T25
1	0	Not Covered
1	1	Covered	T25,T55,T93

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T12,T22,T11
1	Covered	T1,T3,T9

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T9
1	Covered	T36,T82,T107

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T9
1	Covered	T12,T38,T36

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T9
1	Covered	T22,T11,T24

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T4,T7,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T3,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T9,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T9,T24

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T1,T3,T10

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T7,T8
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T9
Phase1St	198	Covered	T1,T3,T9
Phase2St	215	Covered	T1,T3,T9
Phase3St	233	Covered	T1,T3,T9
TerminalSt	249	Covered	T1,T9,T10
TimeoutSt	159	Covered	T42,T24,T25

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T4,T7,T8
IdleSt->Phase0St	152	Covered	T1,T3,T9
IdleSt->TimeoutSt	159	Covered	T42,T24,T25
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T24,T36,T26
Phase0St->Phase1St	198	Covered	T1,T3,T9
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T28,T29,T61
Phase1St->Phase2St	215	Covered	T1,T3,T9
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T36,T28,T105
Phase2St->Phase3St	233	Covered	T1,T3,T9
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T3,T32,T63
Phase3St->TerminalSt	249	Covered	T1,T9,T10
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T9,T10,T43
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T42,T24,T87
TimeoutSt->Phase0St	172	Covered	T24,T25,T36

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T9
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T42,T24,T25
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T24,T25,T36
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T42,T24,T25
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T42,T24,T87
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T24,T26,T27
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T9
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T10,T12
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T28,T29,T61
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T9
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T10,T12
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T28,T105,T106
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T9
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T10,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T3,T32,T63
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T9,T10
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T10,T12
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T9,T10,T43
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T9,T10
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T8
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T8

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T8
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	574695525	199	0	0
CheckAccumTrig0_A	574695525	800	0	0
CheckAccumTrig1_A	574695525	44	0	0
CheckClr_A	574695525	426	0	0
CheckEn_A	574561090	210061375	0	0
CheckPhase0_A	574695525	862	0	0
CheckPhase1_A	574695525	841	0	0
CheckPhase2_A	574695525	815	0	0
CheckPhase3_A	574695525	802	0	0
CheckTimeout0_A	574695525	1345	0	0
CheckTimeoutSt1_A	574695525	129921	0	0
CheckTimeoutSt2_A	574695525	1250	0	0
CheckTimeoutStTrig_A	574695525	50	0	0
ErrorStAllEscAsserted_A	574695525	1091	0	0
ErrorStIsTerminal_A	574695525	881	0	0
EscStateOut_A	574560034	574493581	0	0
u_state_regs_A	574695525	574539856	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	199	0	0
T4	34842	51	0	0
T5	15921	0	0	0
T7	0	60	0	0
T8	0	22	0	0
T11	29498	0	0	0
T22	24928	0	0	0
T23	4116	0	0	0
T37	11404	0	0	0
T40	0	37	0	0
T41	0	29	0	0
T42	20946	0	0	0
T43	46627	0	0	0
T44	15130	0	0	0
T45	22910	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	800	0	0
T1	3625	1	0	0
T2	17504	0	0	0
T3	2516	1	0	0
T4	34842	0	0	0
T9	23434	3	0	0
T10	21386	1	0	0
T11	0	1	0	0
T12	4255	1	0	0
T13	44856	0	0	0
T14	26042	0	0	0
T22	24928	1	0	0
T24	0	2	0	0
T43	0	1	0	0
T47	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	44	0	0
T6	17700	0	0	0
T7	46195	0	0	0
T8	17366	0	0	0
T24	14854	1	0	0
T25	22156	0	0	0
T26	0	1	0	0
T36	0	1	0	0
T38	19440	0	0	0
T46	3965	0	0	0
T47	4083	0	0	0
T48	11169	0	0	0
T55	0	1	0	0
T57	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T66	0	4	0	0
T72	14932	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	426	0	0
T3	2516	1	0	0
T4	34842	0	0	0
T9	23434	2	0	0
T10	21386	1	0	0
T12	4255	0	0	0
T13	44856	0	0	0
T14	26042	0	0	0
T22	24928	0	0	0
T23	4116	0	0	0
T24	0	2	0	0
T36	0	4	0	0
T38	0	1	0	0
T42	20946	0	0	0
T43	0	1	0	0
T47	0	1	0	0
T82	0	2	0	0
T83	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574561090	210061375	0	0
T1	3625	2149	0	0
T2	17504	2157	0	0
T3	2516	1351	0	0
T4	212	147	0	0
T9	23434	643	0	0
T10	21386	18189	0	0
T12	4255	582	0	0
T13	44856	44781	0	0
T14	26042	582	0	0
T22	24928	3366	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	862	0	0
T1	3625	1	0	0
T2	17504	0	0	0
T3	2516	1	0	0
T4	34842	0	0	0
T9	23434	3	0	0
T10	21386	1	0	0
T11	0	1	0	0
T12	4255	1	0	0
T13	44856	0	0	0
T14	26042	0	0	0
T22	24928	1	0	0
T24	0	2	0	0
T25	0	1	0	0
T43	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	841	0	0
T1	3625	1	0	0
T2	17504	0	0	0
T3	2516	1	0	0
T4	34842	0	0	0
T9	23434	3	0	0
T10	21386	1	0	0
T11	0	1	0	0
T12	4255	1	0	0
T13	44856	0	0	0
T14	26042	0	0	0
T22	24928	1	0	0
T24	0	2	0	0
T25	0	1	0	0
T43	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	815	0	0
T1	3625	1	0	0
T2	17504	0	0	0
T3	2516	1	0	0
T4	34842	0	0	0
T9	23434	3	0	0
T10	21386	1	0	0
T11	0	1	0	0
T12	4255	1	0	0
T13	44856	0	0	0
T14	26042	0	0	0
T22	24928	1	0	0
T24	0	2	0	0
T25	0	1	0	0
T43	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	802	0	0
T1	3625	1	0	0
T2	17504	0	0	0
T3	2516	0	0	0
T4	34842	0	0	0
T9	23434	3	0	0
T10	21386	1	0	0
T11	0	1	0	0
T12	4255	1	0	0
T13	44856	0	0	0
T14	26042	0	0	0
T22	24928	1	0	0
T24	0	2	0	0
T25	0	1	0	0
T43	0	1	0	0
T47	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	1345	0	0
T5	15921	0	0	0
T11	29498	0	0	0
T24	14854	2	0	0
T25	22156	1	0	0
T36	0	1	0	0
T37	11404	0	0	0
T42	20946	6	0	0
T43	46627	0	0	0
T44	15130	0	0	0
T45	22910	0	0	0
T55	0	2	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	10	0	0
T92	0	8	0	0
T93	0	1	0	0
T94	8163	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	129921	0	0
T5	15921	0	0	0
T11	29498	0	0	0
T24	14854	136	0	0
T25	22156	53	0	0
T36	0	6	0	0
T37	11404	0	0	0
T42	20946	492	0	0
T43	46627	0	0	0
T44	15130	0	0	0
T45	22910	0	0	0
T55	0	173	0	0
T87	0	71	0	0
T88	0	278	0	0
T89	0	2149	0	0
T92	0	1588	0	0
T93	0	74	0	0
T94	8163	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	1250	0	0
T5	15921	0	0	0
T11	29498	0	0	0
T24	14854	1	0	0
T25	22156	0	0	0
T28	0	3	0	0
T37	11404	0	0	0
T42	20946	6	0	0
T43	46627	0	0	0
T44	15130	0	0	0
T45	22910	0	0	0
T56	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	10	0	0
T92	0	8	0	0
T94	8163	0	0	0
T95	0	41	0	0
T98	0	4	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	50	0	0
T6	17700	0	0	0
T7	46195	0	0	0
T8	17366	0	0	0
T25	22156	1	0	0
T26	0	1	0	0
T28	0	1	0	0
T32	0	1	0	0
T38	19440	0	0	0
T46	3965	0	0	0
T47	4083	0	0	0
T48	11169	0	0	0
T55	0	1	0	0
T63	0	1	0	0
T72	14932	0	0	0
T87	34934	0	0	0
T93	0	1	0	0
T99	0	1	0	0
T100	0	1	0	0
T101	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	1091	0	0
T4	34842	318	0	0
T5	15921	0	0	0
T7	0	329	0	0
T8	0	153	0	0
T11	29498	0	0	0
T22	24928	0	0	0
T23	4116	0	0	0
T37	11404	0	0	0
T40	0	142	0	0
T41	0	149	0	0
T42	20946	0	0	0
T43	46627	0	0	0
T44	15130	0	0	0
T45	22910	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	881	0	0
T4	34842	258	0	0
T5	15921	0	0	0
T7	0	269	0	0
T8	0	123	0	0
T11	29498	0	0	0
T22	24928	0	0	0
T23	4116	0	0	0
T37	11404	0	0	0
T40	0	112	0	0
T41	0	119	0	0
T42	20946	0	0	0
T43	46627	0	0	0
T44	15130	0	0	0
T45	22910	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574560034	574493581	0	0
T1	3625	3563	0	0
T2	17504	17381	0	0
T3	2516	2421	0	0
T4	84	20	0	0
T9	23434	23374	0	0
T10	21386	21302	0	0
T12	4255	4171	0	0
T13	44856	44782	0	0
T14	26042	25943	0	0
T22	24928	24838	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	574539856	0	0
T1	3625	3563	0	0
T2	17504	17381	0	0
T3	2516	2421	0	0
T4	34842	9426	0	0
T9	23434	23374	0	0
T10	21386	21302	0	0
T12	4255	4171	0	0
T13	44856	44782	0	0
T14	26042	25943	0	0
T22	24928	24838	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T3 T10 T12 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T3 T10 T12 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T3 T10 T12 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T10 T12 T22 
159        1/1                    state_d = TimeoutSt;
           Tests:       T10 T12 T22 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T10 T12 T22 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T10 T12 T22 
172        1/1                    state_d    = Phase0St;
           Tests:       T22 T91 T93 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T22 T91 T93 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T22 T91 T93 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T22 T91 T93 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T10 T12 T22 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T10 T12 T22 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T10 T12 T22 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T12 T22 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T3 T10 T12 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T3 T10 T12 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T3 T10 T12 
190        1/1                  esc_state_o = Phase0;
           Tests:       T3 T10 T12 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T3 T10 T12 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T3 T10 T12 
194        1/1                    state_d = IdleSt;
           Tests:       T108 T62 T66 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T108 T62 T66 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T108 T62 T66 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T3 T10 T12 
198        1/1                    state_d = Phase1St;
           Tests:       T3 T10 T12 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T10 T12 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T3 T10 T12 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T3 T10 T12 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T3 T10 T12 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T3 T10 T12 
207        1/1                  esc_state_o = Phase1;
           Tests:       T3 T10 T12 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T3 T10 T12 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T3 T10 T12 
211        1/1                    state_d = IdleSt;
           Tests:       T109 T110 T111 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T109 T110 T111 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T109 T110 T111 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T3 T10 T12 
215        1/1                    state_d = Phase2St;
           Tests:       T3 T10 T12 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T10 T12 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T3 T10 T12 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T3 T10 T12 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T3 T10 T12 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T3 T10 T12 
224        1/1                  esc_state_o = Phase2;
           Tests:       T3 T10 T12 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T3 T10 T12 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T3 T10 T12 
229        1/1                    state_d = IdleSt;
           Tests:       T31 T26 T112 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T31 T26 T112 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T31 T26 T112 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T3 T10 T12 
233        1/1                    state_d = Phase3St;
           Tests:       T3 T10 T12 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T10 T12 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T3 T10 T12 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T3 T10 T12 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T3 T10 T12 
241        1/1                  esc_state_o = Phase3;
           Tests:       T3 T10 T12 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T3 T10 T12 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T3 T10 T12 
245        1/1                    state_d = IdleSt;
           Tests:       T113 T114 T115 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T113 T114 T115 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T113 T114 T115 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T3 T10 T12 
249        1/1                    state_d = TerminalSt;
           Tests:       T3 T10 T12 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T10 T12 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T3 T10 T12 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T3 T10 T12 
259        1/1                  esc_state_o = Terminal;
           Tests:       T3 T10 T12 
260        1/1                  if (clr_i) begin
           Tests:       T3 T10 T12 
261        1/1                    state_d = IdleSt;
           Tests:       T3 T10 T12 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T4 T7 T8 
269        1/1                  fsm_error = 1'b1;
           Tests:       T4 T7 T8 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T4 T7 T8 
285        1/1                fsm_error = 1'b1;
           Tests:       T4 T7 T8 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T8
1	0	Covered	T3,T10,T12
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T10,T12

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T10,T12

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T12,T22
1	0	1	Covered	T72,T46,T36
1	1	0	Covered	T13,T22,T42
1	1	1	Covered	T10,T12,T22

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T10,T12,T22
0	1	Covered	T91,T93,T97
1	0	Covered	T22,T56,T39

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T10,T12,T22
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T22,T56,T39

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T22
1	0	Not Covered
1	1	Covered	T91,T93,T97

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T10,T12
1	Covered	T46,T49,T116

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T10,T12
1	Covered	T22,T15,T50

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T10,T12,T22
1	Covered	T3,T10,T37

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T10,T22
1	Covered	T10,T12,T22

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T4,T7,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T3,T10,T22

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T12,T22,T37

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T3,T12,T22

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T10,T12,T37

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T7,T8
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T3,T10,T12
Phase1St	198	Covered	T3,T10,T12
Phase2St	215	Covered	T3,T10,T12
Phase3St	233	Covered	T3,T10,T12
TerminalSt	249	Covered	T3,T10,T12
TimeoutSt	159	Covered	T10,T12,T22

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T4,T7,T8
IdleSt->Phase0St	152	Covered	T3,T10,T12
IdleSt->TimeoutSt	159	Covered	T10,T12,T22
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T39,T57,T108
Phase0St->Phase1St	198	Covered	T3,T10,T12
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T109,T110,T111
Phase1St->Phase2St	215	Covered	T3,T10,T12
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T31,T26,T112
Phase2St->Phase3St	233	Covered	T3,T10,T12
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T113,T114,T115
Phase3St->TerminalSt	249	Covered	T3,T10,T12
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T3,T10,T12
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T10,T12,T22
TimeoutSt->Phase0St	172	Covered	T22,T91,T93

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T10,T12
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T12,T22
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T22,T91,T93
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T10,T12,T22
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T10,T12,T22
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T108,T62,T66
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T10,T12
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T10,T12
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T109,T110,T111
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T10,T12
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T10,T12
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T31,T26,T112
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T10,T12
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T10,T12,T22
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T113,T114,T115
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T10,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T10,T12
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T10,T12
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T10,T12
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T8
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T8

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T8
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	574695525	183	0	0
CheckAccumTrig0_A	574695525	429	0	0
CheckAccumTrig1_A	574695525	21	0	0
CheckClr_A	574695525	192	0	0
CheckEn_A	574561090	220780718	0	0
CheckPhase0_A	574695525	483	0	0
CheckPhase1_A	574695525	472	0	0
CheckPhase2_A	574695525	461	0	0
CheckPhase3_A	574695525	457	0	0
CheckTimeout0_A	574695525	1197	0	0
CheckTimeoutSt1_A	574695525	101088	0	0
CheckTimeoutSt2_A	574695525	1123	0	0
CheckTimeoutStTrig_A	574695525	48	0	0
ErrorStAllEscAsserted_A	574695525	1102	0	0
ErrorStIsTerminal_A	574695525	892	0	0
EscStateOut_A	574560034	574493581	0	0
u_state_regs_A	574695525	574539856	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	183	0	0
T4	34842	42	0	0
T5	15921	0	0	0
T7	0	50	0	0
T8	0	21	0	0
T11	29498	0	0	0
T22	24928	0	0	0
T23	4116	0	0	0
T37	11404	0	0	0
T40	0	45	0	0
T41	0	25	0	0
T42	20946	0	0	0
T43	46627	0	0	0
T44	15130	0	0	0
T45	22910	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	429	0	0
T3	2516	1	0	0
T4	34842	0	0	0
T9	23434	0	0	0
T10	21386	2	0	0
T12	4255	1	0	0
T13	44856	0	0	0
T14	26042	0	0	0
T15	0	1	0	0
T22	24928	1	0	0
T23	4116	0	0	0
T37	0	1	0	0
T42	20946	0	0	0
T46	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	21	0	0
T5	15921	0	0	0
T11	29498	0	0	0
T22	24928	2	0	0
T23	4116	0	0	0
T37	11404	0	0	0
T39	0	1	0	0
T42	20946	0	0	0
T43	46627	0	0	0
T44	15130	0	0	0
T45	22910	0	0	0
T56	0	1	0	0
T94	8163	0	0	0
T109	0	1	0	0
T110	0	1	0	0
T117	0	1	0	0
T118	0	1	0	0
T119	0	1	0	0
T120	0	1	0	0
T121	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	192	0	0
T3	2516	1	0	0
T4	34842	0	0	0
T9	23434	0	0	0
T10	21386	1	0	0
T12	4255	1	0	0
T13	44856	0	0	0
T14	26042	0	0	0
T22	24928	2	0	0
T23	4116	0	0	0
T31	0	1	0	0
T42	20946	0	0	0
T48	0	1	0	0
T85	0	1	0	0
T91	0	1	0	0
T97	0	1	0	0
T122	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574561090	220780718	0	0
T1	3625	2167	0	0
T2	17504	2184	0	0
T3	2516	1351	0	0
T4	212	147	0	0
T9	23434	23373	0	0
T10	21386	1832	0	0
T12	4255	590	0	0
T13	44856	44781	0	0
T14	26042	25942	0	0
T22	24928	3374	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	483	0	0
T3	2516	1	0	0
T4	34842	0	0	0
T9	23434	0	0	0
T10	21386	2	0	0
T12	4255	1	0	0
T13	44856	0	0	0
T14	26042	0	0	0
T15	0	1	0	0
T22	24928	3	0	0
T23	4116	0	0	0
T37	0	1	0	0
T42	20946	0	0	0
T46	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	472	0	0
T3	2516	1	0	0
T4	34842	0	0	0
T9	23434	0	0	0
T10	21386	2	0	0
T12	4255	1	0	0
T13	44856	0	0	0
T14	26042	0	0	0
T15	0	1	0	0
T22	24928	3	0	0
T23	4116	0	0	0
T37	0	1	0	0
T42	20946	0	0	0
T46	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	461	0	0
T3	2516	1	0	0
T4	34842	0	0	0
T9	23434	0	0	0
T10	21386	2	0	0
T12	4255	1	0	0
T13	44856	0	0	0
T14	26042	0	0	0
T15	0	1	0	0
T22	24928	3	0	0
T23	4116	0	0	0
T37	0	1	0	0
T42	20946	0	0	0
T46	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	457	0	0
T3	2516	1	0	0
T4	34842	0	0	0
T9	23434	0	0	0
T10	21386	2	0	0
T12	4255	1	0	0
T13	44856	0	0	0
T14	26042	0	0	0
T15	0	1	0	0
T22	24928	3	0	0
T23	4116	0	0	0
T37	0	1	0	0
T42	20946	0	0	0
T46	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	1197	0	0
T4	34842	0	0	0
T10	21386	1	0	0
T11	29498	0	0	0
T12	4255	1	0	0
T13	44856	0	0	0
T14	26042	0	0	0
T22	24928	3	0	0
T23	4116	0	0	0
T25	0	2	0	0
T35	0	9	0	0
T42	20946	2	0	0
T43	46627	0	0	0
T87	0	1	0	0
T91	0	2	0	0
T92	0	2	0	0
T93	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	101088	0	0
T4	34842	0	0	0
T10	21386	43	0	0
T11	29498	0	0	0
T12	4255	25	0	0
T13	44856	0	0	0
T14	26042	0	0	0
T22	24928	18	0	0
T23	4116	0	0	0
T25	0	236	0	0
T35	0	1635	0	0
T42	20946	143	0	0
T43	46627	0	0	0
T87	0	109	0	0
T91	0	419	0	0
T92	0	300	0	0
T93	0	69	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	1123	0	0
T4	34842	0	0	0
T10	21386	1	0	0
T11	29498	0	0	0
T12	4255	1	0	0
T13	44856	0	0	0
T14	26042	0	0	0
T22	24928	1	0	0
T23	4116	0	0	0
T25	0	2	0	0
T35	0	9	0	0
T42	20946	2	0	0
T43	46627	0	0	0
T87	0	1	0	0
T91	0	1	0	0
T92	0	2	0	0
T97	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	48	0	0
T26	0	1	0	0
T32	0	1	0	0
T60	0	1	0	0
T62	0	1	0	0
T91	27862	1	0	0
T92	83375	0	0	0
T93	359909	1	0	0
T95	173173	0	0	0
T97	0	1	0	0
T99	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	177096	0	0	0
T126	130899	0	0	0
T127	4236	0	0	0
T128	102485	0	0	0
T129	4292	0	0	0
T130	107329	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	1102	0	0
T4	34842	295	0	0
T5	15921	0	0	0
T7	0	326	0	0
T8	0	159	0	0
T11	29498	0	0	0
T22	24928	0	0	0
T23	4116	0	0	0
T37	11404	0	0	0
T40	0	164	0	0
T41	0	158	0	0
T42	20946	0	0	0
T43	46627	0	0	0
T44	15130	0	0	0
T45	22910	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	892	0	0
T4	34842	235	0	0
T5	15921	0	0	0
T7	0	266	0	0
T8	0	129	0	0
T11	29498	0	0	0
T22	24928	0	0	0
T23	4116	0	0	0
T37	11404	0	0	0
T40	0	134	0	0
T41	0	128	0	0
T42	20946	0	0	0
T43	46627	0	0	0
T44	15130	0	0	0
T45	22910	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574560034	574493581	0	0
T1	3625	3563	0	0
T2	17504	17381	0	0
T3	2516	2421	0	0
T4	84	20	0	0
T9	23434	23374	0	0
T10	21386	21302	0	0
T12	4255	4171	0	0
T13	44856	44782	0	0
T14	26042	25943	0	0
T22	24928	24838	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	574539856	0	0
T1	3625	3563	0	0
T2	17504	17381	0	0
T3	2516	2421	0	0
T4	34842	9426	0	0
T9	23434	23374	0	0
T10	21386	21302	0	0
T12	4255	4171	0	0
T13	44856	44782	0	0
T14	26042	25943	0	0
T22	24928	24838	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T2 T3 T10 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T2 T3 T10 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T2 T3 T10 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T12 T22 T37 
159        1/1                    state_d = TimeoutSt;
           Tests:       T12 T22 T37 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T12 T22 T37 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T12 T22 T37 
172        1/1                    state_d    = Phase0St;
           Tests:       T22 T35 T90 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T22 T35 T90 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T22 T35 T90 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T22 T35 T90 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T12 T22 T37 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T12 T22 T37 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T12 T22 T37 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T22 T37 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T3 T10 T22 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T3 T10 T22 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T3 T10 T22 
190        1/1                  esc_state_o = Phase0;
           Tests:       T3 T10 T22 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T3 T10 T22 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T3 T10 T22 
194        1/1                    state_d = IdleSt;
           Tests:       T62 T66 T131 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T62 T66 T131 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T62 T66 T131 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T3 T10 T22 
198        1/1                    state_d = Phase1St;
           Tests:       T3 T10 T22 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T10 T22 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T3 T10 T22 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T3 T10 T22 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T3 T10 T22 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T3 T10 T22 
207        1/1                  esc_state_o = Phase1;
           Tests:       T3 T10 T22 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T3 T10 T22 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T3 T10 T22 
211        1/1                    state_d = IdleSt;
           Tests:       T30 T132 T133 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T30 T132 T133 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T30 T132 T133 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T3 T10 T22 
215        1/1                    state_d = Phase2St;
           Tests:       T3 T10 T22 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T10 T22 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T3 T10 T22 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T3 T10 T22 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T3 T10 T22 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T3 T10 T22 
224        1/1                  esc_state_o = Phase2;
           Tests:       T3 T10 T22 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T3 T10 T22 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T3 T10 T22 
229        1/1                    state_d = IdleSt;
           Tests:       T134 T135 T69 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T134 T135 T69 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T134 T135 T69 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T3 T10 T22 
233        1/1                    state_d = Phase3St;
           Tests:       T3 T10 T22 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T10 T22 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T3 T10 T22 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T3 T10 T22 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T3 T10 T22 
241        1/1                  esc_state_o = Phase3;
           Tests:       T3 T10 T22 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T3 T10 T22 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T3 T10 T22 
245        1/1                    state_d = IdleSt;
           Tests:       T28 T136 T137 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T28 T136 T137 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T28 T136 T137 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T3 T10 T22 
249        1/1                    state_d = TerminalSt;
           Tests:       T3 T10 T22 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T10 T22 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T3 T10 T22 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T3 T10 T22 
259        1/1                  esc_state_o = Terminal;
           Tests:       T3 T10 T22 
260        1/1                  if (clr_i) begin
           Tests:       T3 T10 T22 
261        1/1                    state_d = IdleSt;
           Tests:       T3 T22 T48 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T4 T7 T8 
269        1/1                  fsm_error = 1'b1;
           Tests:       T4 T7 T8 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T4 T7 T8 
285        1/1                fsm_error = 1'b1;
           Tests:       T4 T7 T8 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T8
1	0	Covered	T2,T3,T10
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T10

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T33
1	1	1	Covered	T2,T3,T10

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T9,T10,T12
1	0	1	Covered	T3,T23,T44
1	1	0	Covered	T13,T12,T22
1	1	1	Covered	T12,T22,T37

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T12,T22,T37
0	1	Covered	T22,T35,T90
1	0	Covered	T138,T58,T61

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T12,T22,T37
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T138,T58,T61

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T22,T37
1	0	Not Covered
1	1	Covered	T22,T35,T90

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T10,T37
1	Covered	T3,T22,T23

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T22,T23
1	Covered	T10,T37,T48

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T10,T22
1	Covered	T49,T50,T52

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T10,T22
1	Covered	T3,T35,T53

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T4,T7,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T10,T22,T23

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T3,T22,T23

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T3,T10,T22

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T3,T10,T22

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T7,T8
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T3,T10,T22
Phase1St	198	Covered	T3,T10,T22
Phase2St	215	Covered	T3,T10,T22
Phase3St	233	Covered	T3,T10,T22
TerminalSt	249	Covered	T3,T10,T22
TimeoutSt	159	Covered	T12,T22,T37

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T4,T7,T8
IdleSt->Phase0St	152	Covered	T3,T10,T23
IdleSt->TimeoutSt	159	Covered	T12,T22,T37
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T57,T27,T62
Phase0St->Phase1St	198	Covered	T3,T10,T22
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T30,T132,T121
Phase1St->Phase2St	215	Covered	T3,T10,T22
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T134,T135,T69
Phase2St->Phase3St	233	Covered	T3,T10,T22
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T28,T136,T69
Phase3St->TerminalSt	249	Covered	T3,T10,T22
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T3,T22,T48
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T12,T22,T37
TimeoutSt->Phase0St	172	Covered	T22,T35,T90

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T10
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T22,T37
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T22,T35,T90
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T12,T22,T37
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T12,T22,T37
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T62,T66,T131
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T10,T22
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T10,T22,T37
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T30,T132,T133
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T10,T22
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T10,T22
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T134,T135,T69
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T10,T22
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T10,T22
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T28,T136,T137
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T10,T22
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T10,T22,T37
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T22,T48
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T10,T22
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T8
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T8

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T8
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	574695525	189	0	0
CheckAccumTrig0_A	574695525	422	0	0
CheckAccumTrig1_A	574695525	18	0	0
CheckClr_A	574695525	176	0	0
CheckEn_A	574561090	205568966	0	0
CheckPhase0_A	574695525	469	0	0
CheckPhase1_A	574695525	463	0	0
CheckPhase2_A	574695525	453	0	0
CheckPhase3_A	574695525	437	0	0
CheckTimeout0_A	574695525	1167	0	0
CheckTimeoutSt1_A	574695525	104979	0	0
CheckTimeoutSt2_A	574695525	1102	0	0
CheckTimeoutStTrig_A	574695525	42	0	0
ErrorStAllEscAsserted_A	574695525	1134	0	0
ErrorStIsTerminal_A	574695525	924	0	0
EscStateOut_A	574560034	574493581	0	0
u_state_regs_A	574695525	574539856	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	189	0	0
T4	34842	68	0	0
T5	15921	0	0	0
T7	0	52	0	0
T8	0	27	0	0
T11	29498	0	0	0
T22	24928	0	0	0
T23	4116	0	0	0
T37	11404	0	0	0
T40	0	18	0	0
T41	0	24	0	0
T42	20946	0	0	0
T43	46627	0	0	0
T44	15130	0	0	0
T45	22910	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	422	0	0
T3	2516	2	0	0
T4	34842	0	0	0
T9	23434	0	0	0
T10	21386	1	0	0
T12	4255	0	0	0
T13	44856	0	0	0
T14	26042	0	0	0
T22	24928	0	0	0
T23	4116	1	0	0
T37	0	1	0	0
T42	20946	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	18	0	0
T58	25795	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T65	0	1	0	0
T66	0	2	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	2	0	0
T73	67665	0	0	0
T74	89372	0	0	0
T75	34761	0	0	0
T76	122573	0	0	0
T77	17544	0	0	0
T78	1721	0	0	0
T79	113162	0	0	0
T80	42026	0	0	0
T81	110592	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	176	0	0
T3	2516	2	0	0
T4	34842	0	0	0
T9	23434	0	0	0
T10	21386	0	0	0
T12	4255	0	0	0
T13	44856	0	0	0
T14	26042	0	0	0
T22	24928	1	0	0
T23	4116	0	0	0
T28	0	5	0	0
T35	0	1	0	0
T42	20946	0	0	0
T48	0	1	0	0
T53	0	1	0	0
T57	0	6	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574561090	205568966	0	0
T1	3625	2153	0	0
T2	17504	2161	0	0
T3	2516	586	0	0
T4	212	147	0	0
T9	23434	21779	0	0
T10	21386	3704	0	0
T12	4255	2120	0	0
T13	44856	44781	0	0
T14	26042	25942	0	0
T22	24928	3370	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	469	0	0
T3	2516	2	0	0
T4	34842	0	0	0
T9	23434	0	0	0
T10	21386	1	0	0
T12	4255	0	0	0
T13	44856	0	0	0
T14	26042	0	0	0
T22	24928	2	0	0
T23	4116	1	0	0
T35	0	2	0	0
T37	0	1	0	0
T42	20946	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T52	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	463	0	0
T3	2516	2	0	0
T4	34842	0	0	0
T9	23434	0	0	0
T10	21386	1	0	0
T12	4255	0	0	0
T13	44856	0	0	0
T14	26042	0	0	0
T22	24928	2	0	0
T23	4116	1	0	0
T35	0	2	0	0
T37	0	1	0	0
T42	20946	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T52	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	453	0	0
T3	2516	2	0	0
T4	34842	0	0	0
T9	23434	0	0	0
T10	21386	1	0	0
T12	4255	0	0	0
T13	44856	0	0	0
T14	26042	0	0	0
T22	24928	2	0	0
T23	4116	1	0	0
T35	0	2	0	0
T37	0	1	0	0
T42	20946	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T52	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	437	0	0
T3	2516	2	0	0
T4	34842	0	0	0
T9	23434	0	0	0
T10	21386	1	0	0
T12	4255	0	0	0
T13	44856	0	0	0
T14	26042	0	0	0
T22	24928	2	0	0
T23	4116	1	0	0
T35	0	2	0	0
T37	0	1	0	0
T42	20946	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T52	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	1167	0	0
T4	34842	0	0	0
T5	15921	0	0	0
T11	29498	0	0	0
T12	4255	1	0	0
T22	24928	3	0	0
T23	4116	0	0	0
T25	0	2	0	0
T35	0	2	0	0
T37	0	1	0	0
T42	20946	0	0	0
T43	46627	0	0	0
T44	15130	0	0	0
T45	22910	0	0	0
T53	0	1	0	0
T87	0	4	0	0
T89	0	6	0	0
T90	0	1	0	0
T92	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	104979	0	0
T4	34842	0	0	0
T5	15921	0	0	0
T11	29498	0	0	0
T12	4255	28	0	0
T22	24928	578	0	0
T23	4116	0	0	0
T25	0	303	0	0
T35	0	56	0	0
T37	0	186	0	0
T42	20946	0	0	0
T43	46627	0	0	0
T44	15130	0	0	0
T45	22910	0	0	0
T53	0	11	0	0
T87	0	279	0	0
T89	0	1383	0	0
T90	0	777	0	0
T92	0	145	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	1102	0	0
T4	34842	0	0	0
T5	15921	0	0	0
T11	29498	0	0	0
T12	4255	1	0	0
T22	24928	1	0	0
T23	4116	0	0	0
T25	0	2	0	0
T37	0	1	0	0
T42	20946	0	0	0
T43	46627	0	0	0
T44	15130	0	0	0
T45	22910	0	0	0
T53	0	1	0	0
T87	0	4	0	0
T89	0	6	0	0
T92	0	1	0	0
T95	0	43	0	0
T96	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	42	0	0
T5	15921	0	0	0
T11	29498	0	0	0
T22	24928	2	0	0
T23	4116	0	0	0
T32	0	1	0	0
T35	0	2	0	0
T37	11404	0	0	0
T42	20946	0	0	0
T43	46627	0	0	0
T44	15130	0	0	0
T45	22910	0	0	0
T67	0	1	0	0
T68	0	3	0	0
T90	0	1	0	0
T93	0	1	0	0
T94	8163	0	0	0
T102	0	1	0	0
T103	0	1	0	0
T104	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	1134	0	0
T4	34842	355	0	0
T5	15921	0	0	0
T7	0	326	0	0
T8	0	162	0	0
T11	29498	0	0	0
T22	24928	0	0	0
T23	4116	0	0	0
T37	11404	0	0	0
T40	0	148	0	0
T41	0	143	0	0
T42	20946	0	0	0
T43	46627	0	0	0
T44	15130	0	0	0
T45	22910	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	924	0	0
T4	34842	295	0	0
T5	15921	0	0	0
T7	0	266	0	0
T8	0	132	0	0
T11	29498	0	0	0
T22	24928	0	0	0
T23	4116	0	0	0
T37	11404	0	0	0
T40	0	118	0	0
T41	0	113	0	0
T42	20946	0	0	0
T43	46627	0	0	0
T44	15130	0	0	0
T45	22910	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574560034	574493581	0	0
T1	3625	3563	0	0
T2	17504	17381	0	0
T3	2516	2421	0	0
T4	84	20	0	0
T9	23434	23374	0	0
T10	21386	21302	0	0
T12	4255	4171	0	0
T13	44856	44782	0	0
T14	26042	25943	0	0
T22	24928	24838	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	574539856	0	0
T1	3625	3563	0	0
T2	17504	17381	0	0
T3	2516	2421	0	0
T4	34842	9426	0	0
T9	23434	23374	0	0
T10	21386	21302	0	0
T12	4255	4171	0	0
T13	44856	44782	0	0
T14	26042	25943	0	0
T22	24928	24838	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T3 T10 T22 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T3 T10 T22 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T3 T10 T22 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T13 T22 T42 
159        1/1                    state_d = TimeoutSt;
           Tests:       T13 T22 T42 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T13 T22 T42 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T13 T22 T42 
172        1/1                    state_d    = Phase0St;
           Tests:       T90 T97 T56 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T90 T97 T56 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T90 T97 T56 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T90 T97 T56 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T13 T22 T42 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T13 T22 T42 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T13 T22 T42 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T13 T22 T42 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T3 T10 T22 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T3 T10 T22 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T3 T10 T22 
190        1/1                  esc_state_o = Phase0;
           Tests:       T3 T10 T22 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T3 T10 T22 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T3 T10 T22 
194        1/1                    state_d = IdleSt;
           Tests:       T56 T61 T33 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T56 T61 T33 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T56 T61 T33 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T3 T10 T22 
198        1/1                    state_d = Phase1St;
           Tests:       T3 T10 T22 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T10 T22 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T3 T10 T22 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T3 T10 T22 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T3 T10 T22 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T3 T10 T22 
207        1/1                  esc_state_o = Phase1;
           Tests:       T3 T10 T22 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T3 T10 T22 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T3 T10 T22 
211        1/1                    state_d = IdleSt;
           Tests:       T61 T33 T139 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T61 T33 T139 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T61 T33 T139 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T3 T10 T22 
215        1/1                    state_d = Phase2St;
           Tests:       T3 T10 T22 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T10 T22 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T3 T10 T22 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T3 T10 T22 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T3 T10 T22 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T3 T10 T22 
224        1/1                  esc_state_o = Phase2;
           Tests:       T3 T10 T22 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T3 T10 T22 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T3 T10 T22 
229        1/1                    state_d = IdleSt;
           Tests:       T56 T61 T140 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T56 T61 T140 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T56 T61 T140 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T3 T10 T22 
233        1/1                    state_d = Phase3St;
           Tests:       T3 T10 T22 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T10 T22 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T3 T10 T22 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T3 T10 T22 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T3 T10 T22 
241        1/1                  esc_state_o = Phase3;
           Tests:       T3 T10 T22 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T3 T10 T22 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T3 T10 T22 
245        1/1                    state_d = IdleSt;
           Tests:       T141 T142 T139 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T141 T142 T139 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T141 T142 T139 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T3 T10 T22 
249        1/1                    state_d = TerminalSt;
           Tests:       T3 T10 T22 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T10 T22 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T3 T10 T22 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T3 T10 T22 
259        1/1                  esc_state_o = Terminal;
           Tests:       T3 T10 T22 
260        1/1                  if (clr_i) begin
           Tests:       T3 T10 T22 
261        1/1                    state_d = IdleSt;
           Tests:       T3 T10 T22 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T4 T7 T8 
269        1/1                  fsm_error = 1'b1;
           Tests:       T4 T7 T8 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T4 T7 T8 
285        1/1                fsm_error = 1'b1;
           Tests:       T4 T7 T8 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T8
1	0	Covered	T3,T10,T13
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T10,T13

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T34
1	1	1	Covered	T3,T10,T22

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T13,T22
1	0	1	Covered	T44,T72,T15
1	1	0	Covered	T12,T22,T37
1	1	1	Covered	T13,T22,T42

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T13,T22,T42
0	1	Covered	T90,T97,T56
1	0	Covered	T138,T143,T140

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T13,T22,T42
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T138,T143,T140

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T22,T42
1	0	Not Covered
1	1	Covered	T90,T97,T56

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T10,T48
1	Covered	T22,T49,T144

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T10,T22
1	Covered	T53,T85,T145

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T10,T22,T49
1	Covered	T3,T10,T48

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T10,T22
1	Covered	T10,T50,T125

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T4,T7,T8

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T10,T22,T49

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T3,T10,T48

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T10,T49,T50

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T7,T8
1	0	Covered	T3,T10,T48

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T7,T8
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T3,T10,T22
Phase1St	198	Covered	T3,T10,T22
Phase2St	215	Covered	T3,T10,T22
Phase3St	233	Covered	T3,T10,T22
TerminalSt	249	Covered	T3,T10,T22
TimeoutSt	159	Covered	T13,T22,T42

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T4,T7,T8
IdleSt->Phase0St	152	Covered	T3,T10,T22
IdleSt->TimeoutSt	159	Covered	T13,T22,T42
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T56,T57,T61
Phase0St->Phase1St	198	Covered	T3,T10,T22
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T39,T61,T33
Phase1St->Phase2St	215	Covered	T3,T10,T22
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T56,T61,T140
Phase2St->Phase3St	233	Covered	T3,T10,T22
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T141,T142,T139
Phase3St->TerminalSt	249	Covered	T3,T10,T22
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T3,T10,T22
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T13,T22,T42
TimeoutSt->Phase0St	172	Covered	T90,T97,T56

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T10,T22
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T22,T42
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T90,T97,T56
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T13,T22,T42
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T13,T22,T42
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T56,T61,T33
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T10,T22
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T10,T22
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T61,T33,T139
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T10,T22
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T10,T22
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T56,T61,T140
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T10,T22
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T10,T22
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T141,T142,T139
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T10,T22
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T10,T22
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T10,T22
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T10,T22
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T8
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T8

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T8
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	574695525	221	0	0
CheckAccumTrig0_A	574695525	477	0	0
CheckAccumTrig1_A	574695525	16	0	0
CheckClr_A	574695525	249	0	0
CheckEn_A	574561090	220362855	0	0
CheckPhase0_A	574695525	528	0	0
CheckPhase1_A	574695525	520	0	0
CheckPhase2_A	574695525	507	0	0
CheckPhase3_A	574695525	494	0	0
CheckTimeout0_A	574695525	950	0	0
CheckTimeoutSt1_A	574695525	90191	0	0
CheckTimeoutSt2_A	574695525	876	0	0
CheckTimeoutStTrig_A	574695525	56	0	0
ErrorStAllEscAsserted_A	574695525	1175	0	0
ErrorStIsTerminal_A	574695525	965	0	0
EscStateOut_A	574560034	574493581	0	0
u_state_regs_A	574695525	574539856	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	221	0	0
T4	34842	67	0	0
T5	15921	0	0	0
T7	0	48	0	0
T8	0	31	0	0
T11	29498	0	0	0
T22	24928	0	0	0
T23	4116	0	0	0
T37	11404	0	0	0
T40	0	49	0	0
T41	0	26	0	0
T42	20946	0	0	0
T43	46627	0	0	0
T44	15130	0	0	0
T45	22910	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	477	0	0
T3	2516	1	0	0
T4	34842	0	0	0
T9	23434	0	0	0
T10	21386	2	0	0
T12	4255	0	0	0
T13	44856	0	0	0
T14	26042	0	0	0
T22	24928	2	0	0
T23	4116	0	0	0
T42	20946	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T53	0	1	0	0
T144	0	1	0	0
T146	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	16	0	0
T39	133062	0	0	0
T57	236883	0	0	0
T58	25795	0	0	0
T86	25636	0	0	0
T117	0	1	0	0
T136	0	1	0	0
T138	32358	1	0	0
T140	0	1	0	0
T143	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	50439	0	0	0
T153	16431	0	0	0
T154	3678	0	0	0
T155	139108	0	0	0
T156	198972	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	249	0	0
T3	2516	1	0	0
T4	34842	0	0	0
T9	23434	0	0	0
T10	21386	1	0	0
T12	4255	0	0	0
T13	44856	0	0	0
T14	26042	0	0	0
T22	24928	1	0	0
T23	4116	0	0	0
T39	0	1	0	0
T42	20946	0	0	0
T48	0	1	0	0
T56	0	7	0	0
T85	0	1	0	0
T86	0	1	0	0
T97	0	1	0	0
T138	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574561090	220362855	0	0
T1	3625	2175	0	0
T2	17504	2203	0	0
T3	2516	1351	0	0
T4	212	147	0	0
T9	23434	23373	0	0
T10	21386	1836	0	0
T12	4255	4170	0	0
T13	44856	2049	0	0
T14	26042	25942	0	0
T22	24928	4888	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	528	0	0
T3	2516	1	0	0
T4	34842	0	0	0
T9	23434	0	0	0
T10	21386	2	0	0
T12	4255	0	0	0
T13	44856	0	0	0
T14	26042	0	0	0
T22	24928	2	0	0
T23	4116	0	0	0
T42	20946	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T53	0	1	0	0
T144	0	1	0	0
T146	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	520	0	0
T3	2516	1	0	0
T4	34842	0	0	0
T9	23434	0	0	0
T10	21386	2	0	0
T12	4255	0	0	0
T13	44856	0	0	0
T14	26042	0	0	0
T22	24928	2	0	0
T23	4116	0	0	0
T42	20946	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T53	0	1	0	0
T144	0	1	0	0
T146	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	507	0	0
T3	2516	1	0	0
T4	34842	0	0	0
T9	23434	0	0	0
T10	21386	2	0	0
T12	4255	0	0	0
T13	44856	0	0	0
T14	26042	0	0	0
T22	24928	2	0	0
T23	4116	0	0	0
T42	20946	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T53	0	1	0	0
T144	0	1	0	0
T146	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	494	0	0
T3	2516	1	0	0
T4	34842	0	0	0
T9	23434	0	0	0
T10	21386	2	0	0
T12	4255	0	0	0
T13	44856	0	0	0
T14	26042	0	0	0
T22	24928	2	0	0
T23	4116	0	0	0
T42	20946	0	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T53	0	1	0	0
T144	0	1	0	0
T146	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	950	0	0
T4	34842	0	0	0
T5	15921	0	0	0
T11	29498	0	0	0
T12	4255	0	0	0
T13	44856	5	0	0
T22	24928	1	0	0
T23	4116	0	0	0
T25	0	3	0	0
T31	0	1	0	0
T35	0	9	0	0
T42	20946	9	0	0
T43	46627	0	0	0
T44	15130	0	0	0
T88	0	1	0	0
T89	0	9	0	0
T90	0	1	0	0
T92	0	3	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	90191	0	0
T4	34842	0	0	0
T5	15921	0	0	0
T11	29498	0	0	0
T12	4255	0	0	0
T13	44856	603	0	0
T22	24928	3	0	0
T23	4116	0	0	0
T25	0	435	0	0
T31	0	122	0	0
T35	0	1608	0	0
T42	20946	740	0	0
T43	46627	0	0	0
T44	15130	0	0	0
T88	0	278	0	0
T89	0	2610	0	0
T90	0	785	0	0
T92	0	614	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	876	0	0
T4	34842	0	0	0
T5	15921	0	0	0
T11	29498	0	0	0
T12	4255	0	0	0
T13	44856	5	0	0
T22	24928	1	0	0
T23	4116	0	0	0
T25	0	3	0	0
T31	0	1	0	0
T35	0	9	0	0
T42	20946	9	0	0
T43	46627	0	0	0
T44	15130	0	0	0
T88	0	1	0	0
T89	0	9	0	0
T92	0	3	0	0
T95	0	41	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	56	0	0
T31	47213	0	0	0
T56	0	2	0	0
T66	0	2	0	0
T90	98112	1	0	0
T91	27862	0	0	0
T92	83375	0	0	0
T93	359909	0	0	0
T95	173173	0	0	0
T97	0	1	0	0
T103	0	2	0	0
T104	0	3	0	0
T125	177096	0	0	0
T126	130899	0	0	0
T137	0	2	0	0
T142	0	1	0	0
T157	0	1	0	0
T158	0	2	0	0
T159	44749	0	0	0
T160	89375	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	1175	0	0
T4	34842	348	0	0
T5	15921	0	0	0
T7	0	346	0	0
T8	0	157	0	0
T11	29498	0	0	0
T22	24928	0	0	0
T23	4116	0	0	0
T37	11404	0	0	0
T40	0	153	0	0
T41	0	171	0	0
T42	20946	0	0	0
T43	46627	0	0	0
T44	15130	0	0	0
T45	22910	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	965	0	0
T4	34842	288	0	0
T5	15921	0	0	0
T7	0	286	0	0
T8	0	127	0	0
T11	29498	0	0	0
T22	24928	0	0	0
T23	4116	0	0	0
T37	11404	0	0	0
T40	0	123	0	0
T41	0	141	0	0
T42	20946	0	0	0
T43	46627	0	0	0
T44	15130	0	0	0
T45	22910	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574560034	574493581	0	0
T1	3625	3563	0	0
T2	17504	17381	0	0
T3	2516	2421	0	0
T4	84	20	0	0
T9	23434	23374	0	0
T10	21386	21302	0	0
T12	4255	4171	0	0
T13	44856	44782	0	0
T14	26042	25943	0	0
T22	24928	24838	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	574695525	574539856	0	0
T1	3625	3563	0	0
T2	17504	17381	0	0
T3	2516	2421	0	0
T4	34842	9426	0	0
T9	23434	23374	0	0
T10	21386	21302	0	0
T12	4255	4171	0	0
T13	44856	44782	0	0
T14	26042	25943	0	0
T22	24928	24838	0	0