Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	47920	1			T26	914		T20	2		T83	26
class_i[0x1]	51588	1			T40	93		T265	7		T83	3
class_i[0x2]	25319	1			T158	1		T19	1		T20	3
class_i[0x3]	67154	1			T18	1		T19	1		T20	2

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	48829	1			T26	2		T40	14		T19	1
alert[0x1]	47235	1			T26	597		T40	15		T265	4
alert[0x2]	48187	1			T26	313		T40	45		T20	3
alert[0x3]	47730	1			T26	2		T158	1		T40	19

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

191718

1

T26

914

T158

1

T40

93

esc_ping_fail

263

1

T18

1

T19

2

T20

2

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	48751	1			T26	2		T40	14		T20	3
esc_integrity_fail	alert[0x1]	47176	1			T26	597		T40	15		T265	3
esc_integrity_fail	alert[0x2]	48125	1			T26	313		T40	45		T20	2
esc_integrity_fail	alert[0x3]	47666	1			T26	2		T158	1		T40	19
esc_ping_fail	alert[0x0]	78	1			T19	1		T20	1		T265	1
esc_ping_fail	alert[0x1]	59	1			T265	1		T266	1		T328	3
esc_ping_fail	alert[0x2]	62	1			T20	1		T266	2		T325	1
esc_ping_fail	alert[0x3]	64	1			T18	1		T19	1		T265	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	47863	1			T26	914		T83	26		T94	152
esc_integrity_fail	class_i[0x1]	51515	1			T40	93		T265	7		T83	3
esc_integrity_fail	class_i[0x2]	25254	1			T158	1		T20	3		T97	3
esc_integrity_fail	class_i[0x3]	67086	1			T20	2		T83	13		T33	108
esc_ping_fail	class_i[0x0]	57	1			T20	2		T325	1		T336	6
esc_ping_fail	class_i[0x1]	73	1			T266	7		T328	6		T325	4
esc_ping_fail	class_i[0x2]	65	1			T19	1		T265	4		T325	1
esc_ping_fail	class_i[0x3]	68	1			T18	1		T19	1		T326	2