Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	95899	1			T13	587		T27	3		T51	2
class_i[0x1]	47923	1			T13	7		T54	5		T88	8
class_i[0x2]	30337	1			T27	10		T42	367		T88	5
class_i[0x3]	59080	1			T13	3		T27	215		T51	18

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	58544	1			T13	8		T27	6		T51	4
alert[0x1]	58172	1			T13	7		T51	5		T42	28
alert[0x2]	59430	1			T13	580		T27	221		T51	9
alert[0x3]	57093	1			T13	2		T27	1		T51	2

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

232931

1

T13

597

T27

228

T51

20

esc_ping_fail

308

1

T16

5

T17

3

T18

8

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	58458	1			T13	8		T27	6		T51	4
esc_integrity_fail	alert[0x1]	58091	1			T13	7		T51	5		T42	28
esc_integrity_fail	alert[0x2]	59355	1			T13	580		T27	221		T51	9
esc_integrity_fail	alert[0x3]	57027	1			T13	2		T27	1		T51	2
esc_ping_fail	alert[0x0]	86	1			T16	2		T17	2		T18	2
esc_ping_fail	alert[0x1]	81	1			T16	2		T18	2		T131	3
esc_ping_fail	alert[0x2]	75	1			T16	1		T17	1		T18	2
esc_ping_fail	alert[0x3]	66	1			T18	2		T130	1		T131	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	95822	1			T13	587		T27	3		T51	2
esc_integrity_fail	class_i[0x1]	47825	1			T13	7		T54	5		T88	8
esc_integrity_fail	class_i[0x2]	30275	1			T27	10		T42	367		T88	5
esc_integrity_fail	class_i[0x3]	59009	1			T13	3		T27	215		T51	18
esc_ping_fail	class_i[0x0]	77	1			T17	1		T341	3		T340	9
esc_ping_fail	class_i[0x1]	98	1			T17	2		T18	8		T343	4
esc_ping_fail	class_i[0x2]	62	1			T16	1		T131	6		T344	6
esc_ping_fail	class_i[0x3]	71	1			T16	4		T130	3		T362	1