Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	550566037	0	0	622
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	550566037	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	550566037	550407217	0	0
tb.dut.CheckAccuCntDw	0	0	622	622	0	0
tb.dut.CheckEscCntDw	0	0	622	622	0	0
tb.dut.CheckNAlerts	0	0	622	622	0	0
tb.dut.CheckNClasses	0	0	622	622	0	0
tb.dut.CheckNEscSev	0	0	622	622	0	0
tb.dut.CrashdumpKnownO_A	0	0	550566037	550407217	0	0
tb.dut.EdnKnownO_A	0	0	550566037	550407217	0	0
tb.dut.EscPKnownO_A	0	0	550566037	550407217	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	550566037	70	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	550566037	70	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	550566037	70	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	550566037	70	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	550566037	70	0	0
tb.dut.IrqAKnownO_A	0	0	550566037	550407217	0	0
tb.dut.IrqBKnownO_A	0	0	550566037	550407217	0	0
tb.dut.IrqCKnownO_A	0	0	550566037	550407217	0	0
tb.dut.IrqDKnownO_A	0	0	550566037	550407217	0	0
tb.dut.TlAReadyKnownO_A	0	0	550566037	550407217	0	0
tb.dut.TlDValidKnownO_A	0	0	550566037	550407217	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	575319970	166138	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	575319970	13790	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	575319970	13629	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	575319970	13307	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	575319970	13564	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	575319970	13486	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	575319970	14447	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	575319970	13487	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	575319970	14187	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	575319970	13906	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	575319970	13725	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	575319970	13555	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	575319970	13441	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	575319970	14052	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	575319970	13847	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	575319970	13915	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	575319970	13469	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	575319970	13853	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	575319970	14900	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	575319970	14225	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	575319970	14556	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	575319970	13760	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	575319970	14367	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	575319970	14089	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	575319970	13626	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	575319970	14470	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	575319970	13675	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	575319970	14913	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	575319970	13355	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	575319970	13539	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	575319970	13344	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	575319970	14486	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	575319970	13702	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	575319970	14482	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	575319970	14407	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	575319970	13664	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	575319970	13761	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	575319970	13562	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	575319970	14108	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	575319970	14266	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	575319970	13615	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	575319970	13746	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	575319970	14332	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	575319970	14147	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	575319970	13781	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	575319970	14199	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	575319970	13867	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	575319970	13714	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	575319970	14820	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	575319970	13721	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	575319970	14070	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	575319970	14043	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	575319970	13978	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	575319970	13258	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	575319970	14365	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	575319970	13306	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	575319970	13581	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	575319970	13656	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	575319970	14265	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	575319970	13680	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	575319970	14358	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	575319970	13696	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	575319970	13771	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	575319970	14315	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	575319970	13787	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	575319970	14428	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	575319970	13460	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	575319970	13681	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	575319970	14608	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	575319970	14122	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	575319970	27867	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	575319970	13446	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	575319970	14968	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	575319970	13833	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	575319970	13797	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	575319970	14107	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	575319970	13981	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	575319970	13785	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	575319970	14002	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	550566037	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	550566037	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	550566037	70	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	550566037	2212	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	550566037	163064	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	550566037	292503874	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	550566037	187	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	550566037	762	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	550566037	41	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	550566037	380	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	550428711	238899323	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	550566037	855	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	550566037	826	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	550566037	797	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	550566037	782	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	550566037	514	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	550566037	63612	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	550566037	403	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	550566037	67	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	550566037	1153	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	550566037	943	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	550427392	550357694	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	622	622	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	550566037	550407217	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	550566037	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	550566037	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	550566037	70	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	550566037	3421	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	550566037	186369	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	550566037	291945697	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	550566037	148	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	550566037	475	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	550566037	24	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	550566037	223	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	550428711	228126846	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	550566037	547	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	550566037	537	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	550566037	528	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	550566037	514	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	550566037	452	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	550566037	63875	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	550566037	369	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	550566037	54	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	550566037	1104	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	550566037	894	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	550427392	550357694	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	622	622	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	550566037	550407217	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	550566037	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	550566037	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	550566037	70	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	550566037	2090	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	550566037	167296	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	550566037	308858761	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	550566037	245	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	550566037	537	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	550566037	16	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	550566037	274	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	550428711	220034436	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	550566037	588	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	550566037	569	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	550566037	551	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	550566037	533	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	550566037	468	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	550566037	56246	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	550566037	406	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	550566037	45	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	550566037	1082	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	550566037	872	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	550427392	550357694	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	622	622	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	550566037	550407217	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	550566037	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	550566037	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	550566037	70	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	550566037	5021	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	550566037	186118	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	550566037	291819476	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	550566037	220	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	550566037	478	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	550566037	28	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	550566037	231	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	550428711	238906740	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	550566037	531	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	550566037	524	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	550566037	517	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	550566037	503	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	550566037	744	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	550566037	89531	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	550566037	670	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	550566037	42	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	550566037	1194	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	550566037	984	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	550427392	550357694	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	622	622	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	550566037	550407217	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	575319970	83234920	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	575319970	574651505	0	0
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