Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	653253201	0	0	622
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	653253201	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	653253201	653070951	0	0
tb.dut.CheckAccuCntDw	0	0	622	622	0	0
tb.dut.CheckEscCntDw	0	0	622	622	0	0
tb.dut.CheckNAlerts	0	0	622	622	0	0
tb.dut.CheckNClasses	0	0	622	622	0	0
tb.dut.CheckNEscSev	0	0	622	622	0	0
tb.dut.CrashdumpKnownO_A	0	0	653253201	653070951	0	0
tb.dut.EdnKnownO_A	0	0	653253201	653070951	0	0
tb.dut.EscPKnownO_A	0	0	653253201	653070951	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	653253201	90	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	653253201	90	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	653253201	90	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	653253201	90	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	653253201	90	0	0
tb.dut.IrqAKnownO_A	0	0	653253201	653070951	0	0
tb.dut.IrqBKnownO_A	0	0	653253201	653070951	0	0
tb.dut.IrqCKnownO_A	0	0	653253201	653070951	0	0
tb.dut.IrqDKnownO_A	0	0	653253201	653070951	0	0
tb.dut.TlAReadyKnownO_A	0	0	653253201	653070951	0	0
tb.dut.TlDValidKnownO_A	0	0	653253201	653070951	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	678394440	3412432	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	678394440	14483	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	678394440	15965	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	678394440	15467	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	678394440	15972	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	678394440	14188	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	678394440	15346	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	678394440	13620	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	678394440	16014	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	678394440	14959	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	678394440	14688	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	678394440	15719	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	678394440	16340	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	678394440	15909	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	678394440	16040	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	678394440	15814	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	678394440	14028	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	678394440	14283	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	678394440	15118	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	678394440	15358	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	678394440	14265	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	678394440	16081	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	678394440	14042	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	678394440	14117	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	678394440	14176	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	678394440	14737	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	678394440	14252	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	678394440	16009	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	678394440	15567	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	678394440	15409	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	678394440	15182	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	678394440	15242	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	678394440	14178	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	678394440	15300	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	678394440	13626	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	678394440	14933	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	678394440	15006	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	678394440	15065	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	678394440	14057	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	678394440	15299	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	678394440	16104	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	678394440	16411	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	678394440	15470	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	678394440	14262	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	678394440	16101	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	678394440	13984	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	678394440	14155	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	678394440	14487	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	678394440	14302	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	678394440	14949	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	678394440	14225	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	678394440	14764	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	678394440	17519	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	678394440	15213	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	678394440	13991	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	678394440	15317	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	678394440	14856	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	678394440	13948	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	678394440	14093	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	678394440	13871	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	678394440	14293	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	678394440	14735	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	678394440	15274	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	678394440	15724	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	678394440	16300	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	678394440	14279	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	678394440	15537	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	678394440	14524	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	678394440	14658	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	678394440	14033	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	678394440	28508	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	678394440	15034	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	678394440	15923	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	678394440	14329	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	678394440	15258	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	678394440	14506	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	678394440	15277	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	678394440	17170	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	678394440	14663	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	653253201	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	653253201	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	653253201	90	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	653253201	4324	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	653253201	243038	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	653253201	312246353	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	653253201	233	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	653253201	810	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	653253201	56	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	653253201	410	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	653083950	243426876	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	653253201	915	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	653253201	897	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	653253201	876	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	653253201	857	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	653253201	1314	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	653253201	142859	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	653253201	1197	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	653253201	59	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	653253201	1469	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	653253201	1199	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	653083129	653015626	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	622	622	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	653253201	653070951	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	653253201	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	653253201	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	653253201	90	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	653253201	3101	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	653253201	181704	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	653253201	412486860	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	653253201	227	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	653253201	470	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	653253201	16	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	653253201	230	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	653083950	317175423	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	653253201	552	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	653253201	547	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	653253201	538	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	653253201	527	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	653253201	746	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	653253201	94930	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	653253201	655	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	653253201	75	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	653253201	1447	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	653253201	1177	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	653083129	653015626	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	622	622	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	653253201	653070951	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	653253201	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	653253201	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	653253201	90	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	653253201	3279	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	653253201	174022	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	653253201	373991347	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	653253201	243	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	653253201	454	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	653253201	23	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	653253201	195	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	653083950	307473113	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	653253201	527	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	653253201	519	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	653253201	514	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	653253201	511	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	653253201	764	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	653253201	85739	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	653253201	673	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	653253201	67	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	653253201	1490	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	653253201	1220	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	653083129	653015626	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	622	622	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	653253201	653070951	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	653253201	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	653253201	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	653253201	90	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	653253201	2699	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	653253201	177083	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	653253201	381171964	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	653253201	273	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	653253201	479	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	653253201	23	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	653253201	230	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	653083950	311706560	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	653253201	555	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	653253201	544	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	653253201	528	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	653253201	523	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	653253201	718	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	653253201	103641	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	653253201	633	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	653253201	62	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	653253201	1502	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	653253201	1232	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	653083129	653015626	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	622	622	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	653253201	653070951	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	678394440	138060541	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	678394440	677700103	0	0
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