Design Hierarchy
dashboard | hierarchy | modlist | groups | tests | asserts

NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb 99.19 99.99 98.69 97.09 100.00 100.00 99.38
dut 99.19 99.99 98.69 97.09 100.00 100.00 99.38
alert_handler_csr_assert 100.00 100.00
gen_alerts[0].u_alert_receiver 100.00 100.00
gen_alerts[10].u_alert_receiver 100.00 100.00
gen_alerts[11].u_alert_receiver 100.00 100.00
gen_alerts[12].u_alert_receiver 100.00 100.00
gen_alerts[13].u_alert_receiver 100.00 100.00
gen_alerts[14].u_alert_receiver 100.00 100.00
gen_alerts[15].u_alert_receiver 100.00 100.00
gen_alerts[16].u_alert_receiver 100.00 100.00
gen_alerts[17].u_alert_receiver 100.00 100.00
gen_alerts[18].u_alert_receiver 100.00 100.00
gen_alerts[19].u_alert_receiver 100.00 100.00
gen_alerts[1].u_alert_receiver 100.00 100.00
gen_alerts[20].u_alert_receiver 100.00 100.00
gen_alerts[21].u_alert_receiver 100.00 100.00
gen_alerts[22].u_alert_receiver 100.00 100.00
gen_alerts[23].u_alert_receiver 100.00 100.00
gen_alerts[24].u_alert_receiver 100.00 100.00
gen_alerts[25].u_alert_receiver 100.00 100.00
gen_alerts[26].u_alert_receiver 100.00 100.00
gen_alerts[27].u_alert_receiver 100.00 100.00
gen_alerts[28].u_alert_receiver 100.00 100.00
gen_alerts[29].u_alert_receiver 100.00 100.00
gen_alerts[2].u_alert_receiver 100.00 100.00
gen_alerts[30].u_alert_receiver 100.00 100.00
gen_alerts[31].u_alert_receiver 100.00 100.00
gen_alerts[32].u_alert_receiver 100.00 100.00
gen_alerts[33].u_alert_receiver 100.00 100.00
gen_alerts[34].u_alert_receiver 100.00 100.00
gen_alerts[35].u_alert_receiver 100.00 100.00
gen_alerts[36].u_alert_receiver 100.00 100.00
gen_alerts[37].u_alert_receiver 100.00 100.00
gen_alerts[38].u_alert_receiver 100.00 100.00
gen_alerts[39].u_alert_receiver 100.00 100.00
gen_alerts[3].u_alert_receiver 100.00 100.00
gen_alerts[40].u_alert_receiver 100.00 100.00
gen_alerts[41].u_alert_receiver 100.00 100.00
gen_alerts[42].u_alert_receiver 100.00 100.00
gen_alerts[43].u_alert_receiver 100.00 100.00
gen_alerts[44].u_alert_receiver 100.00 100.00
gen_alerts[45].u_alert_receiver 100.00 100.00
gen_alerts[46].u_alert_receiver 100.00 100.00
gen_alerts[47].u_alert_receiver 100.00 100.00
gen_alerts[48].u_alert_receiver 100.00 100.00
gen_alerts[49].u_alert_receiver 100.00 100.00
gen_alerts[4].u_alert_receiver 100.00 100.00
gen_alerts[50].u_alert_receiver 100.00 100.00
gen_alerts[51].u_alert_receiver 100.00 100.00
gen_alerts[52].u_alert_receiver 100.00 100.00
gen_alerts[53].u_alert_receiver 100.00 100.00
gen_alerts[54].u_alert_receiver 100.00 100.00
gen_alerts[55].u_alert_receiver 100.00 100.00
gen_alerts[56].u_alert_receiver 100.00 100.00
gen_alerts[57].u_alert_receiver 100.00 100.00
gen_alerts[58].u_alert_receiver 100.00 100.00
gen_alerts[59].u_alert_receiver 100.00 100.00
gen_alerts[5].u_alert_receiver 100.00 100.00
gen_alerts[60].u_alert_receiver 100.00 100.00
gen_alerts[61].u_alert_receiver 100.00 100.00
gen_alerts[62].u_alert_receiver 100.00 100.00
gen_alerts[63].u_alert_receiver 100.00 100.00
gen_alerts[64].u_alert_receiver 100.00 100.00
gen_alerts[6].u_alert_receiver 100.00 100.00
gen_alerts[7].u_alert_receiver 100.00 100.00
gen_alerts[8].u_alert_receiver 100.00 100.00
gen_alerts[9].u_alert_receiver 100.00 100.00
gen_classes[0].u_accu 100.00 100.00 100.00 100.00 100.00
u_prim_count 100.00 100.00
gen_classes[0].u_esc_timer 94.02 100.00 95.56 68.57 100.00 100.00 100.00
u_prim_count 68.57 68.57
u_state_regs 100.00 100.00 100.00 100.00
u_state_flop 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
gen_classes[1].u_accu 100.00 100.00 100.00 100.00 100.00
u_prim_count 100.00 100.00
gen_classes[1].u_esc_timer 93.65 100.00 93.33 68.57 100.00 100.00 100.00
u_prim_count 68.57 68.57
u_state_regs 100.00 100.00 100.00 100.00
u_state_flop 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
gen_classes[2].u_accu 100.00 100.00 100.00 100.00 100.00
u_prim_count 100.00 100.00
gen_classes[2].u_esc_timer 93.65 100.00 93.33 68.57 100.00 100.00 100.00
u_prim_count 68.57 68.57
u_state_regs 100.00 100.00 100.00 100.00
u_state_flop 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
gen_classes[3].u_accu 100.00 100.00 100.00 100.00 100.00
u_prim_count 100.00 100.00
gen_classes[3].u_esc_timer 93.65 100.00 93.33 68.57 100.00 100.00 100.00
u_prim_count 68.57 68.57
u_state_regs 100.00 100.00 100.00 100.00
u_state_flop 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
gen_esc_sev[0].u_esc_sender 100.00 100.00
gen_esc_sev[1].u_esc_sender 100.00 100.00
gen_esc_sev[2].u_esc_sender 100.00 100.00
gen_esc_sev[3].u_esc_sender 100.00 100.00
tlul_assert_device 97.90 97.90
u_alert_handler_lpg_ctrl 100.00 100.00 100.00 100.00
subtree...
u_class 100.00 100.00
u_edn_req 91.96 100.00 92.86 100.00 75.00
u_prim_packer_fifo 74.32 100.00 97.30 100.00 0.00
u_prim_sync_reqack_data 95.83 100.00 83.33 100.00 100.00
u_prim_sync_reqack 95.83 100.00 83.33 100.00 100.00
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_ping_timer 99.57 100.00 97.44 100.00 100.00 100.00 100.00
u_prim_buf_spurious_alert_ping 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
u_prim_buf_spurious_esc_ping 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
u_prim_count_cnt 100.00 100.00
u_prim_count_esc_cnt 100.00 100.00
u_prim_double_lfsr 100.00 100.00 100.00 100.00 100.00
gen_double_lfsr[0].u_prim_buf_input 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
gen_double_lfsr[0].u_prim_buf_output 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
gen_double_lfsr[0].u_prim_lfsr 100.00 100.00
gen_double_lfsr[1].u_prim_buf_input 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
gen_double_lfsr[1].u_prim_buf_output 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
gen_double_lfsr[1].u_prim_lfsr 100.00 100.00
u_state_regs 100.00 100.00 100.00 100.00
u_state_flop 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_reg_wrap 99.75 99.99 98.75 100.00 100.00 100.00
u_irq_classa 100.00 100.00 100.00 100.00 100.00
u_irq_classb 100.00 100.00 100.00 100.00 100.00
u_irq_classc 100.00 100.00 100.00 100.00 100.00
u_irq_classd 100.00 100.00 100.00 100.00 100.00
u_reg 99.74 99.99 98.72 100.00 100.00 100.00
subtree...
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