Testbench Group List
dashboard | hierarchy | modlist | groups | tests | asserts
Total Groups Coverage Summary 
COVEREDEXPECTEDSCORECOVEREDEXPECTEDINST SCOREWEIGHT
2477 2486 99.64 2477 2486 99.64 1


Total groups in report: 32
NAMECOVEREDEXPECTEDSCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSINGCOMMENT
tl_agent_pkg::pending_req_on_rst_cg 1 2 50.00 50.00 1 100 1 1 64 64
alert_handler_env_pkg::alert_handler_env_cov::cycles_between_pings_cg 3 5 60.00 1 100 1 0 64 64
cip_base_pkg::tl_errors_cg_wrap::tl_errors_cg 12 15 80.00 100.00 1 100 1 1 64 64
cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg 13 14 92.86 100.00 1 100 1 1 64 64
alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg 52 54 96.30 1 100 1 0 64 64
alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg 57 59 96.61 1 100 1 0 64 64
alert_esc_agent_pkg::alert_esc_trans_cg 2 2 100.00 100.00 1 100 1 1 64 64
alert_esc_agent_pkg::alert_handshake_complete_cg 3 3 100.00 100.00 1 100 1 1 64 64
alert_esc_agent_pkg::alert_lpg_cg 2 2 100.00 100.00 1 100 1 1 64 64
alert_esc_agent_pkg::esc_handshake_complete_cg 3 3 100.00 100.00 1 100 1 1 64 64
alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg 34 34 100.00 1 100 1 0 64 64
alert_handler_env_pkg::alert_handler_env_cov::alert_cause_cg 329 329 100.00 1 100 1 0 64 64
alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg 209 209 100.00 1 100 1 0 64 64
alert_handler_env_pkg::alert_handler_env_cov::clear_esc_cnt_cg 4 4 100.00 1 100 1 0 64 64
alert_handler_env_pkg::alert_handler_env_cov::clear_intr_cnt_cg 4 4 100.00 1 100 1 0 64 64
alert_handler_env_pkg::alert_handler_env_cov::crashdump_trigger_cg 4 4 100.00 1 100 1 0 64 64
alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg 26 26 100.00 1 100 1 0 64 64
alert_handler_env_pkg::alert_handler_env_cov::num_checked_pings_cg 3 3 100.00 1 100 1 0 64 64
alert_handler_env_pkg::alert_handler_env_cov::num_edn_reqs_cg 2 2 100.00 1 100 1 0 64 64
alert_handler_env_pkg::alert_ping_with_lpg_cg_wrap::alert_ping_with_lpg_cg 2 2 100.00 100.00 1 100 1 1 64 64
cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3} 24 24 100.00 1 100 1 0 64 64
cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3} 24 24 100.00 1 100 1 0 64 64
cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3} 34 34 100.00 1 100 1 0 64 64
cip_base_pkg::resets_cg 4 4 100.00 100.00 1 100 1 1 64 64
dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg 2 2 100.00 100.00 1 100 1 1 64 64
dv_base_reg_pkg::dv_base_shadowed_field_cov::shadow_field_errs_cg 2 2 100.00 100.00 1 100 1 1 64 64
dv_base_reg_pkg::mubi_cov#(4,32'h00000006,32'h00000009)::mubi_cg 6 6 100.00 99.31 1 100 1 1 64 64
dv_lib_pkg::bit_toggle_cg_wrap::bit_toggle_cg 4 4 100.00 100.00 1 100 1 1 64 64
tb.dut.u_reg_wrap.u_reg.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if::prim_onehot_check_without_addr_fault_if_proxy::onehot_without_addr_fault_cg 2 2 100.00 100.00 1 100 1 1 64 64
push_pull_agent_pkg::req_ack_cg 3 3 100.00 100.00 1 100 1 1 64 64
tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=1} 1 1 100.00 100.00 1 100 1 1 64 64
tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128} 137 137 100.00 100.00 1 100 1 1 64 64
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%