Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.22	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	4	40	90.91

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	4	40	90.91	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	184	1			T15	1		T53	1		T56	1
index[0x1]	192	1			T15	1		T42	2		T54	1
index[0x2]	157	1			T33	1		T51	1		T42	3
index[0x3]	170	1			T2	1		T11	1		T53	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	223	1			T11	1		T33	1		T42	1
lens_less_than_1000[1]	133	1			T54	1		T56	1		T147	1
lens_less_than_1000[2]	103	1			T15	1		T51	1		T42	2
lens_less_than_1000[3]	67	1			T15	1		T42	1		T53	1
lens_less_than_1000[4]	58	1			T2	1		T42	1		T54	1
lens_less_than_1000[5]	53	1			T54	1		T280	1		T38	1
lens_less_than_1000[6]	34	1			T149	1		T31	2		T104	1
lens_less_than_1000[7]	17	1			T153	1		T64	1		T281	1
lens_less_than_1000[8]	7	1			T282	1		T283	1		T64	1
lens_less_than_1000[9]	1	1			T284	1		-	-		-	-
len_2	7	1			T90	1		T84	1		T105	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	4	40	90.91	4

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0] , index[0x1]]	[lens_less_than_1000[9]]	--	--	2
[index[0x2]]	[len_2]	0	1	1
[index[0x3]]	[lens_less_than_1000[9]]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	64	1			T53	1		T92	1		T82	1
index[0x0]	lens_less_than_1000[1]	34	1			T56	1		T285	1		T286	1
index[0x0]	lens_less_than_1000[2]	25	1			T15	1		T102	4		T287	1
index[0x0]	lens_less_than_1000[3]	15	1			T88	1		T141	1		T288	1
index[0x0]	lens_less_than_1000[4]	10	1			T90	1		T289	1		T137	1
index[0x0]	lens_less_than_1000[5]	20	1			T39	8		T114	1		T290	1
index[0x0]	lens_less_than_1000[6]	8	1			T31	2		T291	1		T44	2
index[0x0]	lens_less_than_1000[7]	4	1			T153	1		T71	1		T73	1
index[0x0]	lens_less_than_1000[8]	2	1			T64	1		T292	1		-	-
index[0x0]	len_2	2	1			T124	1		T293	1		-	-
index[0x1]	lens_less_than_1000[0]	58	1			T135	1		T294	1		T101	1
index[0x1]	lens_less_than_1000[1]	39	1			T54	1		T82	1		T295	1
index[0x1]	lens_less_than_1000[2]	21	1			T97	2		T102	1		T123	1
index[0x1]	lens_less_than_1000[3]	17	1			T15	1		T42	1		T90	1
index[0x1]	lens_less_than_1000[4]	17	1			T42	1		T85	1		T147	1
index[0x1]	lens_less_than_1000[5]	20	1			T38	1		T153	8		T127	1
index[0x1]	lens_less_than_1000[6]	10	1			T104	1		T296	1		T71	1
index[0x1]	lens_less_than_1000[7]	5	1			T297	1		T298	1		T299	1
index[0x1]	lens_less_than_1000[8]	3	1			T283	1		T298	1		T110	1
index[0x1]	len_2	2	1			T90	1		T84	1		-	-
index[0x2]	lens_less_than_1000[0]	53	1			T33	1		T42	1		T86	2
index[0x2]	lens_less_than_1000[1]	28	1			T100	1		T38	1		T121	2
index[0x2]	lens_less_than_1000[2]	27	1			T51	1		T42	2		T129	1
index[0x2]	lens_less_than_1000[3]	20	1			T53	1		T92	1		T300	1
index[0x2]	lens_less_than_1000[4]	9	1			T54	1		T61	1		T38	1
index[0x2]	lens_less_than_1000[5]	8	1			T54	1		T280	1		T301	1
index[0x2]	lens_less_than_1000[6]	5	1			T71	1		T302	1		T72	1
index[0x2]	lens_less_than_1000[7]	5	1			T64	1		T281	1		T303	1
index[0x2]	lens_less_than_1000[8]	1	1			T282	1		-	-		-	-
index[0x2]	lens_less_than_1000[9]	1	1			T284	1		-	-		-	-
index[0x3]	lens_less_than_1000[0]	48	1			T11	1		T304	1		T305	1
index[0x3]	lens_less_than_1000[1]	32	1			T147	1		T34	1		T306	1
index[0x3]	lens_less_than_1000[2]	30	1			T53	1		T132	1		T307	1
index[0x3]	lens_less_than_1000[3]	15	1			T56	1		T61	1		T137	2
index[0x3]	lens_less_than_1000[4]	22	1			T2	1		T82	1		T153	8
index[0x3]	lens_less_than_1000[5]	5	1			T308	1		T309	1		T310	1
index[0x3]	lens_less_than_1000[6]	11	1			T149	1		T311	2		T71	1
index[0x3]	lens_less_than_1000[7]	3	1			T71	1		T312	1		T313	1
index[0x3]	lens_less_than_1000[8]	1	1			T314	1		-	-		-	-
index[0x3]	len_2	3	1			T105	1		T315	1		T316	1