Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.92	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	3	41	93.18

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	3	41	93.18	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	166	1			T10	1		T15	1		T27	1
index[0x1]	145	1			T15	1		T52	1		T32	1
index[0x2]	165	1			T2	2		T3	5		T138	1
index[0x3]	139	1			T12	1		T50	1		T51	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	192	1			T2	1		T3	5		T15	1
lens_less_than_1000[1]	120	1			T2	1		T12	1		T15	1
lens_less_than_1000[2]	83	1			T141	1		T286	1		T97	1
lens_less_than_1000[3]	70	1			T10	1		T53	1		T42	1
lens_less_than_1000[4]	47	1			T50	1		T32	1		T158	1
lens_less_than_1000[5]	39	1			T287	1		T99	1		T155	2
lens_less_than_1000[6]	36	1			T40	1		T35	2		T288	1
lens_less_than_1000[7]	16	1			T30	2		T289	1		T162	1
lens_less_than_1000[8]	7	1			T255	1		T114	1		T117	1
lens_less_than_1000[9]	1	1			T290	1		-	-		-	-
len_2	4	1			T109	1		T291	1		T270	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	3	41	93.18	3

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0]]	[lens_less_than_1000[9]]	0	1	1
[index[0x2] , index[0x3]]	[lens_less_than_1000[9]]	--	--	2

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	58	1			T15	1		T51	1		T44	1
index[0x0]	lens_less_than_1000[1]	36	1			T27	1		T49	1		T97	1
index[0x0]	lens_less_than_1000[2]	11	1			T162	1		T156	1		T114	1
index[0x0]	lens_less_than_1000[3]	11	1			T10	1		T131	1		T292	1
index[0x0]	lens_less_than_1000[4]	19	1			T158	1		T29	1		T57	1
index[0x0]	lens_less_than_1000[5]	9	1			T99	1		T293	1		T69	1
index[0x0]	lens_less_than_1000[6]	8	1			T35	2		T271	1		T106	1
index[0x0]	lens_less_than_1000[7]	10	1			T162	1		T114	1		T294	1
index[0x0]	lens_less_than_1000[8]	3	1			T255	1		T273	1		T295	1
index[0x0]	len_2	1	1			T109	1		-	-		-	-
index[0x1]	lens_less_than_1000[0]	36	1			T73	1		T56	1		T98	1
index[0x1]	lens_less_than_1000[1]	31	1			T15	1		T52	1		T53	1
index[0x1]	lens_less_than_1000[2]	25	1			T36	1		T58	1		T296	2
index[0x1]	lens_less_than_1000[3]	20	1			T297	1		T102	2		T298	1
index[0x1]	lens_less_than_1000[4]	9	1			T32	1		T299	1		T133	1
index[0x1]	lens_less_than_1000[5]	11	1			T287	1		T59	1		T127	4
index[0x1]	lens_less_than_1000[6]	9	1			T40	1		T272	1		T68	1
index[0x1]	lens_less_than_1000[7]	1	1			T289	1		-	-		-	-
index[0x1]	lens_less_than_1000[8]	1	1			T300	1		-	-		-	-
index[0x1]	lens_less_than_1000[9]	1	1			T290	1		-	-		-	-
index[0x1]	len_2	1	1			T278	1		-	-		-	-
index[0x2]	lens_less_than_1000[0]	55	1			T2	1		T3	5		T138	1
index[0x2]	lens_less_than_1000[1]	30	1			T2	1		T37	6		T59	1
index[0x2]	lens_less_than_1000[2]	23	1			T141	1		T102	1		T36	1
index[0x2]	lens_less_than_1000[3]	20	1			T53	1		T42	1		T301	1
index[0x2]	lens_less_than_1000[4]	10	1			T302	1		T114	1		T105	1
index[0x2]	lens_less_than_1000[5]	7	1			T59	1		T105	1		T303	1
index[0x2]	lens_less_than_1000[6]	15	1			T288	1		T293	1		T304	1
index[0x2]	lens_less_than_1000[7]	3	1			T30	2		T305	1		-	-
index[0x2]	lens_less_than_1000[8]	1	1			T114	1		-	-		-	-
index[0x2]	len_2	1	1			T291	1		-	-		-	-
index[0x3]	lens_less_than_1000[0]	43	1			T51	1		T154	2		T97	1
index[0x3]	lens_less_than_1000[1]	23	1			T12	1		T29	1		T114	1
index[0x3]	lens_less_than_1000[2]	24	1			T286	1		T97	1		T58	1
index[0x3]	lens_less_than_1000[3]	19	1			T94	1		T116	4		T306	1
index[0x3]	lens_less_than_1000[4]	9	1			T50	1		T101	1		T307	1
index[0x3]	lens_less_than_1000[5]	12	1			T155	2		T59	1		T308	1
index[0x3]	lens_less_than_1000[6]	4	1			T69	1		T309	1		T310	1
index[0x3]	lens_less_than_1000[7]	2	1			T269	1		T279	1		-	-
index[0x3]	lens_less_than_1000[8]	2	1			T117	1		T70	1		-	-
index[0x3]	len_2	1	1			T270	1		-	-		-	-