Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	2	38	95.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	2	38	95.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	59	1			T24	1		T88	2		T99	1
class_index[0x1]	75	1			T26	1		T15	1		T86	4
class_index[0x2]	67	1			T14	1		T13	1		T93	1
class_index[0x3]	62	1			T15	1		T56	1		T57	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	111	1			T14	1		T13	1		T24	1
intr_timeout_cnt[1]	56	1			T15	1		T86	4		T57	1
intr_timeout_cnt[2]	31	1			T88	1		T59	1		T38	1
intr_timeout_cnt[3]	17	1			T88	1		T99	1		T100	2
intr_timeout_cnt[4]	16	1			T89	1		T100	1		T124	1
intr_timeout_cnt[5]	7	1			T43	1		T128	1		T317	1
intr_timeout_cnt[6]	7	1			T59	1		T104	1		T124	1
intr_timeout_cnt[7]	6	1			T64	1		T318	1		T319	1
intr_timeout_cnt[8]	5	1			T137	1		T107	1		T320	1
intr_timeout_cnt[9]	7	1			T321	1		T322	1		T215	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	2	38	95.00	2

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[8]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[6]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	30	1			T24	1		T101	1		T102	6
class_index[0x0]	intr_timeout_cnt[1]	7	1			T64	2		T104	1		T67	1
class_index[0x0]	intr_timeout_cnt[2]	10	1			T88	1		T59	1		T38	1
class_index[0x0]	intr_timeout_cnt[3]	3	1			T88	1		T99	1		T100	1
class_index[0x0]	intr_timeout_cnt[4]	4	1			T124	1		T155	1		T302	1
class_index[0x0]	intr_timeout_cnt[5]	1	1			T317	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[6]	2	1			T323	1		T324	1		-	-
class_index[0x0]	intr_timeout_cnt[7]	1	1			T319	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[9]	1	1			T215	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	22	1			T26	1		T98	1		T38	1
class_index[0x1]	intr_timeout_cnt[1]	23	1			T15	1		T86	4		T93	1
class_index[0x1]	intr_timeout_cnt[2]	8	1			T64	1		T213	1		T215	1
class_index[0x1]	intr_timeout_cnt[3]	8	1			T43	1		T310	1		T322	1
class_index[0x1]	intr_timeout_cnt[4]	5	1			T100	1		T140	1		T126	1
class_index[0x1]	intr_timeout_cnt[5]	1	1			T74	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[6]	1	1			T73	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[7]	2	1			T64	1		T325	1		-	-
class_index[0x1]	intr_timeout_cnt[8]	1	1			T107	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[9]	4	1			T321	1		T291	3		-	-
class_index[0x2]	intr_timeout_cnt[0]	37	1			T14	1		T13	1		T93	1
class_index[0x2]	intr_timeout_cnt[1]	14	1			T103	1		T140	1		T155	2
class_index[0x2]	intr_timeout_cnt[2]	2	1			T64	1		T225	1		-	-
class_index[0x2]	intr_timeout_cnt[3]	3	1			T155	1		T71	1		T298	1
class_index[0x2]	intr_timeout_cnt[4]	3	1			T89	1		T140	1		T72	1
class_index[0x2]	intr_timeout_cnt[5]	3	1			T128	1		T298	1		T326	1
class_index[0x2]	intr_timeout_cnt[7]	2	1			T225	2		-	-		-	-
class_index[0x2]	intr_timeout_cnt[8]	2	1			T137	1		T225	1		-	-
class_index[0x2]	intr_timeout_cnt[9]	1	1			T322	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	22	1			T15	1		T56	1		T103	1
class_index[0x3]	intr_timeout_cnt[1]	12	1			T57	1		T89	1		T98	1
class_index[0x3]	intr_timeout_cnt[2]	11	1			T64	2		T140	1		T71	1
class_index[0x3]	intr_timeout_cnt[3]	3	1			T100	1		T137	1		T327	1
class_index[0x3]	intr_timeout_cnt[4]	4	1			T328	1		T329	1		T247	1
class_index[0x3]	intr_timeout_cnt[5]	2	1			T43	1		T74	1		-	-
class_index[0x3]	intr_timeout_cnt[6]	4	1			T59	1		T104	1		T124	1
class_index[0x3]	intr_timeout_cnt[7]	1	1			T318	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[8]	2	1			T320	1		T330	1		-	-
class_index[0x3]	intr_timeout_cnt[9]	1	1			T225	1		-	-		-	-