Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
85.19	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	8	32	80.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	8	32	80.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	67	1			T27	1		T76	1		T54	1
class_index[0x1]	54	1			T13	1		T26	1		T89	1
class_index[0x2]	45	1			T88	1		T89	1		T95	1
class_index[0x3]	42	1			T27	1		T79	1		T44	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	78	1			T27	2		T76	1		T79	1
intr_timeout_cnt[1]	49	1			T13	1		T88	1		T89	2
intr_timeout_cnt[2]	8	1			T136	1		T117	1		T109	2
intr_timeout_cnt[3]	21	1			T26	1		T54	1		T33	3
intr_timeout_cnt[4]	7	1			T36	1		T120	1		T267	2
intr_timeout_cnt[5]	12	1			T54	1		T83	1		T97	1
intr_timeout_cnt[6]	17	1			T30	1		T103	1		T60	1
intr_timeout_cnt[7]	7	1			T118	2		T117	1		T268	1
intr_timeout_cnt[8]	3	1			T33	1		T102	1		T269	1
intr_timeout_cnt[9]	6	1			T104	4		T270	2		-	-

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	8	32	80.00	8

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[8] , intr_timeout_cnt[9]]	--	--	2
[class_index[0x1]]	[intr_timeout_cnt[4]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[8] , intr_timeout_cnt[9]]	--	--	2
[class_index[0x3]]	[intr_timeout_cnt[4]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[7] , intr_timeout_cnt[8]]	--	--	2

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	27	1			T27	1		T76	1		T97	1
class_index[0x0]	intr_timeout_cnt[1]	14	1			T96	1		T271	1		T272	2
class_index[0x0]	intr_timeout_cnt[2]	2	1			T136	1		T273	1		-	-
class_index[0x0]	intr_timeout_cnt[3]	9	1			T54	1		T33	3		T149	1
class_index[0x0]	intr_timeout_cnt[4]	3	1			T36	1		T120	1		T274	1
class_index[0x0]	intr_timeout_cnt[5]	2	1			T97	1		T275	1		-	-
class_index[0x0]	intr_timeout_cnt[6]	7	1			T30	1		T103	1		T67	2
class_index[0x0]	intr_timeout_cnt[7]	3	1			T117	1		T276	1		T269	1
class_index[0x1]	intr_timeout_cnt[0]	24	1			T95	1		T101	1		T277	1
class_index[0x1]	intr_timeout_cnt[1]	10	1			T13	1		T89	1		T111	1
class_index[0x1]	intr_timeout_cnt[2]	1	1			T109	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[3]	4	1			T26	1		T117	1		T270	1
class_index[0x1]	intr_timeout_cnt[5]	3	1			T54	1		T83	1		T278	1
class_index[0x1]	intr_timeout_cnt[6]	3	1			T256	3		-	-		-	-
class_index[0x1]	intr_timeout_cnt[7]	2	1			T118	1		T268	1		-	-
class_index[0x1]	intr_timeout_cnt[8]	3	1			T33	1		T102	1		T269	1
class_index[0x1]	intr_timeout_cnt[9]	4	1			T104	4		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	14	1			T95	1		T136	1		T62	1
class_index[0x2]	intr_timeout_cnt[1]	10	1			T88	1		T89	1		T97	1
class_index[0x2]	intr_timeout_cnt[2]	3	1			T279	1		T270	1		T280	1
class_index[0x2]	intr_timeout_cnt[3]	2	1			T30	1		T270	1		-	-
class_index[0x2]	intr_timeout_cnt[4]	4	1			T267	2		T125	2		-	-
class_index[0x2]	intr_timeout_cnt[5]	5	1			T98	1		T36	1		T120	1
class_index[0x2]	intr_timeout_cnt[6]	5	1			T281	1		T269	4		-	-
class_index[0x2]	intr_timeout_cnt[7]	2	1			T118	1		T274	1		-	-
class_index[0x3]	intr_timeout_cnt[0]	13	1			T27	1		T79	1		T44	1
class_index[0x3]	intr_timeout_cnt[1]	15	1			T83	1		T91	1		T58	1
class_index[0x3]	intr_timeout_cnt[2]	2	1			T117	1		T109	1		-	-
class_index[0x3]	intr_timeout_cnt[3]	6	1			T67	1		T282	1		T269	3
class_index[0x3]	intr_timeout_cnt[5]	2	1			T155	1		T283	1		-	-
class_index[0x3]	intr_timeout_cnt[6]	2	1			T60	1		T256	1		-	-
class_index[0x3]	intr_timeout_cnt[9]	2	1			T270	2		-	-		-	-