Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	341405	1			T2	5		T11	19		T12	12
all_values[1]	341405	1			T2	5		T11	19		T12	12
all_values[2]	341405	1			T2	5		T11	19		T12	12
all_values[3]	341405	1			T2	5		T11	19		T12	12

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

678729

1

T2

2

T11

44

T12

28

auto[1]

686891

1

T2

18

T11

32

T12

20

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

825582

1

T2

12

T11

67

T12

28

auto[1]

540038

1

T2

8

T11

9

T12

20

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	97337	1			T11	5		T12	3		T32	5
all_values[0]	auto[0]	auto[1]	71954	1			T11	4		T12	3		T32	4
all_values[0]	auto[1]	auto[0]	99387	1			T2	3		T11	5		T12	4
all_values[0]	auto[1]	auto[1]	72727	1			T2	2		T11	5		T12	2
all_values[1]	auto[0]	auto[0]	103856	1			T2	1		T11	10		T12	2
all_values[1]	auto[0]	auto[1]	66375	1			T2	1		T12	2		T14	8
all_values[1]	auto[1]	auto[0]	104920	1			T2	2		T11	9		T12	5
all_values[1]	auto[1]	auto[1]	66254	1			T2	1		T12	3		T14	4
all_values[2]	auto[0]	auto[0]	104496	1			T11	13		T12	6		T32	9
all_values[2]	auto[0]	auto[1]	65152	1			T12	4		T14	8		T13	2
all_values[2]	auto[1]	auto[0]	106463	1			T2	3		T11	6		T12	1
all_values[2]	auto[1]	auto[1]	65294	1			T2	2		T12	1		T14	3
all_values[3]	auto[0]	auto[0]	103474	1			T11	12		T12	5		T32	6
all_values[3]	auto[0]	auto[1]	66085	1			T12	3		T14	7		T13	2
all_values[3]	auto[1]	auto[0]	105649	1			T2	3		T11	7		T12	2
all_values[3]	auto[1]	auto[1]	66197	1			T2	2		T12	2		T14	5