Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	296361	1			T2	35		T3	19		T10	41
all_values[1]	296361	1			T2	35		T3	19		T10	41
all_values[2]	296361	1			T2	35		T3	19		T10	41
all_values[3]	296361	1			T2	35		T3	19		T10	41

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

589499

1

T2

63

T3

39

T10

62

auto[1]

595945

1

T2

77

T3

37

T10

102

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

703728

1

T2

74

T3

43

T10

160

auto[1]

481716

1

T2

66

T3

33

T10

4

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	86175	1			T2	10		T3	4		T10	13
all_values[0]	auto[0]	auto[1]	61305	1			T2	7		T3	4		T10	3
all_values[0]	auto[1]	auto[0]	87484	1			T2	10		T3	6		T10	24
all_values[0]	auto[1]	auto[1]	61397	1			T2	8		T3	5		T10	1
all_values[1]	auto[0]	auto[0]	88390	1			T2	9		T3	7		T10	19
all_values[1]	auto[0]	auto[1]	58845	1			T2	9		T3	6		T13	4
all_values[1]	auto[1]	auto[0]	89988	1			T2	9		T3	3		T10	22
all_values[1]	auto[1]	auto[1]	59138	1			T2	8		T3	3		T13	8
all_values[2]	auto[0]	auto[0]	86242	1			T2	8		T3	5		T10	15
all_values[2]	auto[0]	auto[1]	60955	1			T2	8		T3	3		T13	7
all_values[2]	auto[1]	auto[0]	88254	1			T2	10		T3	6		T10	26
all_values[2]	auto[1]	auto[1]	60910	1			T2	9		T3	5		T13	5
all_values[3]	auto[0]	auto[0]	88106	1			T2	6		T3	6		T10	12
all_values[3]	auto[0]	auto[1]	59481	1			T2	6		T3	4		T13	6
all_values[3]	auto[1]	auto[0]	89089	1			T2	12		T3	6		T10	29
all_values[3]	auto[1]	auto[1]	59685	1			T2	11		T3	3		T13	6