Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	341405	1			T2	5		T11	19		T12	12
all_pins[1]	341405	1			T2	5		T11	19		T12	12
all_pins[2]	341405	1			T2	5		T11	19		T12	12
all_pins[3]	341405	1			T2	5		T11	19		T12	12

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1095148	1			T2	13		T11	71		T12	40
values[0x1]	270472	1			T2	7		T11	5		T12	8
transitions[0x0=>0x1]	180478	1			T2	2		T11	4		T12	5
transitions[0x1=>0x0]	180745	1			T2	3		T11	5		T12	6

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	268678	1			T2	3		T11	14		T12	10
all_pins[0]	values[0x1]	72727	1			T2	2		T11	5		T12	2
all_pins[0]	transitions[0x0=>0x1]	72033	1			T2	1		T11	4		T12	1
all_pins[0]	transitions[0x1=>0x0]	65770	1			T2	2		T12	2		T14	5
all_pins[1]	values[0x0]	275151	1			T2	4		T11	19		T12	9
all_pins[1]	values[0x1]	66254	1			T2	1		T12	3		T14	4
all_pins[1]	transitions[0x0=>0x1]	36152	1			T12	2		T14	1		T33	5
all_pins[1]	transitions[0x1=>0x0]	42625	1			T2	1		T11	5		T12	1
all_pins[2]	values[0x0]	276111	1			T2	3		T11	19		T12	11
all_pins[2]	values[0x1]	65294	1			T2	2		T12	1		T14	3
all_pins[2]	transitions[0x0=>0x1]	35735	1			T2	1		T12	1		T14	3
all_pins[2]	transitions[0x1=>0x0]	36695	1			T12	3		T14	4		T13	2
all_pins[3]	values[0x0]	275208	1			T2	3		T11	19		T12	10
all_pins[3]	values[0x1]	66197	1			T2	2		T12	2		T14	5
all_pins[3]	transitions[0x0=>0x1]	36558	1			T12	1		T14	5		T13	1
all_pins[3]	transitions[0x1=>0x0]	35655	1			T14	3		T13	3		T33	3