Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	296361	1			T2	35		T3	19		T10	41
all_pins[1]	296361	1			T2	35		T3	19		T10	41
all_pins[2]	296361	1			T2	35		T3	19		T10	41
all_pins[3]	296361	1			T2	35		T3	19		T10	41

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	944314	1			T2	104		T3	60		T10	163
values[0x1]	241130	1			T2	36		T3	16		T10	1
transitions[0x0=>0x1]	160012	1			T2	19		T3	12		T10	1
transitions[0x1=>0x0]	160279	1			T2	20		T3	12		T10	1

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	234964	1			T2	27		T3	14		T10	40
all_pins[0]	values[0x1]	61397	1			T2	8		T3	5		T10	1
all_pins[0]	transitions[0x0=>0x1]	60882	1			T2	7		T3	5		T10	1
all_pins[0]	transitions[0x1=>0x0]	59437	1			T2	11		T3	3		T13	6
all_pins[1]	values[0x0]	237223	1			T2	27		T3	16		T10	41
all_pins[1]	values[0x1]	59138	1			T2	8		T3	3		T13	8
all_pins[1]	transitions[0x0=>0x1]	32434	1			T2	4		T3	2		T13	4
all_pins[1]	transitions[0x1=>0x0]	34693	1			T2	4		T3	4		T10	1
all_pins[2]	values[0x0]	235451	1			T2	26		T3	14		T10	41
all_pins[2]	values[0x1]	60910	1			T2	9		T3	5		T13	5
all_pins[2]	transitions[0x0=>0x1]	34164	1			T2	4		T3	4		T13	2
all_pins[2]	transitions[0x1=>0x0]	32392	1			T2	3		T3	2		T13	5
all_pins[3]	values[0x0]	236676	1			T2	24		T3	16		T10	41
all_pins[3]	values[0x1]	59685	1			T2	11		T3	3		T13	6
all_pins[3]	transitions[0x0=>0x1]	32532	1			T2	4		T3	1		T13	3
all_pins[3]	transitions[0x1=>0x0]	33757	1			T2	2		T3	3		T13	2