Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	284	1			T220	4		T221	7		T376	4
all_values[1]	284	1			T220	4		T221	7		T376	4
all_values[2]	284	1			T220	4		T221	7		T376	4
all_values[3]	284	1			T220	4		T221	7		T376	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

617

1

T220

4

T221

11

T376

9

auto[1]

519

1

T220

12

T221

17

T376

7

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

445

1

T220

10

T221

13

T376

16

auto[1]

691

1

T220

6

T221

15

T377

14

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

673

1

T220

11

T221

18

T376

16

auto[1]

463

1

T220

5

T221

10

T377

12

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

51

1

T220

1

T221

2

T376

2

all_values[0]

auto[0]

auto[0]

auto[1]

30

1

T220

1

T378

1

T379

1

all_values[0]

auto[0]

auto[1]

auto[0]

41

1

T220

1

T221

1

T376

2

all_values[0]

auto[0]

auto[1]

auto[1]

31

1

T221

1

T380

1

T381

1

all_values[0]

auto[1]

auto[0]

auto[1]

71

1

T377

1

T378

4

T379

3

all_values[0]

auto[1]

auto[1]

auto[1]

60

1

T220

1

T221

3

T377

3

all_values[1]

auto[0]

auto[0]

auto[0]

64

1

T221

1

T376

1

T377

3

all_values[1]

auto[0]

auto[0]

auto[1]

20

1

T221

1

T379

1

T382

1

all_values[1]

auto[0]

auto[1]

auto[0]

49

1

T220

3

T221

2

T376

3

all_values[1]

auto[0]

auto[1]

auto[1]

28

1

T377

1

T378

1

T383

1

all_values[1]

auto[1]

auto[0]

auto[1]

69

1

T221

2

T377

2

T383

3

all_values[1]

auto[1]

auto[1]

auto[1]

54

1

T220

1

T221

1

T377

1

all_values[2]

auto[0]

auto[0]

auto[0]

74

1

T220

2

T221

1

T376

4

all_values[2]

auto[0]

auto[0]

auto[1]

34

1

T221

1

T377

1

T381

2

all_values[2]

auto[0]

auto[1]

auto[0]

51

1

T220

1

T221

3

T377

3

all_values[2]

auto[0]

auto[1]

auto[1]

20

1

T378

1

T379

2

T383

2

all_values[2]

auto[1]

auto[0]

auto[1]

57

1

T221

1

T377

1

T378

2

all_values[2]

auto[1]

auto[1]

auto[1]

48

1

T220

1

T221

1

T378

1

all_values[3]

auto[0]

auto[0]

auto[0]

58

1

T221

1

T376

2

T377

2

all_values[3]

auto[0]

auto[0]

auto[1]

33

1

T221

1

T378

1

T384

4

all_values[3]

auto[0]

auto[1]

auto[0]

57

1

T220

2

T221

2

T376

2

all_values[3]

auto[0]

auto[1]

auto[1]

32

1

T221

1

T378

2

T379

1

all_values[3]

auto[1]

auto[0]

auto[1]

56

1

T377

3

T378

2

T380

1

all_values[3]

auto[1]

auto[1]

auto[1]

48

1

T220

2

T221

2

T377

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal