Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	284	1			T192	7		T194	7		T263	4
all_values[1]	284	1			T192	7		T194	7		T263	4
all_values[2]	284	1			T192	7		T194	7		T263	4
all_values[3]	284	1			T192	7		T194	7		T263	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

636

1

T192

16

T194

16

T263

10

auto[1]

500

1

T192

12

T194

12

T263

6

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

452

1

T192

9

T194

9

T263

6

auto[1]

684

1

T192

19

T194

19

T263

10

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

680

1

T192

17

T194

15

T263

10

auto[1]

456

1

T192

11

T194

13

T263

6

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

59

1

T192

2

T194

1

T263

1

all_values[0]

auto[0]

auto[0]

auto[1]

34

1

T192

1

T263

1

T388

1

all_values[0]

auto[0]

auto[1]

auto[0]

42

1

T194

2

T389

1

T388

2

all_values[0]

auto[0]

auto[1]

auto[1]

25

1

T192

1

T194

1

T390

2

all_values[0]

auto[1]

auto[0]

auto[1]

67

1

T192

1

T263

1

T389

1

all_values[0]

auto[1]

auto[1]

auto[1]

57

1

T192

2

T194

3

T263

1

all_values[1]

auto[0]

auto[0]

auto[0]

71

1

T192

4

T194

1

T263

1

all_values[1]

auto[0]

auto[0]

auto[1]

29

1

T192

2

T194

1

T263

1

all_values[1]

auto[0]

auto[1]

auto[0]

58

1

T389

6

T388

1

T390

1

all_values[1]

auto[0]

auto[1]

auto[1]

31

1

T194

2

T388

1

T391

1

all_values[1]

auto[1]

auto[0]

auto[1]

55

1

T194

3

T263

2

T388

2

all_values[1]

auto[1]

auto[1]

auto[1]

40

1

T192

1

T389

1

T388

3

all_values[2]

auto[0]

auto[0]

auto[0]

60

1

T192

2

T194

2

T389

1

all_values[2]

auto[0]

auto[0]

auto[1]

25

1

T389

1

T390

1

T392

2

all_values[2]

auto[0]

auto[1]

auto[0]

52

1

T194

2

T263

1

T389

2

all_values[2]

auto[0]

auto[1]

auto[1]

28

1

T192

2

T194

1

T263

2

all_values[2]

auto[1]

auto[0]

auto[1]

60

1

T192

2

T194

1

T389

2

all_values[2]

auto[1]

auto[1]

auto[1]

59

1

T192

1

T194

1

T263

1

all_values[3]

auto[0]

auto[0]

auto[0]

74

1

T194

1

T263

2

T389

4

all_values[3]

auto[0]

auto[0]

auto[1]

32

1

T192

1

T194

1

T388

1

all_values[3]

auto[0]

auto[1]

auto[0]

36

1

T192

1

T263

1

T392

2

all_values[3]

auto[0]

auto[1]

auto[1]

24

1

T192

1

T388

1

T390

1

all_values[3]

auto[1]

auto[0]

auto[1]

70

1

T192

1

T194

5

T263

1

all_values[3]

auto[1]

auto[1]

auto[1]

48

1

T192

3

T388

1

T390

2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal