Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	82937	1			T139	336		T82	374		T61	951
accum_cnt_1000	222707	1			T13	9		T42	15		T57	19
accum_cnt_100	24201	1			T57	2		T45	9		T336	16
accum_cnt_50	62770	1			T11	6		T32	10		T14	10
accum_cnt_10	162841	1			T2	2		T11	4		T12	17
accum_cnt_0	413440	1			T2	6		T11	34		T12	23

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	252087	1			T2	2		T11	11		T12	10
class_index[0x1]	252087	1			T2	2		T11	11		T12	10
class_index[0x2]	252087	1			T2	2		T11	11		T12	10
class_index[0x3]	252087	1			T2	2		T11	11		T12	10

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	25484	1			T82	47		T61	169		T265	571
class_index[0x0]	accum_cnt_1000	61122	1			T13	9		T57	12		T31	10
class_index[0x0]	accum_cnt_100	7749	1			T45	9		T31	11		T58	14
class_index[0x0]	accum_cnt_50	16032	1			T11	6		T32	10		T33	12
class_index[0x0]	accum_cnt_10	45094	1			T11	4		T12	1		T32	2
class_index[0x0]	accum_cnt_0	82735	1			T2	2		T11	1		T12	9
class_index[0x1]	accum_cnt_2000	17590	1			T139	336		T82	65		T61	348
class_index[0x1]	accum_cnt_1000	50013	1			T89	23		T147	50		T135	23
class_index[0x1]	accum_cnt_100	5244	1			T336	16		T147	21		T135	12
class_index[0x1]	accum_cnt_50	18003	1			T13	1		T33	8		T26	22
class_index[0x1]	accum_cnt_10	39723	1			T2	1		T12	8		T14	22
class_index[0x1]	accum_cnt_0	112806	1			T2	1		T11	11		T12	2
class_index[0x2]	accum_cnt_2000	19867	1			T61	198		T218	120		T283	501
class_index[0x2]	accum_cnt_1000	57479	1			T42	15		T147	44		T304	46
class_index[0x2]	accum_cnt_100	5464	1			T93	2		T337	3		T89	20
class_index[0x2]	accum_cnt_50	15424	1			T14	10		T13	3		T33	7
class_index[0x2]	accum_cnt_10	40801	1			T2	1		T12	6		T14	14
class_index[0x2]	accum_cnt_0	104143	1			T2	1		T11	11		T12	4
class_index[0x3]	accum_cnt_2000	19996	1			T82	262		T61	236		T265	664
class_index[0x3]	accum_cnt_1000	54093	1			T57	7		T88	2		T147	54
class_index[0x3]	accum_cnt_100	5744	1			T57	2		T147	19		T97	1
class_index[0x3]	accum_cnt_50	13311	1			T15	6		T42	13		T54	11
class_index[0x3]	accum_cnt_10	37223	1			T12	2		T14	4		T13	9
class_index[0x3]	accum_cnt_0	113756	1			T2	2		T11	11		T12	8