Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	83394	1			T154	235		T318	40		T319	274
accum_cnt_1000	184930	1			T50	1		T320	40		T164	31
accum_cnt_100	19620	1			T12	5		T50	28		T40	6
accum_cnt_50	52803	1			T2	13		T3	2		T12	14
accum_cnt_10	170688	1			T2	29		T3	14		T10	31
accum_cnt_0	326721	1			T2	54		T3	32		T10	93

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	219726	1			T2	24		T3	12		T10	31
class_index[0x1]	219726	1			T2	24		T3	12		T10	31
class_index[0x2]	219726	1			T2	24		T3	12		T10	31
class_index[0x3]	219726	1			T2	24		T3	12		T10	31

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	19163	1			T319	274		T86	62		T254	213
class_index[0x0]	accum_cnt_1000	47640	1			T320	33		T94	43		T85	26
class_index[0x0]	accum_cnt_100	5150	1			T12	5		T50	12		T90	8
class_index[0x0]	accum_cnt_50	15091	1			T3	2		T12	14		T13	20
class_index[0x0]	accum_cnt_10	39682	1			T3	9		T10	31		T12	4
class_index[0x0]	accum_cnt_0	84550	1			T2	24		T3	1		T17	6
class_index[0x1]	accum_cnt_2000	23486	1			T86	57		T253	355		T293	73
class_index[0x1]	accum_cnt_1000	47527	1			T165	7		T250	1		T251	14
class_index[0x1]	accum_cnt_100	5047	1			T40	6		T165	16		T97	12
class_index[0x1]	accum_cnt_50	11536	1			T2	13		T50	24		T32	6
class_index[0x1]	accum_cnt_10	37546	1			T2	11		T13	24		T15	21
class_index[0x1]	accum_cnt_0	84141	1			T3	12		T10	31		T12	23
class_index[0x2]	accum_cnt_2000	20077	1			T321	287		T296	438		T60	234
class_index[0x2]	accum_cnt_1000	48364	1			T50	1		T320	7		T286	11
class_index[0x2]	accum_cnt_100	5107	1			T50	16		T301	5		T320	21
class_index[0x2]	accum_cnt_50	14439	1			T88	6		T50	12		T89	12
class_index[0x2]	accum_cnt_10	44212	1			T2	2		T3	5		T26	7
class_index[0x2]	accum_cnt_0	78895	1			T2	22		T3	7		T10	31
class_index[0x3]	accum_cnt_2000	20668	1			T154	235		T318	40		T253	111
class_index[0x3]	accum_cnt_1000	41399	1			T164	31		T154	206		T318	500
class_index[0x3]	accum_cnt_100	4316	1			T44	4		T164	26		T33	3
class_index[0x3]	accum_cnt_50	11737	1			T15	14		T27	6		T32	9
class_index[0x3]	accum_cnt_10	49248	1			T2	16		T13	1		T15	6
class_index[0x3]	accum_cnt_0	79135	1			T2	8		T3	12		T10	31