Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	4424	1			T18	1		T20	1		T289	1
alert[0x1]	5780	1			T252	8		T254	157		T60	45
alert[0x2]	3468	1			T265	1		T322	1		T38	1
alert[0x3]	3483	1			T323	1		T324	1		T36	247
alert[0x4]	1669	1			T38	1		T324	1		T254	15
alert[0x5]	14870	1			T44	2		T325	1		T323	1
alert[0x6]	2440	1			T265	1		T252	1		T289	1
alert[0x7]	8137	1			T26	1		T325	1		T326	1
alert[0x8]	12517	1			T44	1		T38	1		T289	1
alert[0x9]	6638	1			T20	1		T44	5		T266	2
alert[0xa]	5264	1			T96	6		T323	1		T324	1
alert[0xb]	5336	1			T325	1		T103	10		T327	1
alert[0xc]	8023	1			T323	1		T254	143		T321	1
alert[0xd]	3199	1			T44	8		T328	1		T324	1
alert[0xe]	2915	1			T33	2		T266	1		T322	2
alert[0xf]	2347	1			T98	1		T329	1		T255	18
alert[0x10]	2552	1			T266	1		T328	1		T38	1
alert[0x11]	3781	1			T323	1		T329	1		T255	45
alert[0x12]	6652	1			T54	1		T328	1		T325	1
alert[0x13]	8893	1			T96	6		T265	1		T323	1
alert[0x14]	10401	1			T328	1		T325	1		T254	235
alert[0x15]	1548	1			T265	1		T328	1		T322	1
alert[0x16]	3454	1			T19	2		T328	1		T325	1
alert[0x17]	5287	1			T289	1		T329	1		T255	39
alert[0x18]	1946	1			T44	58		T98	5		T36	229
alert[0x19]	7278	1			T20	1		T44	2		T266	1
alert[0x1a]	2600	1			T33	1		T328	1		T252	9
alert[0x1b]	9657	1			T44	45		T325	1		T38	1
alert[0x1c]	7114	1			T324	1		T254	496		T255	120
alert[0x1d]	6954	1			T96	1		T328	1		T326	1
alert[0x1e]	3344	1			T250	1		T325	1		T289	1
alert[0x1f]	7301	1			T96	16		T44	10		T266	1
alert[0x20]	4605	1			T97	3		T329	1		T254	8
alert[0x21]	3909	1			T44	2		T266	1		T328	1
alert[0x22]	5306	1			T266	2		T324	1		T36	55
alert[0x23]	5698	1			T266	2		T324	1		T252	3
alert[0x24]	2169	1			T18	1		T265	1		T328	1
alert[0x25]	7655	1			T44	11		T328	1		T323	1
alert[0x26]	8929	1			T44	1		T329	1		T254	24
alert[0x27]	9738	1			T44	1		T36	482		T255	26
alert[0x28]	1529	1			T54	2		T328	1		T251	1
alert[0x29]	9362	1			T18	2		T266	1		T254	265
alert[0x2a]	1711	1			T38	1		T324	1		T289	1
alert[0x2b]	3843	1			T325	1		T98	1		T322	1
alert[0x2c]	2603	1			T44	1		T289	1		T254	33
alert[0x2d]	4478	1			T20	1		T44	16		T266	1
alert[0x2e]	4449	1			T44	19		T323	3		T38	1
alert[0x2f]	3171	1			T44	1		T323	1		T322	1
alert[0x30]	4193	1			T158	7		T323	1		T322	1
alert[0x31]	3570	1			T36	141		T296	155		T304	1
alert[0x32]	5407	1			T44	5		T38	1		T330	1
alert[0x33]	5058	1			T19	1		T289	1		T36	141
alert[0x34]	3436	1			T328	2		T323	1		T324	1
alert[0x35]	3020	1			T328	1		T324	1		T329	1
alert[0x36]	4281	1			T33	2		T250	5		T326	1
alert[0x37]	2673	1			T266	1		T325	1		T324	1
alert[0x38]	2951	1			T158	6		T323	1		T322	1
alert[0x39]	13294	1			T323	1		T38	1		T103	1
alert[0x3a]	3089	1			T265	1		T44	1		T33	3
alert[0x3b]	4267	1			T19	1		T322	2		T254	1
alert[0x3c]	1406	1			T19	1		T44	1		T324	1
alert[0x3d]	3950	1			T44	2		T323	1		T322	3
alert[0x3e]	4190	1			T265	2		T328	1		T324	1
alert[0x3f]	15611	1			T266	1		T97	3		T322	1
alert[0x40]	4829	1			T44	3		T38	1		T36	184

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	40943	1			T19	2		T96	23		T20	3
class_i[0x1]	97223	1			T158	13		T18	1		T54	3
class_i[0x2]	125520	1			T26	1		T18	1		T19	1
class_i[0x3]	79966	1			T18	2		T19	1		T96	6

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

343018

1

T26

1

T158

13

T54

3

alert_ping_fail

634

1

T18

4

T19

5

T20

4

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	4419	1			T36	6		T296	25		T104	7
alert_integrity_fail	alert[0x1]	5777	1			T252	8		T254	157		T60	45
alert_integrity_fail	alert[0x2]	3456	1			T252	100		T36	42		T255	320
alert_integrity_fail	alert[0x3]	3478	1			T36	247		T255	11		T58	4
alert_integrity_fail	alert[0x4]	1663	1			T254	15		T255	491		T104	29
alert_integrity_fail	alert[0x5]	14856	1			T44	2		T254	15		T36	110
alert_integrity_fail	alert[0x6]	2426	1			T252	1		T254	77		T255	1003
alert_integrity_fail	alert[0x7]	8124	1			T26	1		T252	8		T36	219
alert_integrity_fail	alert[0x8]	12501	1			T44	1		T254	2352		T255	420
alert_integrity_fail	alert[0x9]	6626	1			T44	5		T251	12		T330	1
alert_integrity_fail	alert[0xa]	5258	1			T96	6		T36	60		T58	2
alert_integrity_fail	alert[0xb]	5333	1			T103	10		T58	5		T299	101
alert_integrity_fail	alert[0xc]	8014	1			T254	143		T321	1		T296	47
alert_integrity_fail	alert[0xd]	3189	1			T44	8		T255	349		T321	4
alert_integrity_fail	alert[0xe]	2904	1			T33	2		T254	41		T58	1553
alert_integrity_fail	alert[0xf]	2338	1			T98	1		T255	18		T331	19
alert_integrity_fail	alert[0x10]	2543	1			T254	460		T255	87		T331	82
alert_integrity_fail	alert[0x11]	3775	1			T255	45		T321	4		T296	236
alert_integrity_fail	alert[0x12]	6634	1			T54	1		T254	46		T255	226
alert_integrity_fail	alert[0x13]	8883	1			T96	6		T98	1		T254	11
alert_integrity_fail	alert[0x14]	10386	1			T254	235		T36	5123		T255	90
alert_integrity_fail	alert[0x15]	1539	1			T252	7		T102	5		T36	10
alert_integrity_fail	alert[0x16]	3445	1			T103	9		T36	31		T296	4
alert_integrity_fail	alert[0x17]	5279	1			T255	39		T331	86		T299	12
alert_integrity_fail	alert[0x18]	1935	1			T44	58		T98	5		T36	229
alert_integrity_fail	alert[0x19]	7270	1			T44	2		T251	6		T98	1
alert_integrity_fail	alert[0x1a]	2589	1			T33	1		T252	9		T36	17
alert_integrity_fail	alert[0x1b]	9649	1			T44	45		T36	15		T302	11
alert_integrity_fail	alert[0x1c]	7100	1			T254	496		T255	120		T58	479
alert_integrity_fail	alert[0x1d]	6940	1			T96	1		T254	61		T36	1449
alert_integrity_fail	alert[0x1e]	3336	1			T250	1		T254	9		T36	249
alert_integrity_fail	alert[0x1f]	7290	1			T96	16		T44	10		T97	2
alert_integrity_fail	alert[0x20]	4596	1			T97	3		T254	8		T255	11
alert_integrity_fail	alert[0x21]	3901	1			T44	2		T255	32		T331	46
alert_integrity_fail	alert[0x22]	5300	1			T36	55		T255	328		T57	26
alert_integrity_fail	alert[0x23]	5687	1			T252	3		T103	19		T36	1159
alert_integrity_fail	alert[0x24]	2163	1			T254	47		T36	34		T58	4
alert_integrity_fail	alert[0x25]	7649	1			T44	11		T254	5		T255	65
alert_integrity_fail	alert[0x26]	8924	1			T44	1		T254	24		T36	803
alert_integrity_fail	alert[0x27]	9731	1			T44	1		T36	482		T255	26
alert_integrity_fail	alert[0x28]	1517	1			T54	2		T251	1		T331	105
alert_integrity_fail	alert[0x29]	9358	1			T254	265		T103	8		T36	20
alert_integrity_fail	alert[0x2a]	1692	1			T103	2		T255	23		T331	30
alert_integrity_fail	alert[0x2b]	3827	1			T98	1		T36	102		T104	21
alert_integrity_fail	alert[0x2c]	2594	1			T44	1		T254	33		T102	2
alert_integrity_fail	alert[0x2d]	4465	1			T44	16		T255	87		T331	178
alert_integrity_fail	alert[0x2e]	4435	1			T44	19		T254	121		T103	2
alert_integrity_fail	alert[0x2f]	3152	1			T44	1		T36	37		T331	20
alert_integrity_fail	alert[0x30]	4182	1			T158	7		T254	282		T36	435
alert_integrity_fail	alert[0x31]	3563	1			T36	141		T296	155		T104	15
alert_integrity_fail	alert[0x32]	5400	1			T44	5		T330	1		T331	302
alert_integrity_fail	alert[0x33]	5051	1			T36	141		T255	21		T302	2
alert_integrity_fail	alert[0x34]	3424	1			T254	503		T36	106		T296	3
alert_integrity_fail	alert[0x35]	3012	1			T254	517		T58	264		T331	44
alert_integrity_fail	alert[0x36]	4270	1			T33	2		T250	5		T330	3
alert_integrity_fail	alert[0x37]	2665	1			T254	14		T36	61		T255	84
alert_integrity_fail	alert[0x38]	2938	1			T158	6		T254	2		T36	32
alert_integrity_fail	alert[0x39]	13289	1			T103	1		T36	4913		T255	597
alert_integrity_fail	alert[0x3a]	3084	1			T44	1		T33	3		T255	102
alert_integrity_fail	alert[0x3b]	4257	1			T254	1		T255	213		T306	2
alert_integrity_fail	alert[0x3c]	1399	1			T44	1		T103	1		T104	1
alert_integrity_fail	alert[0x3d]	3938	1			T44	2		T255	16		T58	1
alert_integrity_fail	alert[0x3e]	4177	1			T254	30		T103	1		T255	47
alert_integrity_fail	alert[0x3f]	15600	1			T97	3		T103	3		T255	1
alert_integrity_fail	alert[0x40]	4823	1			T44	3		T36	184		T296	92
alert_ping_fail	alert[0x0]	5	1			T18	1		T20	1		T289	1
alert_ping_fail	alert[0x1]	3	1			T332	1		T333	1		T334	1
alert_ping_fail	alert[0x2]	12	1			T265	1		T322	1		T38	1
alert_ping_fail	alert[0x3]	5	1			T323	1		T324	1		T143	1
alert_ping_fail	alert[0x4]	6	1			T38	1		T324	1		T335	1
alert_ping_fail	alert[0x5]	14	1			T325	1		T323	1		T322	1
alert_ping_fail	alert[0x6]	14	1			T265	1		T289	1		T336	1
alert_ping_fail	alert[0x7]	13	1			T325	1		T326	1		T304	1
alert_ping_fail	alert[0x8]	16	1			T38	1		T289	1		T304	1
alert_ping_fail	alert[0x9]	12	1			T20	1		T266	2		T328	1
alert_ping_fail	alert[0xa]	6	1			T323	1		T324	1		T337	1
alert_ping_fail	alert[0xb]	3	1			T325	1		T327	1		T338	1
alert_ping_fail	alert[0xc]	9	1			T323	1		T339	1		T340	1
alert_ping_fail	alert[0xd]	10	1			T328	1		T324	1		T329	1
alert_ping_fail	alert[0xe]	11	1			T266	1		T322	2		T38	1
alert_ping_fail	alert[0xf]	9	1			T329	1		T336	1		T304	1
alert_ping_fail	alert[0x10]	9	1			T266	1		T328	1		T38	1
alert_ping_fail	alert[0x11]	6	1			T323	1		T329	1		T339	1
alert_ping_fail	alert[0x12]	18	1			T328	1		T325	1		T326	1
alert_ping_fail	alert[0x13]	10	1			T265	1		T323	1		T327	1
alert_ping_fail	alert[0x14]	15	1			T328	1		T325	1		T304	1
alert_ping_fail	alert[0x15]	9	1			T265	1		T328	1		T322	1
alert_ping_fail	alert[0x16]	9	1			T19	2		T328	1		T325	1
alert_ping_fail	alert[0x17]	8	1			T289	1		T329	1		T337	1
alert_ping_fail	alert[0x18]	11	1			T304	2		T341	1		T342	1
alert_ping_fail	alert[0x19]	8	1			T20	1		T266	1		T335	1
alert_ping_fail	alert[0x1a]	11	1			T328	1		T289	1		T327	1
alert_ping_fail	alert[0x1b]	8	1			T325	1		T38	1		T327	1
alert_ping_fail	alert[0x1c]	14	1			T324	1		T336	1		T316	1
alert_ping_fail	alert[0x1d]	14	1			T328	1		T326	1		T324	1
alert_ping_fail	alert[0x1e]	8	1			T325	1		T289	1		T329	1
alert_ping_fail	alert[0x1f]	11	1			T266	1		T289	1		T336	1
alert_ping_fail	alert[0x20]	9	1			T329	1		T327	1		T144	2
alert_ping_fail	alert[0x21]	8	1			T266	1		T328	1		T131	1
alert_ping_fail	alert[0x22]	6	1			T266	2		T324	1		T343	1
alert_ping_fail	alert[0x23]	11	1			T266	2		T324	1		T289	2
alert_ping_fail	alert[0x24]	6	1			T18	1		T265	1		T328	1
alert_ping_fail	alert[0x25]	6	1			T328	1		T323	1		T327	1
alert_ping_fail	alert[0x26]	5	1			T329	1		T344	1		T345	1
alert_ping_fail	alert[0x27]	7	1			T346	1		T347	1		T341	1
alert_ping_fail	alert[0x28]	12	1			T328	1		T38	1		T289	1
alert_ping_fail	alert[0x29]	4	1			T18	2		T266	1		T348	1
alert_ping_fail	alert[0x2a]	19	1			T38	1		T324	1		T289	1
alert_ping_fail	alert[0x2b]	16	1			T325	1		T322	1		T336	1
alert_ping_fail	alert[0x2c]	9	1			T289	1		T327	1		T346	1
alert_ping_fail	alert[0x2d]	13	1			T20	1		T266	1		T324	1
alert_ping_fail	alert[0x2e]	14	1			T323	3		T38	1		T327	1
alert_ping_fail	alert[0x2f]	19	1			T323	1		T322	1		T329	1
alert_ping_fail	alert[0x30]	11	1			T323	1		T322	1		T324	1
alert_ping_fail	alert[0x31]	7	1			T304	1		T349	1		T344	1
alert_ping_fail	alert[0x32]	7	1			T38	1		T336	1		T346	1
alert_ping_fail	alert[0x33]	7	1			T19	1		T289	1		T347	1
alert_ping_fail	alert[0x34]	12	1			T328	2		T323	1		T324	1
alert_ping_fail	alert[0x35]	8	1			T328	1		T324	1		T329	1
alert_ping_fail	alert[0x36]	11	1			T326	1		T336	1		T304	2
alert_ping_fail	alert[0x37]	8	1			T266	1		T325	1		T324	1
alert_ping_fail	alert[0x38]	13	1			T323	1		T322	1		T38	1
alert_ping_fail	alert[0x39]	5	1			T323	1		T38	1		T350	1
alert_ping_fail	alert[0x3a]	5	1			T265	1		T349	1		T351	1
alert_ping_fail	alert[0x3b]	10	1			T19	1		T322	2		T304	2
alert_ping_fail	alert[0x3c]	7	1			T19	1		T324	1		T336	2
alert_ping_fail	alert[0x3d]	12	1			T323	1		T322	3		T337	1
alert_ping_fail	alert[0x3e]	13	1			T265	2		T328	1		T324	1
alert_ping_fail	alert[0x3f]	11	1			T266	1		T322	1		T329	1
alert_ping_fail	alert[0x40]	6	1			T38	1		T352	1		T344	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	40758	1			T96	23		T251	12		T302	28
alert_integrity_fail	class_i[0x1]	97070	1			T158	13		T54	3		T254	9671
alert_integrity_fail	class_i[0x2]	125368	1			T26	1		T44	13		T33	8
alert_integrity_fail	class_i[0x3]	79822	1			T96	6		T44	182		T97	8
alert_ping_fail	class_i[0x0]	185	1			T19	2		T20	3		T328	2
alert_ping_fail	class_i[0x1]	153	1			T18	1		T19	1		T266	15
alert_ping_fail	class_i[0x2]	152	1			T18	1		T19	1		T328	1
alert_ping_fail	class_i[0x3]	144	1			T18	2		T19	1		T20	1