Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	3760	1			T88	1		T16	2		T18	1
alert[0x1]	2301	1			T18	1		T139	12		T339	1
alert[0x2]	6793	1			T13	1		T16	1		T340	1
alert[0x3]	4315	1			T57	15		T16	1		T340	1
alert[0x4]	6092	1			T130	1		T341	1		T139	25
alert[0x5]	2202	1			T13	5		T82	45		T138	8
alert[0x6]	4291	1			T340	1		T101	1		T61	2
alert[0x7]	4086	1			T131	1		T139	61		T82	82
alert[0x8]	7544	1			T16	1		T139	1348		T82	321
alert[0x9]	4691	1			T13	1		T42	2		T57	1
alert[0xa]	1932	1			T139	83		T307	1		T141	250
alert[0xb]	8077	1			T51	3		T340	1		T139	9
alert[0xc]	5267	1			T16	1		T218	49		T342	1
alert[0xd]	4334	1			T13	1		T57	3		T16	1
alert[0xe]	5831	1			T286	1		T139	11		T82	505
alert[0xf]	16509	1			T42	5		T130	1		T82	4711
alert[0x10]	8100	1			T149	2		T97	1		T131	1
alert[0x11]	7007	1			T13	5		T57	1		T18	1
alert[0x12]	2517	1			T57	1		T149	17		T341	1
alert[0x13]	6807	1			T42	5		T57	124		T130	1
alert[0x14]	7258	1			T88	2		T18	1		T340	1
alert[0x15]	3073	1			T18	1		T131	1		T139	56
alert[0x16]	8100	1			T17	1		T340	1		T82	2077
alert[0x17]	13803	1			T130	1		T264	15		T139	49
alert[0x18]	4203	1			T18	1		T264	1		T139	10
alert[0x19]	3538	1			T16	1		T343	1		T79	1
alert[0x1a]	3577	1			T57	20		T36	1		T286	1
alert[0x1b]	8900	1			T13	2		T17	2		T131	1
alert[0x1c]	9719	1			T344	1		T341	1		T286	2
alert[0x1d]	16036	1			T286	1		T139	59		T82	12
alert[0x1e]	3035	1			T42	10		T18	1		T340	1
alert[0x1f]	6507	1			T344	1		T101	1		T82	369
alert[0x20]	3397	1			T18	1		T139	29		T82	59
alert[0x21]	4185	1			T139	247		T61	18		T335	2
alert[0x22]	8029	1			T344	2		T343	1		T79	1
alert[0x23]	3564	1			T57	1		T16	1		T18	1
alert[0x24]	4396	1			T17	1		T286	1		T82	31
alert[0x25]	2732	1			T149	6		T17	1		T130	1
alert[0x26]	3728	1			T42	1		T57	22		T16	1
alert[0x27]	4756	1			T344	2		T139	233		T79	1
alert[0x28]	3893	1			T131	1		T36	1		T343	1
alert[0x29]	7745	1			T57	2		T340	1		T286	1
alert[0x2a]	7313	1			T27	13		T131	1		T101	10
alert[0x2b]	10701	1			T57	1		T18	1		T139	68
alert[0x2c]	5024	1			T88	2		T18	1		T130	1
alert[0x2d]	9409	1			T13	6		T17	1		T18	1
alert[0x2e]	4326	1			T307	100		T339	1		T345	1
alert[0x2f]	6634	1			T343	1		T101	38		T139	90
alert[0x30]	6865	1			T16	2		T286	2		T139	57
alert[0x31]	5785	1			T131	1		T340	1		T61	1
alert[0x32]	940	1			T82	47		T307	1		T265	2
alert[0x33]	3965	1			T344	1		T339	1		T276	2
alert[0x34]	1953	1			T18	1		T131	1		T286	1
alert[0x35]	5046	1			T343	1		T286	1		T139	36
alert[0x36]	16305	1			T130	1		T286	1		T139	1382
alert[0x37]	5616	1			T130	1		T131	2		T340	1
alert[0x38]	3162	1			T97	2		T130	1		T344	1
alert[0x39]	9025	1			T27	4		T57	8		T130	1
alert[0x3a]	4759	1			T13	4		T27	3		T57	63
alert[0x3b]	5103	1			T57	1		T82	25		T61	1
alert[0x3c]	8055	1			T149	2		T131	2		T61	71
alert[0x3d]	6590	1			T340	1		T139	133		T79	1
alert[0x3e]	3610	1			T18	1		T130	1		T82	34
alert[0x3f]	9125	1			T18	1		T43	1		T345	4
alert[0x40]	6919	1			T57	2		T88	11		T344	1

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	77289	1			T13	1		T27	6		T51	3
class_i[0x1]	137755	1			T27	3		T88	3		T149	17
class_i[0x2]	87378	1			T13	24		T57	32		T149	6
class_i[0x3]	90438	1			T27	11		T42	1		T57	233

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

392157

1

T13

25

T27

20

T51

3

alert_ping_fail

703

1

T16

13

T17

6

T18

15

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	3750	1			T88	1		T139	32		T82	7
alert_integrity_fail	alert[0x1]	2291	1			T139	12		T141	204		T318	5
alert_integrity_fail	alert[0x2]	6789	1			T13	1		T139	9		T61	2
alert_integrity_fail	alert[0x3]	4305	1			T57	15		T101	71		T139	83
alert_integrity_fail	alert[0x4]	6082	1			T139	25		T307	3		T38	1
alert_integrity_fail	alert[0x5]	2189	1			T13	5		T82	45		T138	8
alert_integrity_fail	alert[0x6]	4284	1			T101	1		T61	2		T265	2
alert_integrity_fail	alert[0x7]	4079	1			T139	61		T82	82		T218	153
alert_integrity_fail	alert[0x8]	7527	1			T139	1348		T82	321		T138	2
alert_integrity_fail	alert[0x9]	4684	1			T13	1		T42	2		T57	1
alert_integrity_fail	alert[0xa]	1920	1			T139	83		T307	1		T141	250
alert_integrity_fail	alert[0xb]	8073	1			T51	3		T139	9		T82	321
alert_integrity_fail	alert[0xc]	5258	1			T218	49		T342	1		T346	4
alert_integrity_fail	alert[0xd]	4322	1			T13	1		T57	3		T139	13
alert_integrity_fail	alert[0xe]	5819	1			T139	11		T82	505		T138	16
alert_integrity_fail	alert[0xf]	16502	1			T42	5		T82	4711		T141	3
alert_integrity_fail	alert[0x10]	8096	1			T149	2		T97	1		T101	5
alert_integrity_fail	alert[0x11]	6992	1			T13	5		T57	1		T61	10
alert_integrity_fail	alert[0x12]	2507	1			T57	1		T149	17		T139	418
alert_integrity_fail	alert[0x13]	6794	1			T42	5		T57	124		T218	36
alert_integrity_fail	alert[0x14]	7242	1			T88	2		T139	72		T82	185
alert_integrity_fail	alert[0x15]	3057	1			T139	56		T138	58		T68	59
alert_integrity_fail	alert[0x16]	8086	1			T82	2077		T307	13		T141	12
alert_integrity_fail	alert[0x17]	13795	1			T264	15		T139	49		T82	76
alert_integrity_fail	alert[0x18]	4198	1			T264	1		T139	10		T82	3
alert_integrity_fail	alert[0x19]	3531	1			T82	365		T218	31		T65	889
alert_integrity_fail	alert[0x1a]	3565	1			T57	20		T101	2		T139	74
alert_integrity_fail	alert[0x1b]	8888	1			T13	2		T139	147		T61	1
alert_integrity_fail	alert[0x1c]	9708	1			T139	37		T61	1		T138	71
alert_integrity_fail	alert[0x1d]	16024	1			T139	59		T82	12		T38	27
alert_integrity_fail	alert[0x1e]	3019	1			T42	10		T139	27		T59	5
alert_integrity_fail	alert[0x1f]	6488	1			T101	1		T82	369		T61	18
alert_integrity_fail	alert[0x20]	3387	1			T139	29		T82	59		T141	328
alert_integrity_fail	alert[0x21]	4171	1			T139	247		T61	18		T138	43
alert_integrity_fail	alert[0x22]	8009	1			T82	2840		T265	1		T138	4
alert_integrity_fail	alert[0x23]	3555	1			T57	1		T101	1		T307	4
alert_integrity_fail	alert[0x24]	4381	1			T82	31		T61	13		T38	17
alert_integrity_fail	alert[0x25]	2718	1			T149	6		T139	392		T141	10
alert_integrity_fail	alert[0x26]	3721	1			T42	1		T57	22		T139	3
alert_integrity_fail	alert[0x27]	4749	1			T139	233		T265	1		T138	24
alert_integrity_fail	alert[0x28]	3881	1			T141	74		T342	2		T347	6
alert_integrity_fail	alert[0x29]	7736	1			T57	2		T139	28		T82	65
alert_integrity_fail	alert[0x2a]	7302	1			T27	13		T101	10		T139	46
alert_integrity_fail	alert[0x2b]	10694	1			T57	1		T139	68		T61	2
alert_integrity_fail	alert[0x2c]	5005	1			T88	2		T139	1265		T82	62
alert_integrity_fail	alert[0x2d]	9393	1			T13	6		T82	3597		T307	6
alert_integrity_fail	alert[0x2e]	4320	1			T307	100		T345	1		T153	5
alert_integrity_fail	alert[0x2f]	6626	1			T101	38		T139	90		T307	15
alert_integrity_fail	alert[0x30]	6851	1			T139	57		T82	18		T141	4
alert_integrity_fail	alert[0x31]	5774	1			T61	1		T122	5		T103	18
alert_integrity_fail	alert[0x32]	931	1			T82	47		T307	1		T265	2
alert_integrity_fail	alert[0x33]	3955	1			T318	6		T123	24		T140	1
alert_integrity_fail	alert[0x34]	1937	1			T139	23		T82	6		T103	5
alert_integrity_fail	alert[0x35]	5039	1			T139	36		T345	2		T65	470
alert_integrity_fail	alert[0x36]	16295	1			T139	1382		T82	249		T138	1695
alert_integrity_fail	alert[0x37]	5592	1			T139	43		T82	8		T265	2
alert_integrity_fail	alert[0x38]	3155	1			T97	2		T307	4		T138	223
alert_integrity_fail	alert[0x39]	9016	1			T27	4		T57	8		T139	2
alert_integrity_fail	alert[0x3a]	4751	1			T13	4		T27	3		T57	63
alert_integrity_fail	alert[0x3b]	5092	1			T57	1		T82	25		T61	1
alert_integrity_fail	alert[0x3c]	8042	1			T149	2		T61	71		T141	10
alert_integrity_fail	alert[0x3d]	6579	1			T139	133		T82	132		T61	1
alert_integrity_fail	alert[0x3e]	3602	1			T82	34		T61	2		T138	231
alert_integrity_fail	alert[0x3f]	9120	1			T43	1		T345	4		T103	81
alert_integrity_fail	alert[0x40]	6914	1			T57	2		T88	11		T264	1
alert_ping_fail	alert[0x0]	10	1			T16	2		T18	1		T343	1
alert_ping_fail	alert[0x1]	10	1			T18	1		T339	1		T276	1
alert_ping_fail	alert[0x2]	4	1			T16	1		T340	1		T348	1
alert_ping_fail	alert[0x3]	10	1			T16	1		T340	1		T113	1
alert_ping_fail	alert[0x4]	10	1			T130	1		T341	1		T276	1
alert_ping_fail	alert[0x5]	13	1			T270	1		T334	1		T349	1
alert_ping_fail	alert[0x6]	7	1			T340	1		T350	1		T351	1
alert_ping_fail	alert[0x7]	7	1			T131	1		T352	1		T353	1
alert_ping_fail	alert[0x8]	17	1			T16	1		T354	1		T355	2
alert_ping_fail	alert[0x9]	7	1			T344	1		T286	1		T348	1
alert_ping_fail	alert[0xa]	12	1			T356	2		T357	1		T358	1
alert_ping_fail	alert[0xb]	4	1			T340	1		T308	1		T359	1
alert_ping_fail	alert[0xc]	9	1			T16	1		T290	1		T360	1
alert_ping_fail	alert[0xd]	12	1			T16	1		T344	1		T339	1
alert_ping_fail	alert[0xe]	12	1			T286	1		T339	1		T350	1
alert_ping_fail	alert[0xf]	7	1			T130	1		T350	1		T358	1
alert_ping_fail	alert[0x10]	4	1			T131	1		T286	1		T361	1
alert_ping_fail	alert[0x11]	15	1			T18	1		T341	1		T286	2
alert_ping_fail	alert[0x12]	10	1			T341	1		T343	1		T339	1
alert_ping_fail	alert[0x13]	13	1			T130	1		T113	1		T290	1
alert_ping_fail	alert[0x14]	16	1			T18	1		T340	1		T36	1
alert_ping_fail	alert[0x15]	16	1			T18	1		T131	1		T332	1
alert_ping_fail	alert[0x16]	14	1			T17	1		T340	1		T270	1
alert_ping_fail	alert[0x17]	8	1			T130	1		T349	1		T360	2
alert_ping_fail	alert[0x18]	5	1			T18	1		T276	1		T357	1
alert_ping_fail	alert[0x19]	7	1			T16	1		T343	1		T79	1
alert_ping_fail	alert[0x1a]	12	1			T36	1		T286	1		T339	1
alert_ping_fail	alert[0x1b]	12	1			T17	2		T131	1		T362	1
alert_ping_fail	alert[0x1c]	11	1			T344	1		T341	1		T286	2
alert_ping_fail	alert[0x1d]	12	1			T286	1		T276	1		T352	1
alert_ping_fail	alert[0x1e]	16	1			T18	1		T340	1		T36	1
alert_ping_fail	alert[0x1f]	19	1			T344	1		T362	1		T352	1
alert_ping_fail	alert[0x20]	10	1			T18	1		T335	1		T339	1
alert_ping_fail	alert[0x21]	14	1			T335	2		T270	1		T276	1
alert_ping_fail	alert[0x22]	20	1			T344	2		T343	1		T79	1
alert_ping_fail	alert[0x23]	9	1			T16	1		T18	1		T131	1
alert_ping_fail	alert[0x24]	15	1			T17	1		T286	1		T362	1
alert_ping_fail	alert[0x25]	14	1			T17	1		T130	1		T131	1
alert_ping_fail	alert[0x26]	7	1			T16	1		T113	1		T358	2
alert_ping_fail	alert[0x27]	7	1			T344	2		T79	1		T352	1
alert_ping_fail	alert[0x28]	12	1			T131	1		T36	1		T343	1
alert_ping_fail	alert[0x29]	9	1			T340	1		T286	1		T79	1
alert_ping_fail	alert[0x2a]	11	1			T131	1		T331	1		T276	1
alert_ping_fail	alert[0x2b]	7	1			T18	1		T308	1		T363	1
alert_ping_fail	alert[0x2c]	19	1			T18	1		T130	1		T340	1
alert_ping_fail	alert[0x2d]	16	1			T17	1		T18	1		T344	1
alert_ping_fail	alert[0x2e]	6	1			T339	1		T349	1		T360	1
alert_ping_fail	alert[0x2f]	8	1			T343	1		T276	1		T349	1
alert_ping_fail	alert[0x30]	14	1			T16	2		T286	2		T349	1
alert_ping_fail	alert[0x31]	11	1			T131	1		T340	1		T339	1
alert_ping_fail	alert[0x32]	9	1			T270	1		T276	2		T351	1
alert_ping_fail	alert[0x33]	10	1			T344	1		T339	1		T276	2
alert_ping_fail	alert[0x34]	16	1			T18	1		T131	1		T286	1
alert_ping_fail	alert[0x35]	7	1			T343	1		T286	1		T270	2
alert_ping_fail	alert[0x36]	10	1			T130	1		T286	1		T349	2
alert_ping_fail	alert[0x37]	24	1			T130	1		T131	2		T340	1
alert_ping_fail	alert[0x38]	7	1			T130	1		T344	1		T362	1
alert_ping_fail	alert[0x39]	9	1			T130	1		T344	1		T343	1
alert_ping_fail	alert[0x3a]	8	1			T16	1		T308	1		T364	1
alert_ping_fail	alert[0x3b]	11	1			T290	2		T364	1		T348	1
alert_ping_fail	alert[0x3c]	13	1			T131	2		T349	1		T350	1
alert_ping_fail	alert[0x3d]	11	1			T340	1		T79	1		T339	1
alert_ping_fail	alert[0x3e]	8	1			T18	1		T130	1		T351	1
alert_ping_fail	alert[0x3f]	5	1			T18	1		T270	1		T350	1
alert_ping_fail	alert[0x40]	5	1			T344	1		T352	1		T357	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	77182	1			T13	1		T27	6		T51	3
alert_integrity_fail	class_i[0x1]	137567	1			T27	3		T88	3		T149	17
alert_integrity_fail	class_i[0x2]	87146	1			T13	24		T57	32		T149	6
alert_integrity_fail	class_i[0x3]	90262	1			T27	11		T42	1		T57	233
alert_ping_fail	class_i[0x0]	107	1			T344	12		T341	2		T340	11
alert_ping_fail	class_i[0x1]	188	1			T16	1		T18	15		T344	1
alert_ping_fail	class_i[0x2]	232	1			T16	12		T17	6		T340	1
alert_ping_fail	class_i[0x3]	176	1			T130	11		T131	14		T341	2