Unified Coverage Report :: Cond split page

Go back

 LINE       176
 EXPRESSION (reg2hw.alert_en_shadowed[27].q & ((~reg2hw.alert_regwen[27].q)))
             ---------------1--------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T1,T4,T14
1	1	Covered	T4,T11,T7

 LINE       176
 EXPRESSION (reg2hw.alert_en_shadowed[28].q & ((~reg2hw.alert_regwen[28].q)))
             ---------------1--------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T12
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T15

 LINE       176
 EXPRESSION (reg2hw.alert_en_shadowed[29].q & ((~reg2hw.alert_regwen[29].q)))
             ---------------1--------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T13
1	0	Covered	T1,T3,T4
1	1	Covered	T3,T4,T12

 LINE       176
 EXPRESSION (reg2hw.alert_en_shadowed[30].q & ((~reg2hw.alert_regwen[30].q)))
             ---------------1--------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T12
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T15

 LINE       176
 EXPRESSION (reg2hw.alert_en_shadowed[31].q & ((~reg2hw.alert_regwen[31].q)))
             ---------------1--------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T17
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T12

 LINE       176
 EXPRESSION (reg2hw.alert_en_shadowed[32].q & ((~reg2hw.alert_regwen[32].q)))
             ---------------1--------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T17
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T12

 LINE       176
 EXPRESSION (reg2hw.alert_en_shadowed[33].q & ((~reg2hw.alert_regwen[33].q)))
             ---------------1--------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T15,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       176
 EXPRESSION (reg2hw.alert_en_shadowed[34].q & ((~reg2hw.alert_regwen[34].q)))
             ---------------1--------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       176
 EXPRESSION (reg2hw.alert_en_shadowed[35].q & ((~reg2hw.alert_regwen[35].q)))
             ---------------1--------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T1,T2,T4
1	1	Covered	T4,T13,T7

 LINE       176
 EXPRESSION (reg2hw.alert_en_shadowed[36].q & ((~reg2hw.alert_regwen[36].q)))
             ---------------1--------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T12,T15

 LINE       176
 EXPRESSION (reg2hw.alert_en_shadowed[37].q & ((~reg2hw.alert_regwen[37].q)))
             ---------------1--------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T7

 LINE       176
 EXPRESSION (reg2hw.alert_en_shadowed[38].q & ((~reg2hw.alert_regwen[38].q)))
             ---------------1--------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T15

 LINE       176
 EXPRESSION (reg2hw.alert_en_shadowed[39].q & ((~reg2hw.alert_regwen[39].q)))
             ---------------1--------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T15

 LINE       176
 EXPRESSION (reg2hw.alert_en_shadowed[40].q & ((~reg2hw.alert_regwen[40].q)))
             ---------------1--------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       176
 EXPRESSION (reg2hw.alert_en_shadowed[41].q & ((~reg2hw.alert_regwen[41].q)))
             ---------------1--------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T17,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       176
 EXPRESSION (reg2hw.alert_en_shadowed[42].q & ((~reg2hw.alert_regwen[42].q)))
             ---------------1--------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T12

 LINE       176
 EXPRESSION (reg2hw.alert_en_shadowed[43].q & ((~reg2hw.alert_regwen[43].q)))
             ---------------1--------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T1,T4,T12
1	1	Covered	T4,T13,T26

 LINE       176
 EXPRESSION (reg2hw.alert_en_shadowed[44].q & ((~reg2hw.alert_regwen[44].q)))
             ---------------1--------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T43,T48
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T12

 LINE       176
 EXPRESSION (reg2hw.alert_en_shadowed[45].q & ((~reg2hw.alert_regwen[45].q)))
             ---------------1--------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T13,T15

 LINE       176
 EXPRESSION (reg2hw.alert_en_shadowed[46].q & ((~reg2hw.alert_regwen[46].q)))
             ---------------1--------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T17,T43
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       176
 EXPRESSION (reg2hw.alert_en_shadowed[47].q & ((~reg2hw.alert_regwen[47].q)))
             ---------------1--------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       176
 EXPRESSION (reg2hw.alert_en_shadowed[48].q & ((~reg2hw.alert_regwen[48].q)))
             ---------------1--------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T12,T27

 LINE       176
 EXPRESSION (reg2hw.alert_en_shadowed[49].q & ((~reg2hw.alert_regwen[49].q)))
             ---------------1--------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T12
1	0	Covered	T1,T3,T4
1	1	Covered	T3,T4,T13

 LINE       176
 EXPRESSION (reg2hw.alert_en_shadowed[50].q & ((~reg2hw.alert_regwen[50].q)))
             ---------------1--------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T12
1	0	Covered	T1,T3,T4
1	1	Covered	T3,T4,T13

 LINE       176
 EXPRESSION (reg2hw.alert_en_shadowed[51].q & ((~reg2hw.alert_regwen[51].q)))
             ---------------1--------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T12

 LINE       176
 EXPRESSION (reg2hw.alert_en_shadowed[52].q & ((~reg2hw.alert_regwen[52].q)))
             ---------------1--------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T13
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T12

 LINE       176
 EXPRESSION (reg2hw.alert_en_shadowed[53].q & ((~reg2hw.alert_regwen[53].q)))
             ---------------1--------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T13

 LINE       176
 EXPRESSION (reg2hw.alert_en_shadowed[54].q & ((~reg2hw.alert_regwen[54].q)))
             ---------------1--------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T12,T13

 LINE       176
 EXPRESSION (reg2hw.alert_en_shadowed[55].q & ((~reg2hw.alert_regwen[55].q)))
             ---------------1--------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T17
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T12

 LINE       176
 EXPRESSION (reg2hw.alert_en_shadowed[56].q & ((~reg2hw.alert_regwen[56].q)))
             ---------------1--------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       176
 EXPRESSION (reg2hw.alert_en_shadowed[57].q & ((~reg2hw.alert_regwen[57].q)))
             ---------------1--------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T12
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T15

 LINE       176
 EXPRESSION (reg2hw.alert_en_shadowed[58].q & ((~reg2hw.alert_regwen[58].q)))
             ---------------1--------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T13

 LINE       176
 EXPRESSION (reg2hw.alert_en_shadowed[59].q & ((~reg2hw.alert_regwen[59].q)))
             ---------------1--------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       176
 EXPRESSION (reg2hw.alert_en_shadowed[60].q & ((~reg2hw.alert_regwen[60].q)))
             ---------------1--------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T12
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T13

 LINE       176
 EXPRESSION (reg2hw.alert_en_shadowed[61].q & ((~reg2hw.alert_regwen[61].q)))
             ---------------1--------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T15

 LINE       176
 EXPRESSION (reg2hw.alert_en_shadowed[62].q & ((~reg2hw.alert_regwen[62].q)))
             ---------------1--------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T13,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T12

 LINE       176
 EXPRESSION (reg2hw.alert_en_shadowed[63].q & ((~reg2hw.alert_regwen[63].q)))
             ---------------1--------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T27
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T12

 LINE       176
 EXPRESSION (reg2hw.alert_en_shadowed[64].q & ((~reg2hw.alert_regwen[64].q)))
             ---------------1--------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T17
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T12

 LINE       193
 SUB-EXPRESSION 
 Number  Term
      1  reg2hw.classd_ctrl_shadowed.en.q & 
      2  (reg2hw.classd_ctrl_shadowed.en_e3.q | reg2hw.classd_ctrl_shadowed.en_e2.q | reg2hw.classd_ctrl_shadowed.en_e1.q | reg2hw.classd_ctrl_shadowed.en_e0.q))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T18
1	1	Covered	T1,T2,T13

 LINE       193
 SUB-EXPRESSION 
 Number  Term
      1  reg2hw.classd_ctrl_shadowed.en_e3.q | 
      2  reg2hw.classd_ctrl_shadowed.en_e2.q | 
      3  reg2hw.classd_ctrl_shadowed.en_e1.q | 
      4  reg2hw.classd_ctrl_shadowed.en_e0.q)

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T2,T3,T4
0	0	0	1	Covered	T2,T13,T15
0	0	1	0	Covered	T13,T17,T15
0	1	0	0	Covered	T2,T15,T31
1	0	0	0	Covered	T2,T10,T15

 LINE       193
 SUB-EXPRESSION 
 Number  Term
      1  reg2hw.classc_ctrl_shadowed.en.q & 
      2  (reg2hw.classc_ctrl_shadowed.en_e3.q | reg2hw.classc_ctrl_shadowed.en_e2.q | reg2hw.classc_ctrl_shadowed.en_e1.q | reg2hw.classc_ctrl_shadowed.en_e0.q))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T49,T52,T138
1	1	Covered	T1,T2,T3

 LINE       193
 SUB-EXPRESSION 
 Number  Term
      1  reg2hw.classc_ctrl_shadowed.en_e3.q | 
      2  reg2hw.classc_ctrl_shadowed.en_e2.q | 
      3  reg2hw.classc_ctrl_shadowed.en_e1.q | 
      4  reg2hw.classc_ctrl_shadowed.en_e0.q)

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T31,T49,T52
0	0	0	1	Covered	T10,T12,T15
0	0	1	0	Covered	T2,T10,T15
0	1	0	0	Covered	T10,T17,T48
1	0	0	0	Covered	T10,T51,T52

 LINE       193
 SUB-EXPRESSION 
 Number  Term
      1  reg2hw.classb_ctrl_shadowed.en.q & 
      2  (reg2hw.classb_ctrl_shadowed.en_e3.q | reg2hw.classb_ctrl_shadowed.en_e2.q | reg2hw.classb_ctrl_shadowed.en_e1.q | reg2hw.classb_ctrl_shadowed.en_e0.q))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T53,T55,T44
1	1	Covered	T1,T2,T4

 LINE       193
 SUB-EXPRESSION 
 Number  Term
      1  reg2hw.classb_ctrl_shadowed.en_e3.q | 
      2  reg2hw.classb_ctrl_shadowed.en_e2.q | 
      3  reg2hw.classb_ctrl_shadowed.en_e1.q | 
      4  reg2hw.classb_ctrl_shadowed.en_e0.q)

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T12,T13,T31
0	0	0	1	Covered	T4,T12,T15
0	0	1	0	Covered	T2,T15,T43
0	1	0	0	Covered	T15,T27,T43
1	0	0	0	Covered	T2,T10,T26

 LINE       193
 SUB-EXPRESSION 
 Number  Term
      1  reg2hw.classa_ctrl_shadowed.en.q & 
      2  (reg2hw.classa_ctrl_shadowed.en_e3.q | reg2hw.classa_ctrl_shadowed.en_e2.q | reg2hw.classa_ctrl_shadowed.en_e1.q | reg2hw.classa_ctrl_shadowed.en_e0.q))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T43,T34
1	1	Covered	T1,T3,T4

 LINE       193
 SUB-EXPRESSION 
 Number  Term
      1  reg2hw.classa_ctrl_shadowed.en_e3.q | 
      2  reg2hw.classa_ctrl_shadowed.en_e2.q | 
      3  reg2hw.classa_ctrl_shadowed.en_e1.q | 
      4  reg2hw.classa_ctrl_shadowed.en_e0.q)

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T10,T27,T43
0	0	0	1	Covered	T2,T10,T50
0	0	1	0	Covered	T17,T27,T43
0	1	0	0	Covered	T52,T138,T141
1	0	0	0	Covered	T43,T31,T49

 LINE       273
 SUB-EXPRESSION (reg2hw.classd_clr_shadowed.q & reg2hw.classd_clr_shadowed.qe)
                 --------------1-------------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T167,T169,T174
1	0	Covered	T2,T3,T10
1	1	Covered	T2,T3,T10

 LINE       273
 SUB-EXPRESSION (reg2hw.classc_clr_shadowed.q & reg2hw.classc_clr_shadowed.qe)
                 --------------1-------------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T167,T168,T170
1	0	Covered	T2,T3,T12
1	1	Covered	T2,T3,T12

 LINE       273
 SUB-EXPRESSION (reg2hw.classb_clr_shadowed.q & reg2hw.classb_clr_shadowed.qe)
                 --------------1-------------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T169,T170,T236
1	0	Covered	T3,T10,T12
1	1	Covered	T3,T10,T12

 LINE       273
 SUB-EXPRESSION (reg2hw.classa_clr_shadowed.q & reg2hw.classa_clr_shadowed.qe)
                 --------------1-------------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T167,T170,T236
1	0	Covered	T3,T17,T11
1	1	Covered	T3,T17,T11

 LINE       350
 EXPRESSION (((|latch_crashdump_i)) && ((!(|crashdump_latched_q))))
             -----------1----------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T10
1	1	Covered	T1,T2,T3

 LINE       358
 EXPRESSION (((|crashdump_latched_q)) ? crashdump_q : crashdump_d)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3