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 LINE       17382
 EXPRESSION (addr_hit[305] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Covered	T38,T103,T155
1	1	1	Covered	T2,T11,T12

 LINE       17385
 EXPRESSION (addr_hit[306] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Not Covered
1	1	1	Covered	T2,T11,T12

 LINE       17386
 EXPRESSION (addr_hit[307] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Covered	T195
1	1	1	Covered	T2,T11,T12

 LINE       17387
 EXPRESSION (addr_hit[308] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Covered	T38,T103,T155
1	1	1	Covered	T2,T11,T12

 LINE       17390
 EXPRESSION (addr_hit[309] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T38,T103,T155

 LINE       17391
 EXPRESSION (addr_hit[309] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T38,T103,T155
1	1	1	Covered	T1,T2,T3

 LINE       17412
 EXPRESSION (addr_hit[310] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Covered	T38,T103,T155
1	1	1	Covered	T2,T11,T12

 LINE       17415
 EXPRESSION (addr_hit[311] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Covered	T201
1	1	1	Covered	T38,T103,T155

 LINE       17416
 EXPRESSION (addr_hit[311] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Covered	T38,T103,T155
1	1	1	Covered	T2,T11,T12

 LINE       17419
 EXPRESSION (addr_hit[312] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       17420
 EXPRESSION (addr_hit[313] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T38,T103,T155

 LINE       17421
 EXPRESSION (addr_hit[313] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T38,T103,T155
1	1	1	Covered	T1,T2,T3

 LINE       17424
 EXPRESSION (addr_hit[314] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T11,T12,T32
1	1	0	Covered	T197
1	1	1	Covered	T38,T103,T155

 LINE       17425
 EXPRESSION (addr_hit[314] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T11,T12,T32
1	1	0	Covered	T38,T103,T155
1	1	1	Covered	T11,T12,T32

 LINE       17428
 EXPRESSION (addr_hit[315] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Not Covered
1	1	1	Covered	T38,T103,T155

 LINE       17429
 EXPRESSION (addr_hit[315] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Covered	T38,T103,T155
1	1	1	Covered	T2,T11,T12

 LINE       17432
 EXPRESSION (addr_hit[316] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Not Covered
1	1	1	Covered	T38,T103,T155

 LINE       17433
 EXPRESSION (addr_hit[316] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Covered	T38,T103,T155
1	1	1	Covered	T2,T11,T12

 LINE       17436
 EXPRESSION (addr_hit[317] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Not Covered
1	1	1	Covered	T38,T103,T155

 LINE       17437
 EXPRESSION (addr_hit[317] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Covered	T38,T103,T155
1	1	1	Covered	T2,T11,T12

 LINE       17440
 EXPRESSION (addr_hit[318] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Not Covered
1	1	1	Covered	T38,T103,T155

 LINE       17441
 EXPRESSION (addr_hit[318] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Covered	T38,T103,T155
1	1	1	Covered	T2,T11,T12

 LINE       17444
 EXPRESSION (addr_hit[319] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Not Covered
1	1	1	Covered	T38,T103,T155

 LINE       17445
 EXPRESSION (addr_hit[319] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Covered	T38,T103,T155
1	1	1	Covered	T2,T11,T12

 LINE       17448
 EXPRESSION (addr_hit[320] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Covered	T200
1	1	1	Covered	T2,T11,T12

 LINE       17449
 EXPRESSION (addr_hit[321] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Not Covered
1	1	1	Covered	T2,T11,T12

 LINE       17450
 EXPRESSION (addr_hit[322] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Covered	T38,T103,T155
1	1	1	Covered	T2,T11,T12

 LINE       17453
 EXPRESSION (addr_hit[323] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T38,T103,T155

 LINE       17454
 EXPRESSION (addr_hit[323] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T38,T103,T155
1	1	1	Covered	T1,T2,T3

 LINE       17475
 EXPRESSION (addr_hit[324] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Covered	T38,T103,T155
1	1	1	Covered	T2,T11,T12

 LINE       17478
 EXPRESSION (addr_hit[325] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Covered	T212
1	1	1	Covered	T38,T103,T155

 LINE       17479
 EXPRESSION (addr_hit[325] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Covered	T38,T103,T155
1	1	1	Covered	T2,T11,T12

 LINE       17482
 EXPRESSION (addr_hit[326] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       17483
 EXPRESSION (addr_hit[327] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T38,T103,T155

 LINE       17484
 EXPRESSION (addr_hit[327] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T38,T103,T155
1	1	1	Covered	T1,T2,T3

 LINE       17487
 EXPRESSION (addr_hit[328] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T11,T12,T32
1	1	0	Not Covered
1	1	1	Covered	T38,T103,T155

 LINE       17488
 EXPRESSION (addr_hit[328] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T11,T12,T32
1	1	0	Covered	T38,T103,T155
1	1	1	Covered	T11,T12,T32

 LINE       17491
 EXPRESSION (addr_hit[329] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Not Covered
1	1	1	Covered	T38,T103,T155

 LINE       17492
 EXPRESSION (addr_hit[329] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Covered	T38,T103,T155
1	1	1	Covered	T2,T11,T12

 LINE       17495
 EXPRESSION (addr_hit[330] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Not Covered
1	1	1	Covered	T38,T103,T155

 LINE       17496
 EXPRESSION (addr_hit[330] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Covered	T38,T103,T155
1	1	1	Covered	T2,T11,T12

 LINE       17499
 EXPRESSION (addr_hit[331] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Covered	T199
1	1	1	Covered	T38,T103,T155

 LINE       17500
 EXPRESSION (addr_hit[331] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Covered	T38,T103,T155
1	1	1	Covered	T2,T11,T12

 LINE       17503
 EXPRESSION (addr_hit[332] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Not Covered
1	1	1	Covered	T38,T103,T155

 LINE       17504
 EXPRESSION (addr_hit[332] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Covered	T38,T103,T155
1	1	1	Covered	T2,T11,T12

 LINE       17507
 EXPRESSION (addr_hit[333] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Not Covered
1	1	1	Covered	T38,T103,T155

 LINE       17508
 EXPRESSION (addr_hit[333] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Covered	T38,T103,T155
1	1	1	Covered	T2,T11,T12

 LINE       17511
 EXPRESSION (addr_hit[334] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Not Covered
1	1	1	Covered	T2,T11,T12

 LINE       17512
 EXPRESSION (addr_hit[335] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Not Covered
1	1	1	Covered	T2,T11,T12

 LINE       17513
 EXPRESSION (addr_hit[336] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Covered	T38,T103,T155
1	1	1	Covered	T2,T11,T12

 LINE       17516
 EXPRESSION (addr_hit[337] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T38,T103,T155

 LINE       17517
 EXPRESSION (addr_hit[337] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T38,T103,T155
1	1	1	Covered	T1,T2,T3

 LINE       17538
 EXPRESSION (addr_hit[338] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Covered	T38,T103,T155
1	1	1	Covered	T2,T11,T12

 LINE       17541
 EXPRESSION (addr_hit[339] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Not Covered
1	1	1	Covered	T38,T103,T155

 LINE       17542
 EXPRESSION (addr_hit[339] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Covered	T38,T103,T155
1	1	1	Covered	T2,T11,T12

 LINE       17545
 EXPRESSION (addr_hit[340] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       17546
 EXPRESSION (addr_hit[341] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T38,T103,T155

 LINE       17547
 EXPRESSION (addr_hit[341] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T38,T103,T155
1	1	1	Covered	T1,T2,T3

 LINE       17550
 EXPRESSION (addr_hit[342] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T11,T12,T32
1	1	0	Not Covered
1	1	1	Covered	T38,T103,T155

 LINE       17551
 EXPRESSION (addr_hit[342] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T11,T12,T32
1	1	0	Covered	T38,T103,T155
1	1	1	Covered	T11,T12,T32

 LINE       17554
 EXPRESSION (addr_hit[343] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Covered	T212
1	1	1	Covered	T38,T103,T155

 LINE       17555
 EXPRESSION (addr_hit[343] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Covered	T38,T103,T155
1	1	1	Covered	T2,T11,T12

 LINE       17558
 EXPRESSION (addr_hit[344] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Not Covered
1	1	1	Covered	T38,T103,T155

 LINE       17559
 EXPRESSION (addr_hit[344] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Covered	T38,T103,T155
1	1	1	Covered	T2,T11,T12

 LINE       17562
 EXPRESSION (addr_hit[345] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Not Covered
1	1	1	Covered	T38,T103,T155

 LINE       17563
 EXPRESSION (addr_hit[345] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Covered	T38,T103,T155
1	1	1	Covered	T2,T11,T12

 LINE       17566
 EXPRESSION (addr_hit[346] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Not Covered
1	1	1	Covered	T38,T103,T155

 LINE       17567
 EXPRESSION (addr_hit[346] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Covered	T38,T103,T155
1	1	1	Covered	T2,T11,T12

 LINE       17570
 EXPRESSION (addr_hit[347] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Not Covered
1	1	1	Covered	T38,T103,T155

 LINE       17571
 EXPRESSION (addr_hit[347] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Covered	T38,T103,T155
1	1	1	Covered	T2,T11,T12

 LINE       17574
 EXPRESSION (addr_hit[348] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Covered	T199
1	1	1	Covered	T2,T11,T12

 LINE       17575
 EXPRESSION (addr_hit[349] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T11,T12
1	1	0	Not Covered
1	1	1	Covered	T2,T11,T12

 LINE       19408
 SUB-EXPRESSION (rst_done & shadow_rst_done)
                 ----1---   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T156,T157,T158
1	0	Covered	T156,T157,T158
1	1	Covered	T1,T2,T3