LINE 15854
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_OFFSET)
------------------------------------------1-----------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 15855
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET)
-------------------------------------1-------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 15856
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET)
-------------------------------------1-------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 15857
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET)
-------------------------------------1-------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 15858
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET)
-------------------------------------1-------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 15859
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET)
-------------------------------------1-------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 15860
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_LOC_ALERT_CAUSE_5_OFFSET)
-------------------------------------1-------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 15861
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_LOC_ALERT_CAUSE_6_OFFSET)
-------------------------------------1-------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 15862
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSA_REGWEN_OFFSET)
-----------------------------------1-----------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 15863
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSA_CTRL_SHADOWED_OFFSET)
---------------------------------------1--------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 15864
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET)
-------------------------------------1-------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 15865
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSA_CLR_SHADOWED_OFFSET)
--------------------------------------1--------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 15866
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET)
-------------------------------------1------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 15867
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET)
-------------------------------------------1------------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 15868
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_OFFSET)
------------------------------------------1------------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 15869
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET)
---------------------------------------------1---------------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 15870
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_OFFSET)
------------------------------------------1-----------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 15871
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_OFFSET)
------------------------------------------1-----------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 15872
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_OFFSET)
------------------------------------------1-----------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 15873
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_OFFSET)
------------------------------------------1-----------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 15874
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET)
------------------------------------1-----------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 15875
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSA_STATE_OFFSET)
-----------------------------------1----------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 15876
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSB_REGWEN_OFFSET)
-----------------------------------1-----------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 15877
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSB_CTRL_SHADOWED_OFFSET)
---------------------------------------1--------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 15878
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET)
-------------------------------------1-------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 15879
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSB_CLR_SHADOWED_OFFSET)
--------------------------------------1--------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T10 |
LINE 15880
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET)
-------------------------------------1------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 15881
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET)
-------------------------------------------1------------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 15882
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_OFFSET)
------------------------------------------1------------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 15883
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET)
---------------------------------------------1---------------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 15884
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_OFFSET)
------------------------------------------1-----------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 15885
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_OFFSET)
------------------------------------------1-----------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T10 |
LINE 15886
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_OFFSET)
------------------------------------------1-----------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 15887
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_OFFSET)
------------------------------------------1-----------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 15888
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET)
------------------------------------1-----------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 15889
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSB_STATE_OFFSET)
-----------------------------------1----------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 15890
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSC_REGWEN_OFFSET)
-----------------------------------1-----------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 15891
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSC_CTRL_SHADOWED_OFFSET)
---------------------------------------1--------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 15892
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET)
-------------------------------------1-------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 15893
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSC_CLR_SHADOWED_OFFSET)
--------------------------------------1--------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 15894
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET)
-------------------------------------1------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 15895
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET)
-------------------------------------------1------------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 15896
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_OFFSET)
------------------------------------------1------------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 15897
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET)
---------------------------------------------1---------------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 15898
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_OFFSET)
------------------------------------------1-----------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T10 |
LINE 15899
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_OFFSET)
------------------------------------------1-----------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T10 |
LINE 15900
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_OFFSET)
------------------------------------------1-----------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 15901
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_OFFSET)
------------------------------------------1-----------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T10 |
LINE 15902
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET)
------------------------------------1-----------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 15903
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSC_STATE_OFFSET)
-----------------------------------1----------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 15904
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSD_REGWEN_OFFSET)
-----------------------------------1-----------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 15905
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSD_CTRL_SHADOWED_OFFSET)
---------------------------------------1--------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 15906
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET)
-------------------------------------1-------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 15907
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSD_CLR_SHADOWED_OFFSET)
--------------------------------------1--------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T10 |
LINE 15908
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET)
-------------------------------------1------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 15909
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET)
-------------------------------------------1------------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 15910
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_OFFSET)
------------------------------------------1------------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 15911
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET)
---------------------------------------------1---------------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 15912
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_OFFSET)
------------------------------------------1-----------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 15913
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_OFFSET)
------------------------------------------1-----------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 15914
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_OFFSET)
------------------------------------------1-----------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 15915
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_OFFSET)
------------------------------------------1-----------------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T10 |
LINE 15916
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET)
------------------------------------1-----------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T10 |
LINE 15917
EXPRESSION (reg_addr == alert_handler_reg_pkg::ALERT_HANDLER_CLASSD_STATE_OFFSET)
-----------------------------------1----------------------------------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T10 |
LINE 15920
EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
---------1--------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 15920
SUB-EXPRESSION (reg_re || reg_we)
---1-- ---2--
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 15924
EXPRESSION
Number Term
1 reg_we &
2 ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1 & (~reg_be))))) | (addr_hit[28] & ((|(4'b1 & (~reg_be))))) | (addr_hit[29] & ((|(4'b1 & (~reg_be))))) | (addr_hit[30] & ((|(4'b1 & (~reg_be))))) | (addr_hit[31] & ((|(4'b1 & (~reg_be))))) | (addr_hit[32] & ((|(4'b1 & (~reg_be))))) | (addr_hit[33] & ((|(4'b1 & (~reg_be))))) | (addr_hit[34] & ((|(4'b1 & (~reg_be))))) | (addr_hit[35] & ((|(4'b1 & (~reg_be))))) | (addr_hit[36] & ((|(4'b1 & (~reg_be))))) | (addr_hit[37] & ((|(4'b1 & (~reg_be))))) | (addr_hit[38] & ((|(4'b1 & (~reg_be))))) | (addr_hit[39] & ((|(4'b1 & (~reg_be))))) | (addr_hit[40] & ((|(4'b1 & (~reg_be))))) | (addr_hit[41] & ((|(4'b1 & (~reg_be))))) | (addr_hit[42] & ((|(4'b1 & (~reg_be))))) | (addr_hit[43] & ((|(4'b1 & (~reg_be))))) | (addr_hit[44] & ((|(4'b1 & (~reg_be))))) | (addr_hit[45] & ((|(4'b1 & (~reg_be))))) | (addr_hit[46] & ((|(4'b1 & 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((|(4'b1111 & (~reg_be))))) | (addr_hit[319] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[320] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[321] & ((|(4'b1 & (~reg_be))))) | (addr_hit[322] & ((|(4'b1 & (~reg_be))))) | (addr_hit[323] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[324] & ((|(4'b1 & (~reg_be))))) | (addr_hit[325] & ((|(4'b1 & (~reg_be))))) | (addr_hit[326] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[327] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[328] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[329] & ((|(4'b1 & (~reg_be))))) | (addr_hit[330] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[331] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[332] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[333] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[334] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[335] & ((|(4'b1 & (~reg_be))))) | (addr_hit[336] & ((|(4'b1 & (~reg_be))))) | (addr_hit[337] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[338] & ((|(4'b1 & (~reg_be))))) | (addr_hit[339] & ((|(4'b1 & (~reg_be))))) | (addr_hit[340] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[341] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[342] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[343] & ((|(4'b1 & (~reg_be))))) | (addr_hit[344] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[345] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[346] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[347] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[348] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[349] & ((|(4'b1 & (~reg_be)))))))
| -1- | -2- | Status | Tests |
|---|---|---|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T44,T45,T94 |
LINE 15924
SUB-EXPRESSION
Number Term
1 (addr_hit[0] & ((|(4'b1 & (~reg_be))))) |
2 (addr_hit[1] & ((|(4'b1 & (~reg_be))))) |
3 (addr_hit[2] & ((|(4'b1 & (~reg_be))))) |
4 (addr_hit[3] & ((|(4'b1 & (~reg_be))))) |
5 (addr_hit[4] & ((|(4'b0011 & (~reg_be))))) |
6 (addr_hit[5] & ((|(4'b1 & (~reg_be))))) |
7 (addr_hit[6] & ((|(4'b1 & (~reg_be))))) |
8 (addr_hit[7] & ((|(4'b1 & (~reg_be))))) |
9 (addr_hit[8] & ((|(4'b1 & (~reg_be))))) |
10 (addr_hit[9] & ((|(4'b1 & (~reg_be))))) |
11 (addr_hit[10] & ((|(4'b1 & (~reg_be))))) |
12 (addr_hit[11] & ((|(4'b1 & (~reg_be))))) |
13 (addr_hit[12] & ((|(4'b1 & (~reg_be))))) |
14 (addr_hit[13] & ((|(4'b1 & (~reg_be))))) |
15 (addr_hit[14] & ((|(4'b1 & (~reg_be))))) |
16 (addr_hit[15] & ((|(4'b1 & (~reg_be))))) |
17 (addr_hit[16] & ((|(4'b1 & (~reg_be))))) |
18 (addr_hit[17] & ((|(4'b1 & (~reg_be))))) |
19 (addr_hit[18] & ((|(4'b1 & (~reg_be))))) |
20 (addr_hit[19] & ((|(4'b1 & (~reg_be))))) |
21 (addr_hit[20] & ((|(4'b1 & (~reg_be))))) |
22 (addr_hit[21] & ((|(4'b1 & (~reg_be))))) |
23 (addr_hit[22] & ((|(4'b1 & (~reg_be))))) |
24 (addr_hit[23] & ((|(4'b1 & (~reg_be))))) |
25 (addr_hit[24] & ((|(4'b1 & (~reg_be))))) |
26 (addr_hit[25] & ((|(4'b1 & (~reg_be))))) |
27 (addr_hit[26] & ((|(4'b1 & (~reg_be))))) |
28 (addr_hit[27] & ((|(4'b1 & (~reg_be))))) |
29 (addr_hit[28] & ((|(4'b1 & (~reg_be))))) |
30 (addr_hit[29] & ((|(4'b1 & (~reg_be))))) |
31 (addr_hit[30] & ((|(4'b1 & (~reg_be))))) |
32 (addr_hit[31] & ((|(4'b1 & (~reg_be))))) |
33 (addr_hit[32] & ((|(4'b1 & (~reg_be))))) |
34 (addr_hit[33] & ((|(4'b1 & (~reg_be))))) |
35 (addr_hit[34] & ((|(4'b1 & (~reg_be))))) |
36 (addr_hit[35] & ((|(4'b1 & (~reg_be))))) |
37 (addr_hit[36] & ((|(4'b1 & (~reg_be))))) |
38 (addr_hit[37] & ((|(4'b1 & (~reg_be))))) |
39 (addr_hit[38] & ((|(4'b1 & (~reg_be))))) |
40 (addr_hit[39] & ((|(4'b1 & (~reg_be))))) |
41 (addr_hit[40] & ((|(4'b1 & (~reg_be))))) |
42 (addr_hit[41] & ((|(4'b1 & (~reg_be))))) |
43 (addr_hit[42] & ((|(4'b1 & (~reg_be))))) |
44 (addr_hit[43] & ((|(4'b1 & (~reg_be))))) |
45 (addr_hit[44] & ((|(4'b1 & (~reg_be))))) |
46 (addr_hit[45] & ((|(4'b1 & (~reg_be))))) |
47 (addr_hit[46] & ((|(4'b1 & (~reg_be))))) |
48 (addr_hit[47] & ((|(4'b1 & (~reg_be))))) |
49 (addr_hit[48] & ((|(4'b1 & (~reg_be))))) |
50 (addr_hit[49] & ((|(4'b1 & (~reg_be))))) |
51 (addr_hit[50] & ((|(4'b1 & (~reg_be))))) |
52 (addr_hit[51] & ((|(4'b1 & (~reg_be))))) |
53 (addr_hit[52] & ((|(4'b1 & (~reg_be))))) |
54 (addr_hit[53] & ((|(4'b1 & (~reg_be))))) |
55 (addr_hit[54] & ((|(4'b1 & (~reg_be))))) |
56 (addr_hit[55] & ((|(4'b1 & (~reg_be))))) |
57 (addr_hit[56] & ((|(4'b1 & (~reg_be))))) |
58 (addr_hit[57] & ((|(4'b1 & (~reg_be))))) |
59 (addr_hit[58] & ((|(4'b1 & (~reg_be))))) |
60 (addr_hit[59] & ((|(4'b1 & (~reg_be))))) |
61 (addr_hit[60] & ((|(4'b1 & (~reg_be))))) |
62 (addr_hit[61] & ((|(4'b1 & (~reg_be))))) |
63 (addr_hit[62] & ((|(4'b1 & (~reg_be))))) |
64 (addr_hit[63] & ((|(4'b1 & (~reg_be))))) |
65 (addr_hit[64] & ((|(4'b1 & (~reg_be))))) |
66 (addr_hit[65] & ((|(4'b1 & (~reg_be))))) |
67 (addr_hit[66] & ((|(4'b1 & (~reg_be))))) |
68 (addr_hit[67] & ((|(4'b1 & (~reg_be))))) |
69 (addr_hit[68] & ((|(4'b1 & (~reg_be))))) |
70 (addr_hit[69] & ((|(4'b1 & (~reg_be))))) |
71 (addr_hit[70] & ((|(4'b1 & (~reg_be))))) |
72 (addr_hit[71] & ((|(4'b1 & (~reg_be))))) |
73 (addr_hit[72] & ((|(4'b1 & (~reg_be))))) |
74 (addr_hit[73] & ((|(4'b1 & (~reg_be))))) |
75 (addr_hit[74] & ((|(4'b1 & (~reg_be))))) |
76 (addr_hit[75] & ((|(4'b1 & (~reg_be))))) |
77 (addr_hit[76] & ((|(4'b1 & (~reg_be))))) |
78 (addr_hit[77] & ((|(4'b1 & (~reg_be))))) |
79 (addr_hit[78] & ((|(4'b1 & (~reg_be))))) |
80 (addr_hit[79] & ((|(4'b1 & (~reg_be))))) |
81 (addr_hit[80] & ((|(4'b1 & (~reg_be))))) |
82 (addr_hit[81] & ((|(4'b1 & (~reg_be))))) |
83 (addr_hit[82] & ((|(4'b1 & (~reg_be))))) |
84 (addr_hit[83] & ((|(4'b1 & (~reg_be))))) |
85 (addr_hit[84] & ((|(4'b1 & (~reg_be))))) |
86 (addr_hit[85] & ((|(4'b1 & (~reg_be))))) |
87 (addr_hit[86] & ((|(4'b1 & (~reg_be))))) |
88 (addr_hit[87] & ((|(4'b1 & (~reg_be))))) |
89 (addr_hit[88] & ((|(4'b1 & (~reg_be))))) |
90 (addr_hit[89] & ((|(4'b1 & (~reg_be))))) |
91 (addr_hit[90] & ((|(4'b1 & (~reg_be))))) |
92 (addr_hit[91] & ((|(4'b1 & (~reg_be))))) |
93 (addr_hit[92] & ((|(4'b1 & (~reg_be))))) |
94 (addr_hit[93] & ((|(4'b1 & (~reg_be))))) |
95 (addr_hit[94] & ((|(4'b1 & (~reg_be))))) |
96 (addr_hit[95] & ((|(4'b1 & (~reg_be))))) |
97 (addr_hit[96] & ((|(4'b1 & (~reg_be))))) |
98 (addr_hit[97] & ((|(4'b1 & (~reg_be))))) |
99 (addr_hit[98] & ((|(4'b1 & (~reg_be))))) |
100 (addr_hit[99] & ((|(4'b1 & (~reg_be))))) |
101 (addr_hit[100] & ((|(4'b1 & (~reg_be))))) |
102 (addr_hit[101] & ((|(4'b1 & (~reg_be))))) |
103 (addr_hit[102] & ((|(4'b1 & (~reg_be))))) |
104 (addr_hit[103] & ((|(4'b1 & (~reg_be))))) |
105 (addr_hit[104] & ((|(4'b1 & (~reg_be))))) |
106 (addr_hit[105] & ((|(4'b1 & (~reg_be))))) |
107 (addr_hit[106] & ((|(4'b1 & (~reg_be))))) |
108 (addr_hit[107] & ((|(4'b1 & (~reg_be))))) |
109 (addr_hit[108] & ((|(4'b1 & (~reg_be))))) |
110 (addr_hit[109] & ((|(4'b1 & (~reg_be))))) |
111 (addr_hit[110] & ((|(4'b1 & (~reg_be))))) |
112 (addr_hit[111] & ((|(4'b1 & (~reg_be))))) |
113 (addr_hit[112] & ((|(4'b1 & (~reg_be))))) |
114 (addr_hit[113] & ((|(4'b1 & (~reg_be))))) |
115 (addr_hit[114] & ((|(4'b1 & (~reg_be))))) |
116 (addr_hit[115] & ((|(4'b1 & (~reg_be))))) |
117 (addr_hit[116] & ((|(4'b1 & (~reg_be))))) |
118 (addr_hit[117] & ((|(4'b1 & (~reg_be))))) |
119 (addr_hit[118] & ((|(4'b1 & (~reg_be))))) |
120 (addr_hit[119] & ((|(4'b1 & (~reg_be))))) |
121 (addr_hit[120] & ((|(4'b1 & (~reg_be))))) |
122 (addr_hit[121] & ((|(4'b1 & (~reg_be))))) |
123 (addr_hit[122] & ((|(4'b1 & (~reg_be))))) |
124 (addr_hit[123] & ((|(4'b1 & (~reg_be))))) |
125 (addr_hit[124] & ((|(4'b1 & (~reg_be))))) |
126 (addr_hit[125] & ((|(4'b1 & (~reg_be))))) |
127 (addr_hit[126] & ((|(4'b1 & (~reg_be))))) |
128 (addr_hit[127] & ((|(4'b1 & (~reg_be))))) |
129 (addr_hit[128] & ((|(4'b1 & (~reg_be))))) |
130 (addr_hit[129] & ((|(4'b1 & (~reg_be))))) |
131 (addr_hit[130] & ((|(4'b1 & (~reg_be))))) |
132 (addr_hit[131] & ((|(4'b1 & (~reg_be))))) |
133 (addr_hit[132] & ((|(4'b1 & (~reg_be))))) |
134 (addr_hit[133] & ((|(4'b1 & (~reg_be))))) |
135 (addr_hit[134] & ((|(4'b1 & (~reg_be))))) |
136 (addr_hit[135] & ((|(4'b1 & (~reg_be))))) |
137 (addr_hit[136] & ((|(4'b1 & (~reg_be))))) |
138 (addr_hit[137] & ((|(4'b1 & (~reg_be))))) |
139 (addr_hit[138] & ((|(4'b1 & (~reg_be))))) |
140 (addr_hit[139] & ((|(4'b1 & (~reg_be))))) |
141 (addr_hit[140] & ((|(4'b1 & (~reg_be))))) |
142 (addr_hit[141] & ((|(4'b1 & (~reg_be))))) |
143 (addr_hit[142] & ((|(4'b1 & (~reg_be))))) |
144 (addr_hit[143] & ((|(4'b1 & (~reg_be))))) |
145 (addr_hit[144] & ((|(4'b1 & (~reg_be))))) |
146 (addr_hit[145] & ((|(4'b1 & (~reg_be))))) |
147 (addr_hit[146] & ((|(4'b1 & (~reg_be))))) |
148 (addr_hit[147] & ((|(4'b1 & (~reg_be))))) |
149 (addr_hit[148] & ((|(4'b1 & (~reg_be))))) |
150 (addr_hit[149] & ((|(4'b1 & (~reg_be))))) |
151 (addr_hit[150] & ((|(4'b1 & (~reg_be))))) |
152 (addr_hit[151] & ((|(4'b1 & (~reg_be))))) |
153 (addr_hit[152] & ((|(4'b1 & (~reg_be))))) |
154 (addr_hit[153] & ((|(4'b1 & (~reg_be))))) |
155 (addr_hit[154] & ((|(4'b1 & (~reg_be))))) |
156 (addr_hit[155] & ((|(4'b1 & (~reg_be))))) |
157 (addr_hit[156] & ((|(4'b1 & (~reg_be))))) |
158 (addr_hit[157] & ((|(4'b1 & (~reg_be))))) |
159 (addr_hit[158] & ((|(4'b1 & (~reg_be))))) |
160 (addr_hit[159] & ((|(4'b1 & (~reg_be))))) |
161 (addr_hit[160] & ((|(4'b1 & (~reg_be))))) |
162 (addr_hit[161] & ((|(4'b1 & (~reg_be))))) |
163 (addr_hit[162] & ((|(4'b1 & (~reg_be))))) |
164 (addr_hit[163] & ((|(4'b1 & (~reg_be))))) |
165 (addr_hit[164] & ((|(4'b1 & (~reg_be))))) |
166 (addr_hit[165] & ((|(4'b1 & (~reg_be))))) |
167 (addr_hit[166] & ((|(4'b1 & (~reg_be))))) |
168 (addr_hit[167] & ((|(4'b1 & (~reg_be))))) |
169 (addr_hit[168] & ((|(4'b1 & (~reg_be))))) |
170 (addr_hit[169] & ((|(4'b1 & (~reg_be))))) |
171 (addr_hit[170] & ((|(4'b1 & (~reg_be))))) |
172 (addr_hit[171] & ((|(4'b1 & (~reg_be))))) |
173 (addr_hit[172] & ((|(4'b1 & (~reg_be))))) |
174 (addr_hit[173] & ((|(4'b1 & (~reg_be))))) |
175 (addr_hit[174] & ((|(4'b1 & (~reg_be))))) |
176 (addr_hit[175] & ((|(4'b1 & (~reg_be))))) |
177 (addr_hit[176] & ((|(4'b1 & (~reg_be))))) |
178 (addr_hit[177] & ((|(4'b1 & (~reg_be))))) |
179 (addr_hit[178] & ((|(4'b1 & (~reg_be))))) |
180 (addr_hit[179] & ((|(4'b1 & (~reg_be))))) |
181 (addr_hit[180] & ((|(4'b1 & (~reg_be))))) |
182 (addr_hit[181] & ((|(4'b1 & (~reg_be))))) |
183 (addr_hit[182] & ((|(4'b1 & (~reg_be))))) |
184 (addr_hit[183] & ((|(4'b1 & (~reg_be))))) |
185 (addr_hit[184] & ((|(4'b1 & (~reg_be))))) |
186 (addr_hit[185] & ((|(4'b1 & (~reg_be))))) |
187 (addr_hit[186] & ((|(4'b1 & (~reg_be))))) |
188 (addr_hit[187] & ((|(4'b1 & (~reg_be))))) |
189 (addr_hit[188] & ((|(4'b1 & (~reg_be))))) |
190 (addr_hit[189] & ((|(4'b1 & (~reg_be))))) |
191 (addr_hit[190] & ((|(4'b1 & (~reg_be))))) |
192 (addr_hit[191] & ((|(4'b1 & (~reg_be))))) |
193 (addr_hit[192] & ((|(4'b1 & (~reg_be))))) |
194 (addr_hit[193] & ((|(4'b1 & (~reg_be))))) |
195 (addr_hit[194] & ((|(4'b1 & (~reg_be))))) |
196 (addr_hit[195] & ((|(4'b1 & (~reg_be))))) |
197 (addr_hit[196] & ((|(4'b1 & (~reg_be))))) |
198 (addr_hit[197] & ((|(4'b1 & (~reg_be))))) |
199 (addr_hit[198] & ((|(4'b1 & (~reg_be))))) |
200 (addr_hit[199] & ((|(4'b1 & (~reg_be))))) |
201 (addr_hit[200] & ((|(4'b1 & (~reg_be))))) |
202 (addr_hit[201] & ((|(4'b1 & (~reg_be))))) |
203 (addr_hit[202] & ((|(4'b1 & (~reg_be))))) |
204 (addr_hit[203] & ((|(4'b1 & (~reg_be))))) |
205 (addr_hit[204] & ((|(4'b1 & (~reg_be))))) |
206 (addr_hit[205] & ((|(4'b1 & (~reg_be))))) |
207 (addr_hit[206] & ((|(4'b1 & (~reg_be))))) |
208 (addr_hit[207] & ((|(4'b1 & (~reg_be))))) |
209 (addr_hit[208] & ((|(4'b1 & (~reg_be))))) |
210 (addr_hit[209] & ((|(4'b1 & (~reg_be))))) |
211 (addr_hit[210] & ((|(4'b1 & (~reg_be))))) |
212 (addr_hit[211] & ((|(4'b1 & (~reg_be))))) |
213 (addr_hit[212] & ((|(4'b1 & (~reg_be))))) |
214 (addr_hit[213] & ((|(4'b1 & (~reg_be))))) |
215 (addr_hit[214] & ((|(4'b1 & (~reg_be))))) |
216 (addr_hit[215] & ((|(4'b1 & (~reg_be))))) |
217 (addr_hit[216] & ((|(4'b1 & (~reg_be))))) |
218 (addr_hit[217] & ((|(4'b1 & (~reg_be))))) |
219 (addr_hit[218] & ((|(4'b1 & (~reg_be))))) |
220 (addr_hit[219] & ((|(4'b1 & (~reg_be))))) |
221 (addr_hit[220] & ((|(4'b1 & (~reg_be))))) |
222 (addr_hit[221] & ((|(4'b1 & (~reg_be))))) |
223 (addr_hit[222] & ((|(4'b1 & (~reg_be))))) |
224 (addr_hit[223] & ((|(4'b1 & (~reg_be))))) |
225 (addr_hit[224] & ((|(4'b1 & (~reg_be))))) |
226 (addr_hit[225] & ((|(4'b1 & (~reg_be))))) |
227 (addr_hit[226] & ((|(4'b1 & (~reg_be))))) |
228 (addr_hit[227] & ((|(4'b1 & (~reg_be))))) |
229 (addr_hit[228] & ((|(4'b1 & (~reg_be))))) |
230 (addr_hit[229] & ((|(4'b1 & (~reg_be))))) |
231 (addr_hit[230] & ((|(4'b1 & (~reg_be))))) |
232 (addr_hit[231] & ((|(4'b1 & (~reg_be))))) |
233 (addr_hit[232] & ((|(4'b1 & (~reg_be))))) |
234 (addr_hit[233] & ((|(4'b1 & (~reg_be))))) |
235 (addr_hit[234] & ((|(4'b1 & (~reg_be))))) |
236 (addr_hit[235] & ((|(4'b1 & (~reg_be))))) |
237 (addr_hit[236] & ((|(4'b1 & (~reg_be))))) |
238 (addr_hit[237] & ((|(4'b1 & (~reg_be))))) |
239 (addr_hit[238] & ((|(4'b1 & (~reg_be))))) |
240 (addr_hit[239] & ((|(4'b1 & (~reg_be))))) |
241 (addr_hit[240] & ((|(4'b1 & (~reg_be))))) |
242 (addr_hit[241] & ((|(4'b1 & (~reg_be))))) |
243 (addr_hit[242] & ((|(4'b1 & (~reg_be))))) |
244 (addr_hit[243] & ((|(4'b1 & (~reg_be))))) |
245 (addr_hit[244] & ((|(4'b1 & (~reg_be))))) |
246 (addr_hit[245] & ((|(4'b1 & (~reg_be))))) |
247 (addr_hit[246] & ((|(4'b1 & (~reg_be))))) |
248 (addr_hit[247] & ((|(4'b1 & (~reg_be))))) |
249 (addr_hit[248] & ((|(4'b1 & (~reg_be))))) |
250 (addr_hit[249] & ((|(4'b1 & (~reg_be))))) |
251 (addr_hit[250] & ((|(4'b1 & (~reg_be))))) |
252 (addr_hit[251] & ((|(4'b1 & (~reg_be))))) |
253 (addr_hit[252] & ((|(4'b1 & (~reg_be))))) |
254 (addr_hit[253] & ((|(4'b1 & (~reg_be))))) |
255 (addr_hit[254] & ((|(4'b1 & (~reg_be))))) |
256 (addr_hit[255] & ((|(4'b1 & (~reg_be))))) |
257 (addr_hit[256] & ((|(4'b1 & (~reg_be))))) |
258 (addr_hit[257] & ((|(4'b1 & (~reg_be))))) |
259 (addr_hit[258] & ((|(4'b1 & (~reg_be))))) |
260 (addr_hit[259] & ((|(4'b1 & (~reg_be))))) |
261 (addr_hit[260] & ((|(4'b1 & (~reg_be))))) |
262 (addr_hit[261] & ((|(4'b1 & (~reg_be))))) |
263 (addr_hit[262] & ((|(4'b1 & (~reg_be))))) |
264 (addr_hit[263] & ((|(4'b1 & (~reg_be))))) |
265 (addr_hit[264] & ((|(4'b1 & (~reg_be))))) |
266 (addr_hit[265] & ((|(4'b1 & (~reg_be))))) |
267 (addr_hit[266] & ((|(4'b1 & (~reg_be))))) |
268 (addr_hit[267] & ((|(4'b1 & (~reg_be))))) |
269 (addr_hit[268] & ((|(4'b1 & (~reg_be))))) |
270 (addr_hit[269] & ((|(4'b1 & (~reg_be))))) |
271 (addr_hit[270] & ((|(4'b1 & (~reg_be))))) |
272 (addr_hit[271] & ((|(4'b1 & (~reg_be))))) |
273 (addr_hit[272] & ((|(4'b1 & (~reg_be))))) |
274 (addr_hit[273] & ((|(4'b1 & (~reg_be))))) |
275 (addr_hit[274] & ((|(4'b1 & (~reg_be))))) |
276 (addr_hit[275] & ((|(4'b1 & (~reg_be))))) |
277 (addr_hit[276] & ((|(4'b1 & (~reg_be))))) |
278 (addr_hit[277] & ((|(4'b1 & (~reg_be))))) |
279 (addr_hit[278] & ((|(4'b1 & (~reg_be))))) |
280 (addr_hit[279] & ((|(4'b1 & (~reg_be))))) |
281 (addr_hit[280] & ((|(4'b1 & (~reg_be))))) |
282 (addr_hit[281] & ((|(4'b1 & (~reg_be))))) |
283 (addr_hit[282] & ((|(4'b1 & (~reg_be))))) |
284 (addr_hit[283] & ((|(4'b1 & (~reg_be))))) |
285 (addr_hit[284] & ((|(4'b1 & (~reg_be))))) |
286 (addr_hit[285] & ((|(4'b1 & (~reg_be))))) |
287 (addr_hit[286] & ((|(4'b1 & (~reg_be))))) |
288 (addr_hit[287] & ((|(4'b1 & (~reg_be))))) |
289 (addr_hit[288] & ((|(4'b1 & (~reg_be))))) |
290 (addr_hit[289] & ((|(4'b1 & (~reg_be))))) |
291 (addr_hit[290] & ((|(4'b1 & (~reg_be))))) |
292 (addr_hit[291] & ((|(4'b1 & (~reg_be))))) |
293 (addr_hit[292] & ((|(4'b1 & (~reg_be))))) |
294 (addr_hit[293] & ((|(4'b1 & (~reg_be))))) |
295 (addr_hit[294] & ((|(4'b1 & (~reg_be))))) |
296 (addr_hit[295] & ((|(4'b0011 & (~reg_be))))) |
297 (addr_hit[296] & ((|(4'b1 & (~reg_be))))) |
298 (addr_hit[297] & ((|(4'b1 & (~reg_be))))) |
299 (addr_hit[298] & ((|(4'b0011 & (~reg_be))))) |
300 (addr_hit[299] & ((|(4'b0011 & (~reg_be))))) |
301 (addr_hit[300] & ((|(4'b1111 & (~reg_be))))) |
302 (addr_hit[301] & ((|(4'b1 & (~reg_be))))) |
303 (addr_hit[302] & ((|(4'b1111 & (~reg_be))))) |
304 (addr_hit[303] & ((|(4'b1111 & (~reg_be))))) |
305 (addr_hit[304] & ((|(4'b1111 & (~reg_be))))) |
306 (addr_hit[305] & ((|(4'b1111 & (~reg_be))))) |
307 (addr_hit[306] & ((|(4'b1111 & (~reg_be))))) |
308 (addr_hit[307] & ((|(4'b1 & (~reg_be))))) |
309 (addr_hit[308] & ((|(4'b1 & (~reg_be))))) |
310 (addr_hit[309] & ((|(4'b0011 & (~reg_be))))) |
311 (addr_hit[310] & ((|(4'b1 & (~reg_be))))) |
312 (addr_hit[311] & ((|(4'b1 & (~reg_be))))) |
313 (addr_hit[312] & ((|(4'b0011 & (~reg_be))))) |
314 (addr_hit[313] & ((|(4'b0011 & (~reg_be))))) |
315 (addr_hit[314] & ((|(4'b1111 & (~reg_be))))) |
316 (addr_hit[315] & ((|(4'b1 & (~reg_be))))) |
317 (addr_hit[316] & ((|(4'b1111 & (~reg_be))))) |
318 (addr_hit[317] & ((|(4'b1111 & (~reg_be))))) |
319 (addr_hit[318] & ((|(4'b1111 & (~reg_be))))) |
320 (addr_hit[319] & ((|(4'b1111 & (~reg_be))))) |
321 (addr_hit[320] & ((|(4'b1111 & (~reg_be))))) |
322 (addr_hit[321] & ((|(4'b1 & (~reg_be))))) |
323 (addr_hit[322] & ((|(4'b1 & (~reg_be))))) |
324 (addr_hit[323] & ((|(4'b0011 & (~reg_be))))) |
325 (addr_hit[324] & ((|(4'b1 & (~reg_be))))) |
326 (addr_hit[325] & ((|(4'b1 & (~reg_be))))) |
327 (addr_hit[326] & ((|(4'b0011 & (~reg_be))))) |
328 (addr_hit[327] & ((|(4'b0011 & (~reg_be))))) |
329 (addr_hit[328] & ((|(4'b1111 & (~reg_be))))) |
330 (addr_hit[329] & ((|(4'b1 & (~reg_be))))) |
331 (addr_hit[330] & ((|(4'b1111 & (~reg_be))))) |
332 (addr_hit[331] & ((|(4'b1111 & (~reg_be))))) |
333 (addr_hit[332] & ((|(4'b1111 & (~reg_be))))) |
334 (addr_hit[333] & ((|(4'b1111 & (~reg_be))))) |
335 (addr_hit[334] & ((|(4'b1111 & (~reg_be))))) |
336 (addr_hit[335] & ((|(4'b1 & (~reg_be))))) |
337 (addr_hit[336] & ((|(4'b1 & (~reg_be))))) |
338 (addr_hit[337] & ((|(4'b0011 & (~reg_be))))) |
339 (addr_hit[338] & ((|(4'b1 & (~reg_be))))) |
340 (addr_hit[339] & ((|(4'b1 & (~reg_be))))) |
341 (addr_hit[340] & ((|(4'b0011 & (~reg_be))))) |
342 (addr_hit[341] & ((|(4'b0011 & (~reg_be))))) |
343 (addr_hit[342] & ((|(4'b1111 & (~reg_be))))) |
344 (addr_hit[343] & ((|(4'b1 & (~reg_be))))) |
345 (addr_hit[344] & ((|(4'b1111 & (~reg_be))))) |
346 (addr_hit[345] & ((|(4'b1111 & (~reg_be))))) |
347 (addr_hit[346] & ((|(4'b1111 & (~reg_be))))) |
348 (addr_hit[347] & ((|(4'b1111 & (~reg_be))))) |
349 (addr_hit[348] & ((|(4'b1111 & (~reg_be))))) |
350 (addr_hit[349] & ((|(4'b1 & (~reg_be))))))
| Sensitive Expression == 1 | Status | Tests |
|---|---|---|
| ALL ZEROS | Covered | T1,T2,T3 |
| 350 (addr_hit[349] & ((|(4... | Covered | T2,T3,T10 |
| 349 (addr_hit[348] & ((|(4... | Covered | T2,T3,T10 |
| 348 (addr_hit[347] & ((|(4... | Covered | T5,T17,T11 |
| 347 (addr_hit[346] & ((|(4... | Covered | T1,T5,T17 |
| 346 (addr_hit[345] & ((|(4... | Covered | T1,T4,T5 |
| 345 (addr_hit[344] & ((|(4... | Covered | T1,T4,T5 |
| 344 (addr_hit[343] & ((|(4... | Covered | T5,T17,T11 |
| 343 (addr_hit[342] & ((|(4... | Covered | T1,T5,T17 |
| 342 (addr_hit[341] & ((|(4... | Covered | T1,T5,T17 |
| 341 (addr_hit[340] & ((|(4... | Covered | T1,T2,T3 |
| 340 (addr_hit[339] & ((|(4... | Covered | T17,T11,T27 |
| 339 (addr_hit[338] & ((|(4... | Covered | T5,T17,T11 |
| 338 (addr_hit[337] & ((|(4... | Covered | T4,T5,T17 |
| 337 (addr_hit[336] & ((|(4... | Covered | T4,T5,T17 |
| 336 (addr_hit[335] & ((|(4... | Covered | T2,T3,T4 |
| 335 (addr_hit[334] & ((|(4... | Covered | T1,T2,T3 |
| 334 (addr_hit[333] & ((|(4... | Covered | T5,T17,T11 |
| 333 (addr_hit[332] & ((|(4... | Covered | T1,T5,T17 |
| 332 (addr_hit[331] & ((|(4... | Covered | T5,T17,T11 |
| 331 (addr_hit[330] & ((|(4... | Covered | T5,T17,T11 |
| 330 (addr_hit[329] & ((|(4... | Covered | T4,T5,T17 |
| 329 (addr_hit[328] & ((|(4... | Covered | T1,T5,T17 |
| 328 (addr_hit[327] & ((|(4... | Covered | T4,T5,T17 |
| 327 (addr_hit[326] & ((|(4... | Covered | T1,T2,T3 |
| 326 (addr_hit[325] & ((|(4... | Covered | T5,T17,T27 |
| 325 (addr_hit[324] & ((|(4... | Covered | T5,T17,T11 |
| 324 (addr_hit[323] & ((|(4... | Covered | T1,T17,T11 |
| 323 (addr_hit[322] & ((|(4... | Covered | T4,T5,T17 |
| 322 (addr_hit[321] & ((|(4... | Covered | T2,T3,T4 |
| 321 (addr_hit[320] & ((|(4... | Covered | T1,T2,T3 |
| 320 (addr_hit[319] & ((|(4... | Covered | T1,T5,T17 |
| 319 (addr_hit[318] & ((|(4... | Covered | T1,T5,T17 |
| 318 (addr_hit[317] & ((|(4... | Covered | T5,T17,T11 |
| 317 (addr_hit[316] & ((|(4... | Covered | T4,T5,T17 |
| 316 (addr_hit[315] & ((|(4... | Covered | T4,T17,T11 |
| 315 (addr_hit[314] & ((|(4... | Covered | T4,T5,T17 |
| 314 (addr_hit[313] & ((|(4... | Covered | T1,T5,T17 |
| 313 (addr_hit[312] & ((|(4... | Covered | T1,T2,T3 |
| 312 (addr_hit[311] & ((|(4... | Covered | T5,T17,T11 |
| 311 (addr_hit[310] & ((|(4... | Covered | T5,T17,T11 |
| 310 (addr_hit[309] & ((|(4... | Covered | T5,T17,T11 |
| 309 (addr_hit[308] & ((|(4... | Covered | T1,T5,T17 |
| 308 (addr_hit[307] & ((|(4... | Covered | T1,T2,T3 |
| 307 (addr_hit[306] & ((|(4... | Covered | T1,T2,T3 |
| 306 (addr_hit[305] & ((|(4... | Covered | T1,T5,T17 |
| 305 (addr_hit[304] & ((|(4... | Covered | T1,T4,T5 |
| 304 (addr_hit[303] & ((|(4... | Covered | T4,T5,T17 |
| 303 (addr_hit[302] & ((|(4... | Covered | T4,T5,T17 |
| 302 (addr_hit[301] & ((|(4... | Covered | T1,T4,T5 |
| 301 (addr_hit[300] & ((|(4... | Covered | T1,T5,T17 |
| 300 (addr_hit[299] & ((|(4... | Covered | T1,T4,T5 |
| 299 (addr_hit[298] & ((|(4... | Covered | T1,T2,T3 |
| 298 (addr_hit[297] & ((|(4... | Covered | T5,T17,T11 |
| 297 (addr_hit[296] & ((|(4... | Covered | T17,T11,T27 |
| 296 (addr_hit[295] & ((|(4... | Covered | T1,T4,T5 |
| 295 (addr_hit[294] & ((|(4... | Covered | T4,T5,T17 |
| 294 (addr_hit[293] & ((|(4... | Covered | T2,T3,T4 |
| 293 (addr_hit[292] & ((|(4... | Covered | T2,T3,T4 |
| 292 (addr_hit[291] & ((|(4... | Covered | T1,T2,T3 |
| 291 (addr_hit[290] & ((|(4... | Covered | T2,T3,T4 |
| 290 (addr_hit[289] & ((|(4... | Covered | T2,T4,T10 |
| 289 (addr_hit[288] & ((|(4... | Covered | T2,T4,T10 |
| 288 (addr_hit[287] & ((|(4... | Covered | T2,T3,T10 |
| 287 (addr_hit[286] & ((|(4... | Covered | T4,T5,T17 |
| 286 (addr_hit[285] & ((|(4... | Covered | T5,T17,T11 |
| 285 (addr_hit[284] & ((|(4... | Covered | T1,T4,T5 |
| 284 (addr_hit[283] & ((|(4... | Covered | T5,T17,T11 |
| 283 (addr_hit[282] & ((|(4... | Covered | T1,T4,T5 |
| 282 (addr_hit[281] & ((|(4... | Covered | T5,T17,T11 |
| 281 (addr_hit[280] & ((|(4... | Covered | T5,T17,T11 |
| 280 (addr_hit[279] & ((|(4... | Covered | T4,T5,T17 |
| 279 (addr_hit[278] & ((|(4... | Covered | T4,T5,T17 |
| 278 (addr_hit[277] & ((|(4... | Covered | T1,T5,T17 |
| 277 (addr_hit[276] & ((|(4... | Covered | T1,T4,T5 |
| 276 (addr_hit[275] & ((|(4... | Covered | T5,T17,T11 |
| 275 (addr_hit[274] & ((|(4... | Covered | T17,T11,T27 |
| 274 (addr_hit[273] & ((|(4... | Covered | T1,T5,T17 |
| 273 (addr_hit[272] & ((|(4... | Covered | T5,T17,T11 |
| 272 (addr_hit[271] & ((|(4... | Covered | T1,T4,T5 |
| 271 (addr_hit[270] & ((|(4... | Covered | T5,T17,T11 |
| 270 (addr_hit[269] & ((|(4... | Covered | T5,T17,T11 |
| 269 (addr_hit[268] & ((|(4... | Covered | T5,T17,T11 |
| 268 (addr_hit[267] & ((|(4... | Covered | T5,T17,T11 |
| 267 (addr_hit[266] & ((|(4... | Covered | T5,T17,T11 |
| 266 (addr_hit[265] & ((|(4... | Covered | T2,T3,T4 |
| 265 (addr_hit[264] & ((|(4... | Covered | T2,T3,T10 |
| 264 (addr_hit[263] & ((|(4... | Covered | T1,T2,T3 |
| 263 (addr_hit[262] & ((|(4... | Covered | T2,T3,T4 |
| 262 (addr_hit[261] & ((|(4... | Covered | T2,T3,T4 |
| 261 (addr_hit[260] & ((|(4... | Covered | T2,T3,T10 |
| 260 (addr_hit[259] & ((|(4... | Covered | T1,T2,T3 |
| 259 (addr_hit[258] & ((|(4... | Covered | T2,T3,T4 |
| 258 (addr_hit[257] & ((|(4... | Covered | T2,T3,T4 |
| 257 (addr_hit[256] & ((|(4... | Covered | T2,T3,T4 |
| 256 (addr_hit[255] & ((|(4... | Covered | T2,T3,T10 |
| 255 (addr_hit[254] & ((|(4... | Covered | T2,T3,T10 |
| 254 (addr_hit[253] & ((|(4... | Covered | T2,T3,T10 |
| 253 (addr_hit[252] & ((|(4... | Covered | T2,T3,T4 |
| 252 (addr_hit[251] & ((|(4... | Covered | T2,T3,T4 |
| 251 (addr_hit[250] & ((|(4... | Covered | T4,T10,T12 |
| 250 (addr_hit[249] & ((|(4... | Covered | T2,T3,T10 |
| 249 (addr_hit[248] & ((|(4... | Covered | T2,T3,T10 |
| 248 (addr_hit[247] & ((|(4... | Covered | T2,T3,T10 |
| 247 (addr_hit[246] & ((|(4... | Covered | T2,T3,T10 |
| 246 (addr_hit[245] & ((|(4... | Covered | T1,T2,T3 |
| 245 (addr_hit[244] & ((|(4... | Covered | T2,T3,T4 |
| 244 (addr_hit[243] & ((|(4... | Covered | T2,T3,T4 |
| 243 (addr_hit[242] & ((|(4... | Covered | T2,T3,T4 |
| 242 (addr_hit[241] & ((|(4... | Covered | T1,T2,T3 |
| 241 (addr_hit[240] & ((|(4... | Covered | T2,T3,T4 |
| 240 (addr_hit[239] & ((|(4... | Covered | T2,T3,T4 |
| 239 (addr_hit[238] & ((|(4... | Covered | T1,T2,T3 |
| 238 (addr_hit[237] & ((|(4... | Covered | T2,T3,T10 |
| 237 (addr_hit[236] & ((|(4... | Covered | T2,T3,T10 |
| 236 (addr_hit[235] & ((|(4... | Covered | T2,T3,T10 |
| 235 (addr_hit[234] & ((|(4... | Covered | T1,T2,T3 |
| 234 (addr_hit[233] & ((|(4... | Covered | T2,T4,T10 |
| 233 (addr_hit[232] & ((|(4... | Covered | T2,T3,T4 |
| 232 (addr_hit[231] & ((|(4... | Covered | T2,T3,T4 |
| 231 (addr_hit[230] & ((|(4... | Covered | T3,T4,T10 |
| 230 (addr_hit[229] & ((|(4... | Covered | T2,T3,T4 |
| 229 (addr_hit[228] & ((|(4... | Covered | T2,T3,T4 |
| 228 (addr_hit[227] & ((|(4... | Covered | T1,T2,T4 |
| 227 (addr_hit[226] & ((|(4... | Covered | T2,T3,T10 |
| 226 (addr_hit[225] & ((|(4... | Covered | T1,T2,T3 |
| 225 (addr_hit[224] & ((|(4... | Covered | T2,T3,T4 |
| 224 (addr_hit[223] & ((|(4... | Covered | T1,T2,T4 |
| 223 (addr_hit[222] & ((|(4... | Covered | T2,T3,T4 |
| 222 (addr_hit[221] & ((|(4... | Covered | T1,T2,T3 |
| 221 (addr_hit[220] & ((|(4... | Covered | T2,T3,T10 |
| 220 (addr_hit[219] & ((|(4... | Covered | T2,T4,T10 |
| 219 (addr_hit[218] & ((|(4... | Covered | T1,T2,T3 |
| 218 (addr_hit[217] & ((|(4... | Covered | T2,T3,T10 |
| 217 (addr_hit[216] & ((|(4... | Covered | T1,T2,T3 |
| 216 (addr_hit[215] & ((|(4... | Covered | T2,T3,T4 |
| 215 (addr_hit[214] & ((|(4... | Covered | T1,T3,T10 |
| 214 (addr_hit[213] & ((|(4... | Covered | T2,T3,T4 |
| 213 (addr_hit[212] & ((|(4... | Covered | T1,T2,T3 |
| 212 (addr_hit[211] & ((|(4... | Covered | T2,T3,T10 |
| 211 (addr_hit[210] & ((|(4... | Covered | T3,T4,T10 |
| 210 (addr_hit[209] & ((|(4... | Covered | T2,T3,T4 |
| 209 (addr_hit[208] & ((|(4... | Covered | T1,T2,T3 |
| 208 (addr_hit[207] & ((|(4... | Covered | T1,T2,T10 |
| 207 (addr_hit[206] & ((|(4... | Covered | T1,T2,T3 |
| 206 (addr_hit[205] & ((|(4... | Covered | T1,T2,T3 |
| 205 (addr_hit[204] & ((|(4... | Covered | T2,T3,T10 |
| 204 (addr_hit[203] & ((|(4... | Covered | T2,T3,T10 |
| 203 (addr_hit[202] & ((|(4... | Covered | T2,T3,T10 |
| 202 (addr_hit[201] & ((|(4... | Covered | T1,T2,T3 |
| 201 (addr_hit[200] & ((|(4... | Covered | T4,T5,T17 |
| 200 (addr_hit[199] & ((|(4... | Covered | T5,T17,T11 |
| 199 (addr_hit[198] & ((|(4... | Covered | T17,T11,T27 |
| 198 (addr_hit[197] & ((|(4... | Covered | T5,T17,T11 |
| 197 (addr_hit[196] & ((|(4... | Covered | T1,T5,T17 |
| 196 (addr_hit[195] & ((|(4... | Covered | T5,T17,T11 |
| 195 (addr_hit[194] & ((|(4... | Covered | T4,T5,T17 |
| 194 (addr_hit[193] & ((|(4... | Covered | T1,T17,T11 |
| 193 (addr_hit[192] & ((|(4... | Covered | T5,T11,T27 |
| 192 (addr_hit[191] & ((|(4... | Covered | T1,T5,T17 |
| 191 (addr_hit[190] & ((|(4... | Covered | T5,T17,T11 |
| 190 (addr_hit[189] & ((|(4... | Covered | T17,T11,T27 |
| 189 (addr_hit[188] & ((|(4... | Covered | T5,T17,T11 |
| 188 (addr_hit[187] & ((|(4... | Covered | T1,T5,T17 |
| 187 (addr_hit[186] & ((|(4... | Covered | T5,T17,T11 |
| 186 (addr_hit[185] & ((|(4... | Covered | T5,T17,T11 |
| 185 (addr_hit[184] & ((|(4... | Covered | T1,T4,T5 |
| 184 (addr_hit[183] & ((|(4... | Covered | T5,T17,T11 |
| 183 (addr_hit[182] & ((|(4... | Covered | T4,T5,T17 |
| 182 (addr_hit[181] & ((|(4... | Covered | T1,T4,T5 |
| 181 (addr_hit[180] & ((|(4... | Covered | T4,T5,T17 |
| 180 (addr_hit[179] & ((|(4... | Covered | T17,T11,T27 |
| 179 (addr_hit[178] & ((|(4... | Covered | T4,T5,T17 |
| 178 (addr_hit[177] & ((|(4... | Covered | T5,T17,T11 |
| 177 (addr_hit[176] & ((|(4... | Covered | T5,T17,T11 |
| 176 (addr_hit[175] & ((|(4... | Covered | T5,T17,T11 |
| 175 (addr_hit[174] & ((|(4... | Covered | T5,T17,T11 |
| 174 (addr_hit[173] & ((|(4... | Covered | T1,T4,T5 |
| 173 (addr_hit[172] & ((|(4... | Covered | T1,T4,T5 |
| 172 (addr_hit[171] & ((|(4... | Covered | T4,T5,T17 |
| 171 (addr_hit[170] & ((|(4... | Covered | T4,T5,T17 |
| 170 (addr_hit[169] & ((|(4... | Covered | T4,T5,T17 |
| 169 (addr_hit[168] & ((|(4... | Covered | T17,T11,T27 |
| 168 (addr_hit[167] & ((|(4... | Covered | T17,T27,T43 |
| 167 (addr_hit[166] & ((|(4... | Covered | T5,T17,T11 |
| 166 (addr_hit[165] & ((|(4... | Covered | T1,T4,T5 |
| 165 (addr_hit[164] & ((|(4... | Covered | T5,T17,T11 |
| 164 (addr_hit[163] & ((|(4... | Covered | T5,T17,T11 |
| 163 (addr_hit[162] & ((|(4... | Covered | T4,T5,T17 |
| 162 (addr_hit[161] & ((|(4... | Covered | T1,T4,T5 |
| 161 (addr_hit[160] & ((|(4... | Covered | T1,T5,T17 |
| 160 (addr_hit[159] & ((|(4... | Covered | T4,T5,T17 |
| 159 (addr_hit[158] & ((|(4... | Covered | T5,T17,T11 |
| 158 (addr_hit[157] & ((|(4... | Covered | T4,T5,T17 |
| 157 (addr_hit[156] & ((|(4... | Covered | T4,T5,T17 |
| 156 (addr_hit[155] & ((|(4... | Covered | T1,T4,T5 |
| 155 (addr_hit[154] & ((|(4... | Covered | T1,T5,T17 |
| 154 (addr_hit[153] & ((|(4... | Covered | T17,T11,T27 |
| 153 (addr_hit[152] & ((|(4... | Covered | T5,T17,T11 |
| 152 (addr_hit[151] & ((|(4... | Covered | T5,T17,T11 |
| 151 (addr_hit[150] & ((|(4... | Covered | T1,T17,T11 |
| 150 (addr_hit[149] & ((|(4... | Covered | T5,T17,T11 |
| 149 (addr_hit[148] & ((|(4... | Covered | T5,T17,T11 |
| 148 (addr_hit[147] & ((|(4... | Covered | T4,T5,T17 |
| 147 (addr_hit[146] & ((|(4... | Covered | T1,T5,T17 |
| 146 (addr_hit[145] & ((|(4... | Covered | T5,T17,T11 |
| 145 (addr_hit[144] & ((|(4... | Covered | T5,T17,T11 |
| 144 (addr_hit[143] & ((|(4... | Covered | T17,T11,T27 |
| 143 (addr_hit[142] & ((|(4... | Covered | T1,T11,T27 |
| 142 (addr_hit[141] & ((|(4... | Covered | T5,T17,T11 |
| 141 (addr_hit[140] & ((|(4... | Covered | T5,T17,T11 |
| 140 (addr_hit[139] & ((|(4... | Covered | T4,T5,T17 |
| 139 (addr_hit[138] & ((|(4... | Covered | T4,T5,T17 |
| 138 (addr_hit[137] & ((|(4... | Covered | T1,T5,T17 |
| 137 (addr_hit[136] & ((|(4... | Covered | T4,T5,T17 |
| 136 (addr_hit[135] & ((|(4... | Covered | T1,T17,T11 |
| 135 (addr_hit[134] & ((|(4... | Covered | T4,T5,T17 |
| 134 (addr_hit[133] & ((|(4... | Covered | T5,T17,T11 |
| 133 (addr_hit[132] & ((|(4... | Covered | T1,T4,T5 |
| 132 (addr_hit[131] & ((|(4... | Covered | T4,T5,T17 |
| 131 (addr_hit[130] & ((|(4... | Covered | T11,T27,T43 |
| 130 (addr_hit[129] & ((|(4... | Covered | T4,T17,T11 |
| 129 (addr_hit[128] & ((|(4... | Covered | T4,T5,T17 |
| 128 (addr_hit[127] & ((|(4... | Covered | T4,T5,T17 |
| 127 (addr_hit[126] & ((|(4... | Covered | T5,T17,T11 |
| 126 (addr_hit[125] & ((|(4... | Covered | T1,T4,T5 |
| 125 (addr_hit[124] & ((|(4... | Covered | T1,T5,T17 |
| 124 (addr_hit[123] & ((|(4... | Covered | T4,T5,T17 |
| 123 (addr_hit[122] & ((|(4... | Covered | T4,T5,T17 |
| 122 (addr_hit[121] & ((|(4... | Covered | T1,T4,T5 |
| 121 (addr_hit[120] & ((|(4... | Covered | T1,T4,T5 |
| 120 (addr_hit[119] & ((|(4... | Covered | T4,T17,T11 |
| 119 (addr_hit[118] & ((|(4... | Covered | T4,T5,T17 |
| 118 (addr_hit[117] & ((|(4... | Covered | T1,T5,T17 |
| 117 (addr_hit[116] & ((|(4... | Covered | T5,T17,T11 |
| 116 (addr_hit[115] & ((|(4... | Covered | T1,T5,T17 |
| 115 (addr_hit[114] & ((|(4... | Covered | T5,T17,T11 |
| 114 (addr_hit[113] & ((|(4... | Covered | T5,T17,T11 |
| 113 (addr_hit[112] & ((|(4... | Covered | T1,T4,T5 |
| 112 (addr_hit[111] & ((|(4... | Covered | T4,T5,T17 |
| 111 (addr_hit[110] & ((|(4... | Covered | T4,T5,T17 |
| 110 (addr_hit[109] & ((|(4... | Covered | T5,T17,T11 |
| 109 (addr_hit[108] & ((|(4... | Covered | T5,T17,T11 |
| 108 (addr_hit[107] & ((|(4... | Covered | T1,T5,T17 |
| 107 (addr_hit[106] & ((|(4... | Covered | T4,T5,T17 |
| 106 (addr_hit[105] & ((|(4... | Covered | T4,T5,T17 |
| 105 (addr_hit[104] & ((|(4... | Covered | T4,T5,T17 |
| 104 (addr_hit[103] & ((|(4... | Covered | T5,T17,T11 |
| 103 (addr_hit[102] & ((|(4... | Covered | T5,T17,T11 |
| 102 (addr_hit[101] & ((|(4... | Covered | T5,T17,T11 |
| 101 (addr_hit[100] & ((|(4... | Covered | T5,T17,T11 |
| 100 (addr_hit[99] & ((|(4'... | Covered | T1,T5,T17 |
| 99 (addr_hit[98] & ((|(4'... | Covered | T1,T4,T5 |
| 98 (addr_hit[97] & ((|(4'... | Covered | T5,T17,T11 |
| 97 (addr_hit[96] & ((|(4'... | Covered | T4,T5,T17 |
| 96 (addr_hit[95] & ((|(4'... | Covered | T1,T5,T17 |
| 95 (addr_hit[94] & ((|(4'... | Covered | T1,T5,T17 |
| 94 (addr_hit[93] & ((|(4'... | Covered | T1,T5,T17 |
| 93 (addr_hit[92] & ((|(4'... | Covered | T5,T17,T11 |
| 92 (addr_hit[91] & ((|(4'... | Covered | T1,T5,T17 |
| 91 (addr_hit[90] & ((|(4'... | Covered | T5,T17,T11 |
| 90 (addr_hit[89] & ((|(4'... | Covered | T1,T4,T5 |
| 89 (addr_hit[88] & ((|(4'... | Covered | T1,T4,T5 |
| 88 (addr_hit[87] & ((|(4'... | Covered | T4,T5,T17 |
| 87 (addr_hit[86] & ((|(4'... | Covered | T1,T5,T17 |
| 86 (addr_hit[85] & ((|(4'... | Covered | T5,T17,T11 |
| 85 (addr_hit[84] & ((|(4'... | Covered | T5,T17,T11 |
| 84 (addr_hit[83] & ((|(4'... | Covered | T17,T11,T27 |
| 83 (addr_hit[82] & ((|(4'... | Covered | T5,T17,T11 |
| 82 (addr_hit[81] & ((|(4'... | Covered | T4,T5,T17 |
| 81 (addr_hit[80] & ((|(4'... | Covered | T4,T5,T17 |
| 80 (addr_hit[79] & ((|(4'... | Covered | T4,T17,T11 |
| 79 (addr_hit[78] & ((|(4'... | Covered | T4,T5,T17 |
| 78 (addr_hit[77] & ((|(4'... | Covered | T5,T17,T11 |
| 77 (addr_hit[76] & ((|(4'... | Covered | T1,T4,T5 |
| 76 (addr_hit[75] & ((|(4'... | Covered | T5,T17,T11 |
| 75 (addr_hit[74] & ((|(4'... | Covered | T1,T4,T5 |
| 74 (addr_hit[73] & ((|(4'... | Covered | T4,T17,T11 |
| 73 (addr_hit[72] & ((|(4'... | Covered | T5,T17,T11 |
| 72 (addr_hit[71] & ((|(4'... | Covered | T4,T5,T17 |
| 71 (addr_hit[70] & ((|(4'... | Covered | T4,T5,T17 |
| 70 (addr_hit[69] & ((|(4'... | Covered | T1,T5,T17 |
| 69 (addr_hit[68] & ((|(4'... | Covered | T5,T17,T11 |
| 68 (addr_hit[67] & ((|(4'... | Covered | T17,T11,T27 |
| 67 (addr_hit[66] & ((|(4'... | Covered | T4,T17,T11 |
| 66 (addr_hit[65] & ((|(4'... | Covered | T4,T5,T17 |
| 65 (addr_hit[64] & ((|(4'... | Covered | T17,T11,T27 |
| 64 (addr_hit[63] & ((|(4'... | Covered | T1,T5,T17 |
| 63 (addr_hit[62] & ((|(4'... | Covered | T1,T4,T5 |
| 62 (addr_hit[61] & ((|(4'... | Covered | T5,T17,T11 |
| 61 (addr_hit[60] & ((|(4'... | Covered | T5,T17,T11 |
| 60 (addr_hit[59] & ((|(4'... | Covered | T1,T4,T5 |
| 59 (addr_hit[58] & ((|(4'... | Covered | T4,T17,T11 |
| 58 (addr_hit[57] & ((|(4'... | Covered | T1,T17,T11 |
| 57 (addr_hit[56] & ((|(4'... | Covered | T1,T4,T5 |
| 56 (addr_hit[55] & ((|(4'... | Covered | T5,T17,T11 |
| 55 (addr_hit[54] & ((|(4'... | Covered | T1,T5,T17 |
| 54 (addr_hit[53] & ((|(4'... | Covered | T5,T17,T11 |
| 53 (addr_hit[52] & ((|(4'... | Covered | T1,T4,T17 |
| 52 (addr_hit[51] & ((|(4'... | Covered | T5,T17,T11 |
| 51 (addr_hit[50] & ((|(4'... | Covered | T4,T17,T11 |
| 50 (addr_hit[49] & ((|(4'... | Covered | T5,T17,T11 |
| 49 (addr_hit[48] & ((|(4'... | Covered | T5,T17,T11 |
| 48 (addr_hit[47] & ((|(4'... | Covered | T4,T5,T17 |
| 47 (addr_hit[46] & ((|(4'... | Covered | T5,T17,T11 |
| 46 (addr_hit[45] & ((|(4'... | Covered | T1,T5,T17 |
| 45 (addr_hit[44] & ((|(4'... | Covered | T4,T5,T17 |
| 44 (addr_hit[43] & ((|(4'... | Covered | T5,T17,T11 |
| 43 (addr_hit[42] & ((|(4'... | Covered | T5,T17,T11 |
| 42 (addr_hit[41] & ((|(4'... | Covered | T5,T17,T11 |
| 41 (addr_hit[40] & ((|(4'... | Covered | T5,T17,T11 |
| 40 (addr_hit[39] & ((|(4'... | Covered | T5,T17,T11 |
| 39 (addr_hit[38] & ((|(4'... | Covered | T5,T17,T11 |
| 38 (addr_hit[37] & ((|(4'... | Covered | T1,T5,T17 |
| 37 (addr_hit[36] & ((|(4'... | Covered | T4,T17,T11 |
| 36 (addr_hit[35] & ((|(4'... | Covered | T1,T5,T11 |
| 35 (addr_hit[34] & ((|(4'... | Covered | T4,T5,T17 |
| 34 (addr_hit[33] & ((|(4'... | Covered | T4,T5,T17 |
| 33 (addr_hit[32] & ((|(4'... | Covered | T4,T5,T17 |
| 32 (addr_hit[31] & ((|(4'... | Covered | T1,T17,T11 |
| 31 (addr_hit[30] & ((|(4'... | Covered | T5,T17,T11 |
| 30 (addr_hit[29] & ((|(4'... | Covered | T4,T5,T17 |
| 29 (addr_hit[28] & ((|(4'... | Covered | T4,T5,T11 |
| 28 (addr_hit[27] & ((|(4'... | Covered | T4,T5,T17 |
| 27 (addr_hit[26] & ((|(4'... | Covered | T1,T5,T17 |
| 26 (addr_hit[25] & ((|(4'... | Covered | T1,T5,T17 |
| 25 (addr_hit[24] & ((|(4'... | Covered | T4,T5,T17 |
| 24 (addr_hit[23] & ((|(4'... | Covered | T5,T17,T11 |
| 23 (addr_hit[22] & ((|(4'... | Covered | T5,T17,T11 |
| 22 (addr_hit[21] & ((|(4'... | Covered | T4,T5,T17 |
| 21 (addr_hit[20] & ((|(4'... | Covered | T4,T5,T17 |
| 20 (addr_hit[19] & ((|(4'... | Covered | T1,T4,T5 |
| 19 (addr_hit[18] & ((|(4'... | Covered | T1,T4,T5 |
| 18 (addr_hit[17] & ((|(4'... | Covered | T1,T5,T17 |
| 17 (addr_hit[16] & ((|(4'... | Covered | T5,T17,T11 |
| 16 (addr_hit[15] & ((|(4'... | Covered | T4,T17,T11 |
| 15 (addr_hit[14] & ((|(4'... | Covered | T5,T17,T11 |
| 14 (addr_hit[13] & ((|(4'... | Covered | T4,T5,T17 |
| 13 (addr_hit[12] & ((|(4'... | Covered | T5,T17,T11 |
| 12 (addr_hit[11] & ((|(4'... | Covered | T17,T11,T27 |
| 11 (addr_hit[10] & ((|(4'... | Covered | T1,T4,T17 |
| 10 (addr_hit[9] & ((|(4'b... | Covered | T4,T5,T17 |
| 9 (addr_hit[8] & ((|(4'b... | Covered | T4,T5,T17 |
| 8 (addr_hit[7] & ((|(4'b... | Covered | T5,T17,T11 |
| 7 (addr_hit[6] & ((|(4'b... | Covered | T1,T4,T5 |
| 6 (addr_hit[5] & ((|(4'b... | Covered | T5,T17,T11 |
| 5 (addr_hit[4] & ((|(4'b... | Covered | T5,T17,T11 |
| 4 (addr_hit[3] & ((|(4'b... | Covered | T4,T5,T17 |
| 3 (addr_hit[2] & ((|(4'b... | Covered | T5,T17,T11 |
| 2 (addr_hit[1] & ((|(4'b... | Covered | T5,T17,T11 |
| 1 (addr_hit[0] & ((|(4'b... | Covered | T1,T2,T3 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |