CLKMGR Simulation Results

Thursday April 18 2024 19:02:27 UTC

GitHub Revision: d3942ca074

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 25859338206198790995583629940734127463564215244480240139741775999763579929205

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.460s 260.400us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.930s 48.601us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 0.970s 64.019us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 9.520s 1.358ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 2.130s 209.681us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 1.970s 105.962us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 0.970s 64.019us 20 20 100.00
clkmgr_csr_aliasing 2.130s 209.681us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.000s 122.614us 50 50 100.00
V2 trans_enables clkmgr_trans 1.240s 134.070us 50 50 100.00
V2 extclk clkmgr_extclk 1.260s 188.631us 50 50 100.00
V2 clk_status clkmgr_clk_status 1.070s 173.249us 50 50 100.00
V2 jitter clkmgr_smoke 1.460s 260.400us 50 50 100.00
V2 frequency clkmgr_frequency 19.040s 2.483ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 16.560s 2.301ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 19.040s 2.483ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.430m 12.198ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.900s 132.836us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.710s 321.366us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 5.220s 825.474us 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 5.220s 825.474us 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.930s 48.601us 5 5 100.00
clkmgr_csr_rw 0.970s 64.019us 20 20 100.00
clkmgr_csr_aliasing 2.130s 209.681us 5 5 100.00
clkmgr_same_csr_outstanding 1.780s 193.347us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.930s 48.601us 5 5 100.00
clkmgr_csr_rw 0.970s 64.019us 20 20 100.00
clkmgr_csr_aliasing 2.130s 209.681us 5 5 100.00
clkmgr_same_csr_outstanding 1.780s 193.347us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 4.250s 1.116ms 5 5 100.00
clkmgr_tl_intg_err 3.450s 435.762us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 2.730s 528.091us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 2.730s 528.091us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 2.730s 528.091us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 2.730s 528.091us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 6.170s 1.710ms 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 3.450s 435.762us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 19.040s 2.483ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 16.560s 2.301ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 2.730s 528.091us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.380s 205.726us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.680s 328.546us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.170s 150.519us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.330s 181.615us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.280s 184.148us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 0.970s 64.019us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 4.250s 1.116ms 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 0.970s 64.019us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 0.970s 64.019us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 4.250s 1.116ms 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 7.340s 1.399ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 36.853m 493.814ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.47 99.11 95.67 100.00 100.00 98.71 97.01 98.80

Past Results