Line Coverage for Module :
prim_reg_cdc_arb ( parameter DataWidth=4,ResetVal=9,DstWrReq=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 50 | 47 | 94.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
ALWAYS | 111 | 3 | 3 | 100.00 |
ALWAYS | 121 | 6 | 6 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
ALWAYS | 139 | 6 | 6 | 100.00 |
ALWAYS | 155 | 10 | 9 | 90.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
ALWAYS | 187 | 19 | 17 | 89.47 |
CONT_ASSIGN | 228 | 1 | 1 | 100.00 |
CONT_ASSIGN | 243 | 1 | 1 | 100.00 |
CONT_ASSIGN | 244 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
100 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
114 |
1 |
1 |
121 |
1 |
1 |
122 |
1 |
1 |
123 |
1 |
1 |
128 |
1 |
1 |
129 |
1 |
1 |
132 |
1 |
1 |
|
|
|
MISSING_ELSE |
135 |
1 |
1 |
139 |
1 |
1 |
140 |
1 |
1 |
141 |
1 |
1 |
142 |
1 |
1 |
143 |
1 |
1 |
144 |
1 |
1 |
|
|
|
MISSING_ELSE |
155 |
1 |
1 |
156 |
1 |
1 |
157 |
1 |
1 |
158 |
1 |
1 |
159 |
1 |
1 |
160 |
1 |
1 |
161 |
1 |
1 |
162 |
0 |
1 |
163 |
1 |
1 |
164 |
1 |
1 |
|
|
|
MISSING_ELSE |
183 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
195 |
1 |
1 |
197 |
1 |
1 |
199 |
1 |
1 |
200 |
1 |
1 |
202 |
1 |
1 |
203 |
1 |
1 |
204 |
1 |
1 |
205 |
0 |
1 |
206 |
0 |
1 |
207 |
1 |
1 |
210 |
1 |
1 |
211 |
1 |
1 |
|
|
|
MISSING_ELSE |
216 |
1 |
1 |
217 |
1 |
1 |
218 |
1 |
1 |
|
|
|
MISSING_ELSE |
228 |
1 |
1 |
243 |
1 |
1 |
244 |
1 |
1 |
Line Coverage for Module :
prim_reg_cdc_arb ( parameter DataWidth=20,ResetVal,DstWrReq=0 + DataWidth=18,ResetVal=118010,DstWrReq=0 + DataWidth=16,ResetVal=28290,DstWrReq=0 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 100 | 0 | 0 | |
CONT_ASSIGN | 283 | 1 | 1 | 100.00 |
CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
CONT_ASSIGN | 299 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
100 |
|
unreachable |
283 |
1 |
1 |
284 |
1 |
1 |
299 |
|
unreachable |
Cond Coverage for Module :
prim_reg_cdc_arb ( parameter DataWidth=4,ResetVal=9,DstWrReq=1 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 43 | 36 | 83.72 |
Logical | 43 | 36 | 83.72 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 100
EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
------1----- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T1,T2 |
1 | 1 | Covered | T5,T6,T4 |
LINE 100
SUB-EXPRESSION (dst_qs_o != dst_ds_i)
-----------1----------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T5,T6,T4 |
LINE 123
EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
----------1--------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T4 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T7,T8 |
LINE 129
EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
----1---- ------------2------------ -------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T5,T6,T4 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T5,T6,T4 |
1 | 1 | 1 | Covered | T7,T8 |
LINE 135
EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
----------1--------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T4 |
0 | 1 | Covered | T5,T6,T4 |
1 | 0 | Covered | T7,T8 |
LINE 157
EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
------------1------------ ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T5,T6,T4 |
1 | 1 | Covered | T5,T6,T4 |
LINE 159
EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
---------1-------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T5,T6,T4 |
LINE 161
EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
-----------1----------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T5,T6,T4 |
1 | 1 | Not Covered | |
LINE 183
EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
----------1--------- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T8 |
1 | 0 | Covered | T5,T6,T4 |
1 | 1 | Covered | T5,T6,T4 |
LINE 207
EXPRESSION (dst_qs_o != dst_qs_i)
-----------1----------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T1,T2,T3 |
LINE 228
EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
-----------1----------- ----------2--------- ----------3---------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T5,T6,T4 |
0 | 0 | 1 | Covered | T1,T2,T3 |
0 | 1 | 0 | Covered | T5,T6,T4 |
1 | 0 | 0 | Covered | T5,T6,T4 |
LINE 243
EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
---------1-------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T5,T6,T4 |
LINE 243
SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T6,T4 |
LINE 244
EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
---------1-------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T5,T6,T4 |
1 | 1 | Covered | T1,T2,T3 |
LINE 244
SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_reg_cdc_arb ( parameter DataWidth=20,ResetVal,DstWrReq=0 + DataWidth=18,ResetVal=118010,DstWrReq=0 + DataWidth=16,ResetVal=28290,DstWrReq=0 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 3 | 2 | 66.67 |
Logical | 3 | 2 | 66.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 100
EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
------1----- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T4 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 100
SUB-EXPRESSION (dst_qs_o != dst_ds_i)
-----------1----------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T5,T6,T4 |
Branch Coverage for Module :
prim_reg_cdc_arb
| Line No. | Total | Covered | Percent |
Branches |
|
23 |
20 |
86.96 |
IF |
111 |
2 |
2 |
100.00 |
IF |
121 |
4 |
4 |
100.00 |
IF |
139 |
4 |
4 |
100.00 |
IF |
155 |
6 |
5 |
83.33 |
CASE |
197 |
7 |
5 |
71.43 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 111 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T4 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 121 if ((!rst_dst_ni))
-2-: 123 if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d))
-3-: 129 if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T4 |
0 |
1 |
- |
Covered |
T7,T8 |
0 |
0 |
1 |
Covered |
T7,T8 |
0 |
0 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 139 if ((!rst_dst_ni))
-2-: 141 if (gen_wr_req.dst_lat_d)
-3-: 143 if (gen_wr_req.dst_lat_q)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T4 |
0 |
1 |
- |
Covered |
T5,T6,T4 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 155 if ((!rst_dst_ni))
-2-: 157 if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack))
-3-: 159 if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d))
-4-: 161 if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d))
-5-: 163 if (gen_wr_req.dst_lat_q)
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T5,T6,T4 |
0 |
1 |
- |
- |
- |
Covered |
T5,T6,T4 |
0 |
0 |
1 |
- |
- |
Covered |
T5,T6,T4 |
0 |
0 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
0 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 197 case (gen_wr_req.state_q)
-2-: 200 if (gen_wr_req.dst_req)
-3-: 204 if (dst_update)
-4-: 207 if ((dst_qs_o != dst_qs_i))
-5-: 217 if (gen_wr_req.dst_update_ack)
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
StIdle |
1 |
- |
- |
- |
Covered |
T5,T6,T4 |
StIdle |
0 |
1 |
- |
- |
Not Covered |
|
StIdle |
0 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
StIdle |
0 |
0 |
0 |
- |
Covered |
T5,T6,T4 |
StWait |
- |
- |
- |
1 |
Covered |
T5,T6,T4 |
StWait |
- |
- |
- |
0 |
Covered |
T5,T6,T4 |
default |
- |
- |
- |
- |
Not Covered |
|
Assert Coverage for Module :
prim_reg_cdc_arb
Assertion Details
gen_wr_req.DstUpdateReqCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1494051136 |
0 |
0 |
5050 |
gen_wr_req.HwIdSelCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1494051136 |
5760 |
0 |
0 |
T1 |
3083676 |
105 |
0 |
0 |
T2 |
1746036 |
65 |
0 |
0 |
T3 |
0 |
10 |
0 |
0 |
T9 |
0 |
5 |
0 |
0 |
T10 |
0 |
5 |
0 |
0 |
T11 |
0 |
5 |
0 |
0 |
T12 |
0 |
160 |
0 |
0 |
T13 |
0 |
15 |
0 |
0 |
T14 |
0 |
10 |
0 |
0 |
T15 |
0 |
15 |
0 |
0 |
T16 |
31577 |
0 |
0 |
0 |
T17 |
8395 |
0 |
0 |
0 |
T18 |
407726 |
0 |
0 |
0 |
T19 |
34605 |
0 |
0 |
0 |
T20 |
5551 |
0 |
0 |
0 |
T21 |
91865 |
0 |
0 |
0 |
T22 |
23630 |
0 |
0 |
0 |
T23 |
15681 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 50 | 45 | 90.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
ALWAYS | 111 | 3 | 3 | 100.00 |
ALWAYS | 121 | 6 | 4 | 66.67 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
ALWAYS | 139 | 6 | 6 | 100.00 |
ALWAYS | 155 | 10 | 9 | 90.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
ALWAYS | 187 | 19 | 17 | 89.47 |
CONT_ASSIGN | 228 | 1 | 1 | 100.00 |
CONT_ASSIGN | 243 | 1 | 1 | 100.00 |
CONT_ASSIGN | 244 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
100 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
114 |
1 |
1 |
121 |
1 |
1 |
122 |
1 |
1 |
123 |
1 |
1 |
128 |
0 |
1 |
129 |
1 |
1 |
132 |
0 |
1 |
|
|
|
MISSING_ELSE |
135 |
1 |
1 |
139 |
1 |
1 |
140 |
1 |
1 |
141 |
1 |
1 |
142 |
1 |
1 |
143 |
1 |
1 |
144 |
1 |
1 |
|
|
|
MISSING_ELSE |
155 |
1 |
1 |
156 |
1 |
1 |
157 |
1 |
1 |
158 |
1 |
1 |
159 |
1 |
1 |
160 |
1 |
1 |
161 |
1 |
1 |
162 |
0 |
1 |
163 |
1 |
1 |
164 |
1 |
1 |
|
|
|
MISSING_ELSE |
183 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
195 |
1 |
1 |
197 |
1 |
1 |
199 |
1 |
1 |
200 |
1 |
1 |
202 |
1 |
1 |
203 |
1 |
1 |
204 |
1 |
1 |
205 |
0 |
1 |
206 |
0 |
1 |
207 |
1 |
1 |
210 |
1 |
1 |
211 |
1 |
1 |
|
|
|
MISSING_ELSE |
216 |
1 |
1 |
217 |
1 |
1 |
218 |
1 |
1 |
|
|
|
MISSING_ELSE |
228 |
1 |
1 |
243 |
1 |
1 |
244 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb
| Total | Covered | Percent |
Conditions | 42 | 32 | 76.19 |
Logical | 42 | 32 | 76.19 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 100
EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
------1----- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T1,T2 |
1 | 1 | Covered | T5,T6,T4 |
LINE 100
SUB-EXPRESSION (dst_qs_o != dst_ds_i)
-----------1----------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T5,T6,T4 |
LINE 123
EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
----------1--------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T4 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 129
EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
----1---- ------------2------------ -------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T5,T6,T4 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T5,T6,T4 |
1 | 1 | 1 | Not Covered | |
LINE 135
EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
----------1--------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T4 |
0 | 1 | Covered | T5,T6,T4 |
1 | 0 | Not Covered | |
LINE 157
EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
------------1------------ ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T5,T6,T4 |
1 | 1 | Covered | T5,T6,T4 |
LINE 159
EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
---------1-------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T5,T6,T4 |
LINE 161
EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
-----------1----------- ----------2---------
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Covered | T5,T6,T4 |
1 | 1 | Not Covered | |
LINE 183
EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
----------1--------- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T5,T6,T4 |
1 | 1 | Covered | T5,T6,T4 |
LINE 207
EXPRESSION (dst_qs_o != dst_qs_i)
-----------1----------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T1,T2,T3 |
LINE 228
EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
-----------1----------- ----------2--------- ----------3---------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T5,T6,T4 |
0 | 0 | 1 | Covered | T1,T2,T3 |
0 | 1 | 0 | Covered | T5,T6,T4 |
1 | 0 | 0 | Covered | T5,T6,T4 |
LINE 243
EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
---------1-------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T5,T6,T4 |
LINE 243
SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T6,T4 |
LINE 244
EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
---------1-------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T5,T6,T4 |
1 | 1 | Covered | T1,T2,T3 |
LINE 244
SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb
| Line No. | Total | Covered | Percent |
Branches |
|
23 |
18 |
78.26 |
IF |
111 |
2 |
2 |
100.00 |
IF |
121 |
4 |
2 |
50.00 |
IF |
139 |
4 |
4 |
100.00 |
IF |
155 |
6 |
5 |
83.33 |
CASE |
197 |
7 |
5 |
71.43 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 111 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T4 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 121 if ((!rst_dst_ni))
-2-: 123 if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d))
-3-: 129 if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T4 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 139 if ((!rst_dst_ni))
-2-: 141 if (gen_wr_req.dst_lat_d)
-3-: 143 if (gen_wr_req.dst_lat_q)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T4 |
0 |
1 |
- |
Covered |
T5,T6,T4 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 155 if ((!rst_dst_ni))
-2-: 157 if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack))
-3-: 159 if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d))
-4-: 161 if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d))
-5-: 163 if (gen_wr_req.dst_lat_q)
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T5,T6,T4 |
0 |
1 |
- |
- |
- |
Covered |
T5,T6,T4 |
0 |
0 |
1 |
- |
- |
Covered |
T5,T6,T4 |
0 |
0 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
0 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 197 case (gen_wr_req.state_q)
-2-: 200 if (gen_wr_req.dst_req)
-3-: 204 if (dst_update)
-4-: 207 if ((dst_qs_o != dst_qs_i))
-5-: 217 if (gen_wr_req.dst_update_ack)
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
StIdle |
1 |
- |
- |
- |
Covered |
T5,T6,T4 |
StIdle |
0 |
1 |
- |
- |
Not Covered |
|
StIdle |
0 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
StIdle |
0 |
0 |
0 |
- |
Covered |
T5,T6,T4 |
StWait |
- |
- |
- |
1 |
Covered |
T5,T6,T4 |
StWait |
- |
- |
- |
0 |
Covered |
T5,T6,T4 |
default |
- |
- |
- |
- |
Not Covered |
|
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb
Assertion Details
gen_wr_req.DstUpdateReqCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449209565 |
0 |
0 |
1010 |
gen_wr_req.HwIdSelCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449209565 |
1152 |
0 |
0 |
T1 |
931869 |
21 |
0 |
0 |
T2 |
525480 |
13 |
0 |
0 |
T3 |
0 |
2 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
32 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
2 |
0 |
0 |
T15 |
0 |
3 |
0 |
0 |
T16 |
9356 |
0 |
0 |
0 |
T17 |
2574 |
0 |
0 |
0 |
T18 |
131109 |
0 |
0 |
0 |
T19 |
10540 |
0 |
0 |
0 |
T20 |
1705 |
0 |
0 |
0 |
T21 |
27364 |
0 |
0 |
0 |
T22 |
6997 |
0 |
0 |
0 |
T23 |
4794 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 50 | 45 | 90.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
ALWAYS | 111 | 3 | 3 | 100.00 |
ALWAYS | 121 | 6 | 4 | 66.67 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
ALWAYS | 139 | 6 | 6 | 100.00 |
ALWAYS | 155 | 10 | 9 | 90.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
ALWAYS | 187 | 19 | 17 | 89.47 |
CONT_ASSIGN | 228 | 1 | 1 | 100.00 |
CONT_ASSIGN | 243 | 1 | 1 | 100.00 |
CONT_ASSIGN | 244 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
100 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
114 |
1 |
1 |
121 |
1 |
1 |
122 |
1 |
1 |
123 |
1 |
1 |
128 |
0 |
1 |
129 |
1 |
1 |
132 |
0 |
1 |
|
|
|
MISSING_ELSE |
135 |
1 |
1 |
139 |
1 |
1 |
140 |
1 |
1 |
141 |
1 |
1 |
142 |
1 |
1 |
143 |
1 |
1 |
144 |
1 |
1 |
|
|
|
MISSING_ELSE |
155 |
1 |
1 |
156 |
1 |
1 |
157 |
1 |
1 |
158 |
1 |
1 |
159 |
1 |
1 |
160 |
1 |
1 |
161 |
1 |
1 |
162 |
0 |
1 |
163 |
1 |
1 |
164 |
1 |
1 |
|
|
|
MISSING_ELSE |
183 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
195 |
1 |
1 |
197 |
1 |
1 |
199 |
1 |
1 |
200 |
1 |
1 |
202 |
1 |
1 |
203 |
1 |
1 |
204 |
1 |
1 |
205 |
0 |
1 |
206 |
0 |
1 |
207 |
1 |
1 |
210 |
1 |
1 |
211 |
1 |
1 |
|
|
|
MISSING_ELSE |
216 |
1 |
1 |
217 |
1 |
1 |
218 |
1 |
1 |
|
|
|
MISSING_ELSE |
228 |
1 |
1 |
243 |
1 |
1 |
244 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb
| Total | Covered | Percent |
Conditions | 42 | 32 | 76.19 |
Logical | 42 | 32 | 76.19 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 100
EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
------1----- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T1,T2 |
1 | 1 | Covered | T5,T6,T4 |
LINE 100
SUB-EXPRESSION (dst_qs_o != dst_ds_i)
-----------1----------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T5,T6,T4 |
LINE 123
EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
----------1--------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T4 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 129
EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
----1---- ------------2------------ -------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T5,T6,T4 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T5,T6,T4 |
1 | 1 | 1 | Not Covered | |
LINE 135
EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
----------1--------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T4 |
0 | 1 | Covered | T5,T6,T4 |
1 | 0 | Not Covered | |
LINE 157
EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
------------1------------ ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T5,T6,T4 |
1 | 1 | Covered | T5,T6,T4 |
LINE 159
EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
---------1-------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T5,T6,T4 |
LINE 161
EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
-----------1----------- ----------2---------
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Covered | T5,T6,T4 |
1 | 1 | Not Covered | |
LINE 183
EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
----------1--------- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T5,T6,T4 |
1 | 1 | Covered | T5,T6,T4 |
LINE 207
EXPRESSION (dst_qs_o != dst_qs_i)
-----------1----------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T1,T2,T3 |
LINE 228
EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
-----------1----------- ----------2--------- ----------3---------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T5,T6,T4 |
0 | 0 | 1 | Covered | T1,T2,T3 |
0 | 1 | 0 | Covered | T5,T6,T4 |
1 | 0 | 0 | Covered | T5,T6,T4 |
LINE 243
EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
---------1-------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T5,T6,T4 |
LINE 243
SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T6,T4 |
LINE 244
EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
---------1-------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T5,T6,T4 |
1 | 1 | Covered | T1,T2,T3 |
LINE 244
SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb
| Line No. | Total | Covered | Percent |
Branches |
|
23 |
18 |
78.26 |
IF |
111 |
2 |
2 |
100.00 |
IF |
121 |
4 |
2 |
50.00 |
IF |
139 |
4 |
4 |
100.00 |
IF |
155 |
6 |
5 |
83.33 |
CASE |
197 |
7 |
5 |
71.43 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 111 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T4 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 121 if ((!rst_dst_ni))
-2-: 123 if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d))
-3-: 129 if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T4 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 139 if ((!rst_dst_ni))
-2-: 141 if (gen_wr_req.dst_lat_d)
-3-: 143 if (gen_wr_req.dst_lat_q)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T4 |
0 |
1 |
- |
Covered |
T5,T6,T4 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 155 if ((!rst_dst_ni))
-2-: 157 if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack))
-3-: 159 if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d))
-4-: 161 if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d))
-5-: 163 if (gen_wr_req.dst_lat_q)
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T5,T6,T4 |
0 |
1 |
- |
- |
- |
Covered |
T5,T6,T4 |
0 |
0 |
1 |
- |
- |
Covered |
T5,T6,T4 |
0 |
0 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
0 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 197 case (gen_wr_req.state_q)
-2-: 200 if (gen_wr_req.dst_req)
-3-: 204 if (dst_update)
-4-: 207 if ((dst_qs_o != dst_qs_i))
-5-: 217 if (gen_wr_req.dst_update_ack)
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
StIdle |
1 |
- |
- |
- |
Covered |
T5,T6,T4 |
StIdle |
0 |
1 |
- |
- |
Not Covered |
|
StIdle |
0 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
StIdle |
0 |
0 |
0 |
- |
Covered |
T5,T6,T4 |
StWait |
- |
- |
- |
1 |
Covered |
T5,T6,T4 |
StWait |
- |
- |
- |
0 |
Covered |
T5,T6,T4 |
default |
- |
- |
- |
- |
Not Covered |
|
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb
Assertion Details
gen_wr_req.DstUpdateReqCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
223800382 |
0 |
0 |
1010 |
gen_wr_req.HwIdSelCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
223800382 |
1152 |
0 |
0 |
T1 |
466684 |
21 |
0 |
0 |
T2 |
262760 |
13 |
0 |
0 |
T3 |
0 |
2 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
32 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
2 |
0 |
0 |
T15 |
0 |
3 |
0 |
0 |
T16 |
5198 |
0 |
0 |
0 |
T17 |
1234 |
0 |
0 |
0 |
T18 |
49656 |
0 |
0 |
0 |
T19 |
5210 |
0 |
0 |
0 |
T20 |
813 |
0 |
0 |
0 |
T21 |
14876 |
0 |
0 |
0 |
T22 |
3898 |
0 |
0 |
0 |
T23 |
2330 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 50 | 45 | 90.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
ALWAYS | 111 | 3 | 3 | 100.00 |
ALWAYS | 121 | 6 | 4 | 66.67 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
ALWAYS | 139 | 6 | 6 | 100.00 |
ALWAYS | 155 | 10 | 9 | 90.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
ALWAYS | 187 | 19 | 17 | 89.47 |
CONT_ASSIGN | 228 | 1 | 1 | 100.00 |
CONT_ASSIGN | 243 | 1 | 1 | 100.00 |
CONT_ASSIGN | 244 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
100 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
114 |
1 |
1 |
121 |
1 |
1 |
122 |
1 |
1 |
123 |
1 |
1 |
128 |
0 |
1 |
129 |
1 |
1 |
132 |
0 |
1 |
|
|
|
MISSING_ELSE |
135 |
1 |
1 |
139 |
1 |
1 |
140 |
1 |
1 |
141 |
1 |
1 |
142 |
1 |
1 |
143 |
1 |
1 |
144 |
1 |
1 |
|
|
|
MISSING_ELSE |
155 |
1 |
1 |
156 |
1 |
1 |
157 |
1 |
1 |
158 |
1 |
1 |
159 |
1 |
1 |
160 |
1 |
1 |
161 |
1 |
1 |
162 |
0 |
1 |
163 |
1 |
1 |
164 |
1 |
1 |
|
|
|
MISSING_ELSE |
183 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
195 |
1 |
1 |
197 |
1 |
1 |
199 |
1 |
1 |
200 |
1 |
1 |
202 |
1 |
1 |
203 |
1 |
1 |
204 |
1 |
1 |
205 |
0 |
1 |
206 |
0 |
1 |
207 |
1 |
1 |
210 |
1 |
1 |
211 |
1 |
1 |
|
|
|
MISSING_ELSE |
216 |
1 |
1 |
217 |
1 |
1 |
218 |
1 |
1 |
|
|
|
MISSING_ELSE |
228 |
1 |
1 |
243 |
1 |
1 |
244 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb
| Total | Covered | Percent |
Conditions | 42 | 32 | 76.19 |
Logical | 42 | 32 | 76.19 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 100
EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
------1----- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T1,T2 |
1 | 1 | Covered | T5,T6,T4 |
LINE 100
SUB-EXPRESSION (dst_qs_o != dst_ds_i)
-----------1----------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T5,T6,T4 |
LINE 123
EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
----------1--------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T4 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 129
EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
----1---- ------------2------------ -------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T5,T6,T4 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T5,T6,T4 |
1 | 1 | 1 | Not Covered | |
LINE 135
EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
----------1--------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T4 |
0 | 1 | Covered | T5,T6,T4 |
1 | 0 | Not Covered | |
LINE 157
EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
------------1------------ ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T5,T6,T4 |
1 | 1 | Covered | T5,T6,T4 |
LINE 159
EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
---------1-------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T5,T6,T4 |
LINE 161
EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
-----------1----------- ----------2---------
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Covered | T5,T6,T4 |
1 | 1 | Not Covered | |
LINE 183
EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
----------1--------- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T5,T6,T4 |
1 | 1 | Covered | T5,T6,T4 |
LINE 207
EXPRESSION (dst_qs_o != dst_qs_i)
-----------1----------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T1,T2,T3 |
LINE 228
EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
-----------1----------- ----------2--------- ----------3---------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T5,T6,T4 |
0 | 0 | 1 | Covered | T1,T2,T3 |
0 | 1 | 0 | Covered | T5,T6,T4 |
1 | 0 | 0 | Covered | T5,T6,T4 |
LINE 243
EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
---------1-------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T5,T6,T4 |
LINE 243
SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T6,T4 |
LINE 244
EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
---------1-------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T5,T6,T4 |
1 | 1 | Covered | T1,T2,T3 |
LINE 244
SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb
| Line No. | Total | Covered | Percent |
Branches |
|
23 |
18 |
78.26 |
IF |
111 |
2 |
2 |
100.00 |
IF |
121 |
4 |
2 |
50.00 |
IF |
139 |
4 |
4 |
100.00 |
IF |
155 |
6 |
5 |
83.33 |
CASE |
197 |
7 |
5 |
71.43 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 111 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T4 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 121 if ((!rst_dst_ni))
-2-: 123 if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d))
-3-: 129 if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T4 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 139 if ((!rst_dst_ni))
-2-: 141 if (gen_wr_req.dst_lat_d)
-3-: 143 if (gen_wr_req.dst_lat_q)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T4 |
0 |
1 |
- |
Covered |
T5,T6,T4 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 155 if ((!rst_dst_ni))
-2-: 157 if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack))
-3-: 159 if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d))
-4-: 161 if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d))
-5-: 163 if (gen_wr_req.dst_lat_q)
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T5,T6,T4 |
0 |
1 |
- |
- |
- |
Covered |
T5,T6,T4 |
0 |
0 |
1 |
- |
- |
Covered |
T5,T6,T4 |
0 |
0 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
0 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 197 case (gen_wr_req.state_q)
-2-: 200 if (gen_wr_req.dst_req)
-3-: 204 if (dst_update)
-4-: 207 if ((dst_qs_o != dst_qs_i))
-5-: 217 if (gen_wr_req.dst_update_ack)
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
StIdle |
1 |
- |
- |
- |
Covered |
T5,T6,T4 |
StIdle |
0 |
1 |
- |
- |
Not Covered |
|
StIdle |
0 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
StIdle |
0 |
0 |
0 |
- |
Covered |
T5,T6,T4 |
StWait |
- |
- |
- |
1 |
Covered |
T5,T6,T4 |
StWait |
- |
- |
- |
0 |
Covered |
T5,T6,T4 |
default |
- |
- |
- |
- |
Not Covered |
|
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb
Assertion Details
gen_wr_req.DstUpdateReqCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479031968 |
0 |
0 |
1010 |
gen_wr_req.HwIdSelCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479031968 |
1152 |
0 |
0 |
T1 |
980929 |
21 |
0 |
0 |
T2 |
558192 |
13 |
0 |
0 |
T3 |
0 |
2 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
32 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
2 |
0 |
0 |
T15 |
0 |
3 |
0 |
0 |
T16 |
9746 |
0 |
0 |
0 |
T17 |
2682 |
0 |
0 |
0 |
T18 |
136576 |
0 |
0 |
0 |
T19 |
10980 |
0 |
0 |
0 |
T20 |
1775 |
0 |
0 |
0 |
T21 |
28506 |
0 |
0 |
0 |
T22 |
7289 |
0 |
0 |
0 |
T23 |
4995 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 50 | 45 | 90.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
ALWAYS | 111 | 3 | 3 | 100.00 |
ALWAYS | 121 | 6 | 4 | 66.67 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
ALWAYS | 139 | 6 | 6 | 100.00 |
ALWAYS | 155 | 10 | 9 | 90.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
ALWAYS | 187 | 19 | 17 | 89.47 |
CONT_ASSIGN | 228 | 1 | 1 | 100.00 |
CONT_ASSIGN | 243 | 1 | 1 | 100.00 |
CONT_ASSIGN | 244 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
100 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
114 |
1 |
1 |
121 |
1 |
1 |
122 |
1 |
1 |
123 |
1 |
1 |
128 |
0 |
1 |
129 |
1 |
1 |
132 |
0 |
1 |
|
|
|
MISSING_ELSE |
135 |
1 |
1 |
139 |
1 |
1 |
140 |
1 |
1 |
141 |
1 |
1 |
142 |
1 |
1 |
143 |
1 |
1 |
144 |
1 |
1 |
|
|
|
MISSING_ELSE |
155 |
1 |
1 |
156 |
1 |
1 |
157 |
1 |
1 |
158 |
1 |
1 |
159 |
1 |
1 |
160 |
1 |
1 |
161 |
1 |
1 |
162 |
0 |
1 |
163 |
1 |
1 |
164 |
1 |
1 |
|
|
|
MISSING_ELSE |
183 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
195 |
1 |
1 |
197 |
1 |
1 |
199 |
1 |
1 |
200 |
1 |
1 |
202 |
1 |
1 |
203 |
1 |
1 |
204 |
1 |
1 |
205 |
0 |
1 |
206 |
0 |
1 |
207 |
1 |
1 |
210 |
1 |
1 |
211 |
1 |
1 |
|
|
|
MISSING_ELSE |
216 |
1 |
1 |
217 |
1 |
1 |
218 |
1 |
1 |
|
|
|
MISSING_ELSE |
228 |
1 |
1 |
243 |
1 |
1 |
244 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb
| Total | Covered | Percent |
Conditions | 42 | 32 | 76.19 |
Logical | 42 | 32 | 76.19 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 100
EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
------1----- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T1,T2 |
1 | 1 | Covered | T5,T6,T4 |
LINE 100
SUB-EXPRESSION (dst_qs_o != dst_ds_i)
-----------1----------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T5,T6,T4 |
LINE 123
EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
----------1--------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T4 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 129
EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
----1---- ------------2------------ -------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T5,T6,T4 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T5,T6,T4 |
1 | 1 | 1 | Not Covered | |
LINE 135
EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
----------1--------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T4 |
0 | 1 | Covered | T5,T6,T4 |
1 | 0 | Not Covered | |
LINE 157
EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
------------1------------ ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T5,T6,T4 |
1 | 1 | Covered | T5,T6,T4 |
LINE 159
EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
---------1-------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T5,T6,T4 |
LINE 161
EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
-----------1----------- ----------2---------
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Covered | T5,T6,T4 |
1 | 1 | Not Covered | |
LINE 183
EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
----------1--------- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T5,T6,T4 |
1 | 1 | Covered | T5,T6,T4 |
LINE 207
EXPRESSION (dst_qs_o != dst_qs_i)
-----------1----------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T1,T2,T3 |
LINE 228
EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
-----------1----------- ----------2--------- ----------3---------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T5,T6,T4 |
0 | 0 | 1 | Covered | T1,T2,T3 |
0 | 1 | 0 | Covered | T5,T6,T4 |
1 | 0 | 0 | Covered | T5,T6,T4 |
LINE 243
EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
---------1-------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T5,T6,T4 |
LINE 243
SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T6,T4 |
LINE 244
EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
---------1-------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T5,T6,T4 |
1 | 1 | Covered | T1,T2,T3 |
LINE 244
SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb
| Line No. | Total | Covered | Percent |
Branches |
|
23 |
18 |
78.26 |
IF |
111 |
2 |
2 |
100.00 |
IF |
121 |
4 |
2 |
50.00 |
IF |
139 |
4 |
4 |
100.00 |
IF |
155 |
6 |
5 |
83.33 |
CASE |
197 |
7 |
5 |
71.43 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 111 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T4 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 121 if ((!rst_dst_ni))
-2-: 123 if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d))
-3-: 129 if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T4 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 139 if ((!rst_dst_ni))
-2-: 141 if (gen_wr_req.dst_lat_d)
-3-: 143 if (gen_wr_req.dst_lat_q)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T4 |
0 |
1 |
- |
Covered |
T5,T6,T4 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 155 if ((!rst_dst_ni))
-2-: 157 if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack))
-3-: 159 if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d))
-4-: 161 if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d))
-5-: 163 if (gen_wr_req.dst_lat_q)
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T5,T6,T4 |
0 |
1 |
- |
- |
- |
Covered |
T5,T6,T4 |
0 |
0 |
1 |
- |
- |
Covered |
T5,T6,T4 |
0 |
0 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
0 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 197 case (gen_wr_req.state_q)
-2-: 200 if (gen_wr_req.dst_req)
-3-: 204 if (dst_update)
-4-: 207 if ((dst_qs_o != dst_qs_i))
-5-: 217 if (gen_wr_req.dst_update_ack)
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
StIdle |
1 |
- |
- |
- |
Covered |
T5,T6,T4 |
StIdle |
0 |
1 |
- |
- |
Not Covered |
|
StIdle |
0 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
StIdle |
0 |
0 |
0 |
- |
Covered |
T5,T6,T4 |
StWait |
- |
- |
- |
1 |
Covered |
T5,T6,T4 |
StWait |
- |
- |
- |
0 |
Covered |
T5,T6,T4 |
default |
- |
- |
- |
- |
Not Covered |
|
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb
Assertion Details
gen_wr_req.DstUpdateReqCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
230109673 |
0 |
0 |
1010 |
gen_wr_req.HwIdSelCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
230109673 |
1152 |
0 |
0 |
T1 |
470853 |
21 |
0 |
0 |
T2 |
268224 |
13 |
0 |
0 |
T3 |
0 |
2 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
32 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
2 |
0 |
0 |
T15 |
0 |
3 |
0 |
0 |
T16 |
4678 |
0 |
0 |
0 |
T17 |
1288 |
0 |
0 |
0 |
T18 |
65557 |
0 |
0 |
0 |
T19 |
5270 |
0 |
0 |
0 |
T20 |
852 |
0 |
0 |
0 |
T21 |
13683 |
0 |
0 |
0 |
T22 |
3498 |
0 |
0 |
0 |
T23 |
2397 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 50 | 47 | 94.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
ALWAYS | 111 | 3 | 3 | 100.00 |
ALWAYS | 121 | 6 | 6 | 100.00 |
CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
ALWAYS | 139 | 6 | 6 | 100.00 |
ALWAYS | 155 | 10 | 9 | 90.00 |
CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
ALWAYS | 187 | 19 | 17 | 89.47 |
CONT_ASSIGN | 228 | 1 | 1 | 100.00 |
CONT_ASSIGN | 243 | 1 | 1 | 100.00 |
CONT_ASSIGN | 244 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
100 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
114 |
1 |
1 |
121 |
1 |
1 |
122 |
1 |
1 |
123 |
1 |
1 |
128 |
1 |
1 |
129 |
1 |
1 |
132 |
1 |
1 |
|
|
|
MISSING_ELSE |
135 |
1 |
1 |
139 |
1 |
1 |
140 |
1 |
1 |
141 |
1 |
1 |
142 |
1 |
1 |
143 |
1 |
1 |
144 |
1 |
1 |
|
|
|
MISSING_ELSE |
155 |
1 |
1 |
156 |
1 |
1 |
157 |
1 |
1 |
158 |
1 |
1 |
159 |
1 |
1 |
160 |
1 |
1 |
161 |
1 |
1 |
162 |
0 |
1 |
163 |
1 |
1 |
164 |
1 |
1 |
|
|
|
MISSING_ELSE |
183 |
1 |
1 |
187 |
1 |
1 |
188 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
195 |
1 |
1 |
197 |
1 |
1 |
199 |
1 |
1 |
200 |
1 |
1 |
202 |
1 |
1 |
203 |
1 |
1 |
204 |
1 |
1 |
205 |
0 |
1 |
206 |
0 |
1 |
207 |
1 |
1 |
210 |
1 |
1 |
211 |
1 |
1 |
|
|
|
MISSING_ELSE |
216 |
1 |
1 |
217 |
1 |
1 |
218 |
1 |
1 |
|
|
|
MISSING_ELSE |
228 |
1 |
1 |
243 |
1 |
1 |
244 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb
| Total | Covered | Percent |
Conditions | 42 | 36 | 85.71 |
Logical | 42 | 36 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 100
EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
------1----- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T4,T1,T2 |
1 | 1 | Covered | T5,T6,T4 |
LINE 100
SUB-EXPRESSION (dst_qs_o != dst_ds_i)
-----------1----------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T5,T6,T4 |
LINE 123
EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
----------1--------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T4 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T7,T8 |
LINE 129
EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
----1---- ------------2------------ -------3-------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T5,T6,T4 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T5,T6,T4 |
1 | 1 | 1 | Covered | T7,T8 |
LINE 135
EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
----------1--------- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T4 |
0 | 1 | Covered | T5,T6,T4 |
1 | 0 | Covered | T7,T8 |
LINE 157
EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
------------1------------ ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T5,T6,T4 |
1 | 1 | Covered | T5,T6,T4 |
LINE 159
EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
---------1-------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T5,T6,T4 |
LINE 161
EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
-----------1----------- ----------2---------
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | Covered | T5,T6,T4 |
1 | 1 | Not Covered | |
LINE 183
EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
----------1--------- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T8 |
1 | 0 | Covered | T5,T6,T4 |
1 | 1 | Covered | T5,T6,T4 |
LINE 207
EXPRESSION (dst_qs_o != dst_qs_i)
-----------1----------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T1,T2,T3 |
LINE 228
EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
-----------1----------- ----------2--------- ----------3---------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T5,T6,T4 |
0 | 0 | 1 | Covered | T1,T2,T3 |
0 | 1 | 0 | Covered | T5,T6,T4 |
1 | 0 | 0 | Covered | T5,T6,T4 |
LINE 243
EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
---------1-------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T5,T6,T4 |
LINE 243
SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T6,T4 |
LINE 244
EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
---------1-------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T5,T6,T4 |
1 | 1 | Covered | T1,T2,T3 |
LINE 244
SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T5,T6,T4 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb
| Line No. | Total | Covered | Percent |
Branches |
|
23 |
20 |
86.96 |
IF |
111 |
2 |
2 |
100.00 |
IF |
121 |
4 |
4 |
100.00 |
IF |
139 |
4 |
4 |
100.00 |
IF |
155 |
6 |
5 |
83.33 |
CASE |
197 |
7 |
5 |
71.43 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 111 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T4 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 121 if ((!rst_dst_ni))
-2-: 123 if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d))
-3-: 129 if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T4 |
0 |
1 |
- |
Covered |
T7,T8 |
0 |
0 |
1 |
Covered |
T7,T8 |
0 |
0 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 139 if ((!rst_dst_ni))
-2-: 141 if (gen_wr_req.dst_lat_d)
-3-: 143 if (gen_wr_req.dst_lat_q)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T4 |
0 |
1 |
- |
Covered |
T5,T6,T4 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 155 if ((!rst_dst_ni))
-2-: 157 if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack))
-3-: 159 if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d))
-4-: 161 if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d))
-5-: 163 if (gen_wr_req.dst_lat_q)
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
1 |
- |
- |
- |
- |
Covered |
T5,T6,T4 |
0 |
1 |
- |
- |
- |
Covered |
T5,T6,T4 |
0 |
0 |
1 |
- |
- |
Covered |
T5,T6,T4 |
0 |
0 |
0 |
1 |
- |
Not Covered |
|
0 |
0 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
0 |
0 |
Covered |
T5,T6,T4 |
LineNo. Expression
-1-: 197 case (gen_wr_req.state_q)
-2-: 200 if (gen_wr_req.dst_req)
-3-: 204 if (dst_update)
-4-: 207 if ((dst_qs_o != dst_qs_i))
-5-: 217 if (gen_wr_req.dst_update_ack)
Branches:
-1- | -2- | -3- | -4- | -5- | Status | Tests |
StIdle |
1 |
- |
- |
- |
Covered |
T5,T6,T4 |
StIdle |
0 |
1 |
- |
- |
Not Covered |
|
StIdle |
0 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
StIdle |
0 |
0 |
0 |
- |
Covered |
T5,T6,T4 |
StWait |
- |
- |
- |
1 |
Covered |
T5,T6,T4 |
StWait |
- |
- |
- |
0 |
Covered |
T5,T6,T4 |
default |
- |
- |
- |
- |
Not Covered |
|
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb
Assertion Details
gen_wr_req.DstUpdateReqCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111899548 |
0 |
0 |
1010 |
gen_wr_req.HwIdSelCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111899548 |
1152 |
0 |
0 |
T1 |
233341 |
21 |
0 |
0 |
T2 |
131380 |
13 |
0 |
0 |
T3 |
0 |
2 |
0 |
0 |
T9 |
0 |
1 |
0 |
0 |
T10 |
0 |
1 |
0 |
0 |
T11 |
0 |
1 |
0 |
0 |
T12 |
0 |
32 |
0 |
0 |
T13 |
0 |
3 |
0 |
0 |
T14 |
0 |
2 |
0 |
0 |
T15 |
0 |
3 |
0 |
0 |
T16 |
2599 |
0 |
0 |
0 |
T17 |
617 |
0 |
0 |
0 |
T18 |
24828 |
0 |
0 |
0 |
T19 |
2605 |
0 |
0 |
0 |
T20 |
406 |
0 |
0 |
0 |
T21 |
7436 |
0 |
0 |
0 |
T22 |
1948 |
0 |
0 |
0 |
T23 |
1165 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 100 | 0 | 0 | |
CONT_ASSIGN | 283 | 1 | 1 | 100.00 |
CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
CONT_ASSIGN | 299 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
100 |
|
unreachable |
283 |
1 |
1 |
284 |
1 |
1 |
299 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb
| Total | Covered | Percent |
Conditions | 3 | 2 | 66.67 |
Logical | 3 | 2 | 66.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 100
EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
------1----- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T4 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 100
SUB-EXPRESSION (dst_qs_o != dst_ds_i)
-----------1----------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T5,T6,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 100 | 0 | 0 | |
CONT_ASSIGN | 283 | 1 | 1 | 100.00 |
CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
CONT_ASSIGN | 299 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
100 |
|
unreachable |
283 |
1 |
1 |
284 |
1 |
1 |
299 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb
| Total | Covered | Percent |
Conditions | 3 | 2 | 66.67 |
Logical | 3 | 2 | 66.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 100
EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
------1----- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T4 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 100
SUB-EXPRESSION (dst_qs_o != dst_ds_i)
-----------1----------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T5,T6,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 100 | 0 | 0 | |
CONT_ASSIGN | 283 | 1 | 1 | 100.00 |
CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
CONT_ASSIGN | 299 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
100 |
|
unreachable |
283 |
1 |
1 |
284 |
1 |
1 |
299 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb
| Total | Covered | Percent |
Conditions | 3 | 2 | 66.67 |
Logical | 3 | 2 | 66.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 100
EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
------1----- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T4 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 100
SUB-EXPRESSION (dst_qs_o != dst_ds_i)
-----------1----------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T5,T6,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 100 | 0 | 0 | |
CONT_ASSIGN | 283 | 1 | 1 | 100.00 |
CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
CONT_ASSIGN | 299 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
100 |
|
unreachable |
283 |
1 |
1 |
284 |
1 |
1 |
299 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb
| Total | Covered | Percent |
Conditions | 3 | 2 | 66.67 |
Logical | 3 | 2 | 66.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 100
EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
------1----- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T4 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 100
SUB-EXPRESSION (dst_qs_o != dst_ds_i)
-----------1----------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T5,T6,T4 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 100 | 0 | 0 | |
CONT_ASSIGN | 283 | 1 | 1 | 100.00 |
CONT_ASSIGN | 284 | 1 | 1 | 100.00 |
CONT_ASSIGN | 299 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
100 |
|
unreachable |
283 |
1 |
1 |
284 |
1 |
1 |
299 |
|
unreachable |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb
| Total | Covered | Percent |
Conditions | 3 | 2 | 66.67 |
Logical | 3 | 2 | 66.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 100
EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
------1----- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T4 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
LINE 100
SUB-EXPRESSION (dst_qs_o != dst_ds_i)
-----------1----------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T5,T6,T4 |