Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	86.67			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_io_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	97.74	86.76			94.92	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	87.44	96.94	84.78			93.02	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T4,T1,T2
1	0	Covered	T5,T6,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T4
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T4
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T5,T6,T4

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T4
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T5,T6,T4

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1633491740	1485931	0	0
DstReqKnown_A	2147483647	2147483647	0	0
SrcAckBusyChk_A	1633491740	284045	0	0
SrcBusyKnown_A	1633491740	1607494660	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1633491740	1485931	0	0
T1	2368610	11292	0	0
T2	1411980	12075	0	0
T3	0	1928	0	0
T4	1184820	4943	0	0
T5	934260	1589	0	0
T6	338280	730	0	0
T16	13630	0	0	0
T18	0	736	0	0
T24	15690	0	0	0
T25	7000	0	0	0
T26	13680	0	0	0
T27	16130	0	0	0
T28	0	153	0	0
T32	0	3003	0	0
T33	0	968	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6167352	6163396	0	0
T2	3492072	3491462	0	0
T4	691430	36798	0	0
T5	980306	979128	0	0
T6	704400	703934	0	0
T16	63154	61914	0	0
T24	10038	8880	0	0
T25	27650	26640	0	0
T26	89904	88948	0	0
T27	39984	39226	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1633491740	284045	0	0
T1	2368610	3345	0	0
T2	1411980	3505	0	0
T3	0	560	0	0
T4	1184820	560	0	0
T5	934260	320	0	0
T6	338280	220	0	0
T16	13630	0	0	0
T18	0	296	0	0
T24	15690	0	0	0
T25	7000	0	0	0
T26	13680	0	0	0
T27	16130	0	0	0
T28	0	60	0	0
T32	0	369	0	0
T33	0	180	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1633491740	1607494660	0	0
T1	2368610	2367010	0	0
T2	1411980	1411710	0	0
T4	1184820	55950	0	0
T5	934260	933240	0	0
T6	338280	338070	0	0
T16	13630	13340	0	0
T24	15690	13630	0	0
T25	7000	6730	0	0
T26	13680	13500	0	0
T27	16130	15800	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Unreachable
1	0	Covered	T5,T6,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T4
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T4
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T5,T6,T4

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T4
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	163349174	92659	0	0
DstReqKnown_A	449209565	444856721	0	0
SrcAckBusyChk_A	163349174	25630	0	0
SrcBusyKnown_A	163349174	160749466	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163349174	92659	0	0
T1	236861	823	0	0
T2	141198	899	0	0
T3	0	142	0	0
T4	118482	250	0	0
T5	93426	108	0	0
T6	33828	52	0	0
T16	1363	0	0	0
T18	0	45	0	0
T24	1569	0	0	0
T25	700	0	0	0
T26	1368	0	0	0
T27	1613	0	0	0
T28	0	15	0	0
T32	0	132	0	0
T33	0	67	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449209565	444856721	0	0
T1	931869	931229	0	0
T2	525480	525376	0	0
T4	118482	5595	0	0
T5	129242	129039	0	0
T6	95338	95259	0	0
T16	9356	9153	0	0
T24	1552	1349	0	0
T25	4204	4042	0	0
T26	13139	12963	0	0
T27	5958	5837	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163349174	25630	0	0
T1	236861	332	0	0
T2	141198	348	0	0
T3	0	56	0	0
T4	118482	40	0	0
T5	93426	32	0	0
T6	33828	22	0	0
T16	1363	0	0	0
T18	0	20	0	0
T24	1569	0	0	0
T25	700	0	0	0
T26	1368	0	0	0
T27	1613	0	0	0
T28	0	6	0	0
T32	0	26	0	0
T33	0	18	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163349174	160749466	0	0
T1	236861	236701	0	0
T2	141198	141171	0	0
T4	118482	5595	0	0
T5	93426	93324	0	0
T6	33828	33807	0	0
T16	1363	1334	0	0
T24	1569	1363	0	0
T25	700	673	0	0
T26	1368	1350	0	0
T27	1613	1580	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Unreachable
1	0	Covered	T5,T6,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T4
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T4
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T5,T6,T4

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T4
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	163349174	134159	0	0
DstReqKnown_A	223800382	222694647	0	0
SrcAckBusyChk_A	163349174	25630	0	0
SrcBusyKnown_A	163349174	160749466	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163349174	134159	0	0
T1	236861	1155	0	0
T2	141198	1233	0	0
T3	0	198	0	0
T4	118482	343	0	0
T5	93426	152	0	0
T6	33828	76	0	0
T16	1363	0	0	0
T18	0	45	0	0
T24	1569	0	0	0
T25	700	0	0	0
T26	1368	0	0	0
T27	1613	0	0	0
T28	0	15	0	0
T32	0	218	0	0
T33	0	96	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223800382	222694647	0	0
T1	466684	466450	0	0
T2	262760	262733	0	0
T4	29710	2802	0	0
T5	64568	64520	0	0
T6	47650	47629	0	0
T16	5198	5129	0	0
T24	716	675	0	0
T25	2094	2032	0	0
T26	7705	7684	0	0
T27	3234	3186	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163349174	25630	0	0
T1	236861	332	0	0
T2	141198	348	0	0
T3	0	56	0	0
T4	118482	40	0	0
T5	93426	32	0	0
T6	33828	22	0	0
T16	1363	0	0	0
T18	0	20	0	0
T24	1569	0	0	0
T25	700	0	0	0
T26	1368	0	0	0
T27	1613	0	0	0
T28	0	6	0	0
T32	0	26	0	0
T33	0	18	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163349174	160749466	0	0
T1	236861	236701	0	0
T2	141198	141171	0	0
T4	118482	5595	0	0
T5	93426	93324	0	0
T6	33828	33807	0	0
T16	1363	1334	0	0
T24	1569	1363	0	0
T25	700	673	0	0
T26	1368	1350	0	0
T27	1613	1580	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Unreachable
1	0	Covered	T5,T6,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T4
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T4
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T5,T6,T4

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T4
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	163349174	215503	0	0
DstReqKnown_A	111899548	111346778	0	0
SrcAckBusyChk_A	163349174	25630	0	0
SrcBusyKnown_A	163349174	160749466	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163349174	215503	0	0
T1	236861	1645	0	0
T2	141198	1772	0	0
T3	0	284	0	0
T4	118482	608	0	0
T5	93426	241	0	0
T6	33828	107	0	0
T16	1363	0	0	0
T18	0	50	0	0
T24	1569	0	0	0
T25	700	0	0	0
T26	1368	0	0	0
T27	1613	0	0	0
T28	0	16	0	0
T32	0	362	0	0
T33	0	156	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111899548	111346778	0	0
T1	233341	233224	0	0
T2	131380	131366	0	0
T4	14855	1401	0	0
T5	32284	32260	0	0
T6	23825	23815	0	0
T16	2599	2565	0	0
T24	358	337	0	0
T25	1047	1016	0	0
T26	3851	3841	0	0
T27	1616	1592	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163349174	25630	0	0
T1	236861	332	0	0
T2	141198	348	0	0
T3	0	56	0	0
T4	118482	40	0	0
T5	93426	32	0	0
T6	33828	22	0	0
T16	1363	0	0	0
T18	0	20	0	0
T24	1569	0	0	0
T25	700	0	0	0
T26	1368	0	0	0
T27	1613	0	0	0
T28	0	6	0	0
T32	0	26	0	0
T33	0	18	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163349174	160749466	0	0
T1	236861	236701	0	0
T2	141198	141171	0	0
T4	118482	5595	0	0
T5	93426	93324	0	0
T6	33828	33807	0	0
T16	1363	1334	0	0
T24	1569	1363	0	0
T25	700	673	0	0
T26	1368	1350	0	0
T27	1613	1580	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Unreachable
1	0	Covered	T5,T6,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T4
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T4
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T5,T6,T4

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T4
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	163349174	90713	0	0
DstReqKnown_A	479031968	474384813	0	0
SrcAckBusyChk_A	163349174	25630	0	0
SrcBusyKnown_A	163349174	160749466	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163349174	90713	0	0
T1	236861	823	0	0
T2	141198	867	0	0
T3	0	142	0	0
T4	118482	207	0	0
T5	93426	107	0	0
T6	33828	52	0	0
T16	1363	0	0	0
T18	0	45	0	0
T24	1569	0	0	0
T25	700	0	0	0
T26	1368	0	0	0
T27	1613	0	0	0
T28	0	15	0	0
T32	0	130	0	0
T33	0	66	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479031968	474384813	0	0
T1	980929	980262	0	0
T2	558192	558084	0	0
T4	123424	5812	0	0
T5	170633	170421	0	0
T6	123315	123232	0	0
T16	9746	9534	0	0
T24	1617	1405	0	0
T25	4379	4210	0	0
T26	13687	13504	0	0
T27	6206	6080	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163349174	25630	0	0
T1	236861	332	0	0
T2	141198	348	0	0
T3	0	56	0	0
T4	118482	40	0	0
T5	93426	32	0	0
T6	33828	22	0	0
T16	1363	0	0	0
T18	0	20	0	0
T24	1569	0	0	0
T25	700	0	0	0
T26	1368	0	0	0
T27	1613	0	0	0
T28	0	6	0	0
T32	0	26	0	0
T33	0	18	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163349174	160749466	0	0
T1	236861	236701	0	0
T2	141198	141171	0	0
T4	118482	5595	0	0
T5	93426	93324	0	0
T6	33828	33807	0	0
T16	1363	1334	0	0
T24	1569	1363	0	0
T25	700	673	0	0
T26	1368	1350	0	0
T27	1613	1580	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Unreachable
1	0	Covered	T5,T6,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T4
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T4
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T5,T6,T4

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T4
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	163349174	132644	0	0
DstReqKnown_A	230109673	227895096	0	0
SrcAckBusyChk_A	163349174	25172	0	0
SrcBusyKnown_A	163349174	160749466	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163349174	132644	0	0
T1	236861	1155	0	0
T2	141198	1249	0	0
T3	0	198	0	0
T4	118482	183	0	0
T5	93426	184	0	0
T6	33828	76	0	0
T16	1363	0	0	0
T18	0	43	0	0
T24	1569	0	0	0
T25	700	0	0	0
T26	1368	0	0	0
T27	1613	0	0	0
T28	0	15	0	0
T32	0	123	0	0
T33	0	96	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230109673	227895096	0	0
T1	470853	470533	0	0
T2	268224	268172	0	0
T4	59244	2789	0	0
T5	93426	93324	0	0
T6	62072	62032	0	0
T16	4678	4576	0	0
T24	776	674	0	0
T25	2101	2020	0	0
T26	6570	6482	0	0
T27	2978	2918	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163349174	25172	0	0
T1	236861	332	0	0
T2	141198	348	0	0
T3	0	56	0	0
T4	118482	20	0	0
T5	93426	32	0	0
T6	33828	22	0	0
T16	1363	0	0	0
T18	0	16	0	0
T24	1569	0	0	0
T25	700	0	0	0
T26	1368	0	0	0
T27	1613	0	0	0
T28	0	6	0	0
T32	0	13	0	0
T33	0	18	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163349174	160749466	0	0
T1	236861	236701	0	0
T2	141198	141171	0	0
T4	118482	5595	0	0
T5	93426	93324	0	0
T6	33828	33807	0	0
T16	1363	1334	0	0
T24	1569	1363	0	0
T25	700	673	0	0
T26	1368	1350	0	0
T27	1613	1580	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T4,T1,T2
1	0	Covered	T5,T6,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Unreachable
1	0	Covered	T5,T6,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T4
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T4
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T5,T6,T4

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T4
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	163349174	113484	0	0
DstReqKnown_A	449209565	444856721	0	0
SrcAckBusyChk_A	163349174	31302	0	0
SrcBusyKnown_A	163349174	160749466	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163349174	113484	0	0
T1	236861	836	0	0
T2	141198	888	0	0
T3	0	142	0	0
T4	118482	496	0	0
T5	93426	108	0	0
T6	33828	53	0	0
T16	1363	0	0	0
T18	0	98	0	0
T24	1569	0	0	0
T25	700	0	0	0
T26	1368	0	0	0
T27	1613	0	0	0
T28	0	15	0	0
T32	0	261	0	0
T33	0	67	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449209565	444856721	0	0
T1	931869	931229	0	0
T2	525480	525376	0	0
T4	118482	5595	0	0
T5	129242	129039	0	0
T6	95338	95259	0	0
T16	9356	9153	0	0
T24	1552	1349	0	0
T25	4204	4042	0	0
T26	13139	12963	0	0
T27	5958	5837	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163349174	31302	0	0
T1	236861	337	0	0
T2	141198	353	0	0
T3	0	56	0	0
T4	118482	80	0	0
T5	93426	32	0	0
T6	33828	22	0	0
T16	1363	0	0	0
T18	0	40	0	0
T24	1569	0	0	0
T25	700	0	0	0
T26	1368	0	0	0
T27	1613	0	0	0
T28	0	6	0	0
T32	0	52	0	0
T33	0	18	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163349174	160749466	0	0
T1	236861	236701	0	0
T2	141198	141171	0	0
T4	118482	5595	0	0
T5	93426	93324	0	0
T6	33828	33807	0	0
T16	1363	1334	0	0
T24	1569	1363	0	0
T25	700	673	0	0
T26	1368	1350	0	0
T27	1613	1580	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T4,T1,T2
1	0	Covered	T5,T6,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Unreachable
1	0	Covered	T5,T6,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T4
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T4
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T5,T6,T4

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T4
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	163349174	164339	0	0
DstReqKnown_A	223800382	222694647	0	0
SrcAckBusyChk_A	163349174	31280	0	0
SrcBusyKnown_A	163349174	160749466	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163349174	164339	0	0
T1	236861	1174	0	0
T2	141198	1254	0	0
T3	0	198	0	0
T4	118482	696	0	0
T5	93426	152	0	0
T6	33828	76	0	0
T16	1363	0	0	0
T18	0	98	0	0
T24	1569	0	0	0
T25	700	0	0	0
T26	1368	0	0	0
T27	1613	0	0	0
T28	0	15	0	0
T32	0	414	0	0
T33	0	97	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	223800382	222694647	0	0
T1	466684	466450	0	0
T2	262760	262733	0	0
T4	29710	2802	0	0
T5	64568	64520	0	0
T6	47650	47629	0	0
T16	5198	5129	0	0
T24	716	675	0	0
T25	2094	2032	0	0
T26	7705	7684	0	0
T27	3234	3186	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163349174	31280	0	0
T1	236861	337	0	0
T2	141198	353	0	0
T3	0	56	0	0
T4	118482	80	0	0
T5	93426	32	0	0
T6	33828	22	0	0
T16	1363	0	0	0
T18	0	40	0	0
T24	1569	0	0	0
T25	700	0	0	0
T26	1368	0	0	0
T27	1613	0	0	0
T28	0	6	0	0
T32	0	52	0	0
T33	0	18	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163349174	160749466	0	0
T1	236861	236701	0	0
T2	141198	141171	0	0
T4	118482	5595	0	0
T5	93426	93324	0	0
T6	33828	33807	0	0
T16	1363	1334	0	0
T24	1569	1363	0	0
T25	700	673	0	0
T26	1368	1350	0	0
T27	1613	1580	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T4,T1,T2
1	0	Covered	T5,T6,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Unreachable
1	0	Covered	T5,T6,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T4
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T4
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T5,T6,T4

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T4
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	163349174	266470	0	0
DstReqKnown_A	111899548	111346778	0	0
SrcAckBusyChk_A	163349174	31352	0	0
SrcBusyKnown_A	163349174	160749466	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163349174	266470	0	0
T1	236861	1672	0	0
T2	141198	1791	0	0
T3	0	284	0	0
T4	118482	1204	0	0
T5	93426	246	0	0
T6	33828	108	0	0
T16	1363	0	0	0
T18	0	116	0	0
T24	1569	0	0	0
T25	700	0	0	0
T26	1368	0	0	0
T27	1613	0	0	0
T28	0	17	0	0
T32	0	720	0	0
T33	0	159	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111899548	111346778	0	0
T1	233341	233224	0	0
T2	131380	131366	0	0
T4	14855	1401	0	0
T5	32284	32260	0	0
T6	23825	23815	0	0
T16	2599	2565	0	0
T24	358	337	0	0
T25	1047	1016	0	0
T26	3851	3841	0	0
T27	1616	1592	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163349174	31352	0	0
T1	236861	337	0	0
T2	141198	353	0	0
T3	0	56	0	0
T4	118482	80	0	0
T5	93426	32	0	0
T6	33828	22	0	0
T16	1363	0	0	0
T18	0	40	0	0
T24	1569	0	0	0
T25	700	0	0	0
T26	1368	0	0	0
T27	1613	0	0	0
T28	0	6	0	0
T32	0	52	0	0
T33	0	18	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163349174	160749466	0	0
T1	236861	236701	0	0
T2	141198	141171	0	0
T4	118482	5595	0	0
T5	93426	93324	0	0
T6	33828	33807	0	0
T16	1363	1334	0	0
T24	1569	1363	0	0
T25	700	673	0	0
T26	1368	1350	0	0
T27	1613	1580	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T4,T1,T2
1	0	Covered	T5,T6,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Unreachable
1	0	Covered	T5,T6,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T4
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T4
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T5,T6,T4

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T4
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	163349174	111503	0	0
DstReqKnown_A	479031968	474384813	0	0
SrcAckBusyChk_A	163349174	31330	0	0
SrcBusyKnown_A	163349174	160749466	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163349174	111503	0	0
T1	236861	836	0	0
T2	141198	871	0	0
T3	0	142	0	0
T4	118482	411	0	0
T5	93426	107	0	0
T6	33828	52	0	0
T16	1363	0	0	0
T18	0	98	0	0
T24	1569	0	0	0
T25	700	0	0	0
T26	1368	0	0	0
T27	1613	0	0	0
T28	0	15	0	0
T32	0	251	0	0
T33	0	66	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479031968	474384813	0	0
T1	980929	980262	0	0
T2	558192	558084	0	0
T4	123424	5812	0	0
T5	170633	170421	0	0
T6	123315	123232	0	0
T16	9746	9534	0	0
T24	1617	1405	0	0
T25	4379	4210	0	0
T26	13687	13504	0	0
T27	6206	6080	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163349174	31330	0	0
T1	236861	337	0	0
T2	141198	353	0	0
T3	0	56	0	0
T4	118482	80	0	0
T5	93426	32	0	0
T6	33828	22	0	0
T16	1363	0	0	0
T18	0	40	0	0
T24	1569	0	0	0
T25	700	0	0	0
T26	1368	0	0	0
T27	1613	0	0	0
T28	0	6	0	0
T32	0	52	0	0
T33	0	18	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163349174	160749466	0	0
T1	236861	236701	0	0
T2	141198	141171	0	0
T4	118482	5595	0	0
T5	93426	93324	0	0
T6	33828	33807	0	0
T16	1363	1334	0	0
T24	1569	1363	0	0
T25	700	673	0	0
T26	1368	1350	0	0
T27	1613	1580	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T4,T1,T2
1	0	Covered	T5,T6,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Unreachable
1	0	Covered	T5,T6,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T4
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T4
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T5,T6,T4

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T4
0	1	-	Covered	T5,T6,T4
0	0	1	Covered	T5,T6,T4
0	0	0	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	163349174	164457	0	0
DstReqKnown_A	230109673	227895096	0	0
SrcAckBusyChk_A	163349174	31089	0	0
SrcBusyKnown_A	163349174	160749466	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163349174	164457	0	0
T1	236861	1173	0	0
T2	141198	1251	0	0
T3	0	198	0	0
T4	118482	545	0	0
T5	93426	184	0	0
T6	33828	78	0	0
T16	1363	0	0	0
T18	0	98	0	0
T24	1569	0	0	0
T25	700	0	0	0
T26	1368	0	0	0
T27	1613	0	0	0
T28	0	15	0	0
T32	0	392	0	0
T33	0	98	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230109673	227895096	0	0
T1	470853	470533	0	0
T2	268224	268172	0	0
T4	59244	2789	0	0
T5	93426	93324	0	0
T6	62072	62032	0	0
T16	4678	4576	0	0
T24	776	674	0	0
T25	2101	2020	0	0
T26	6570	6482	0	0
T27	2978	2918	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163349174	31089	0	0
T1	236861	337	0	0
T2	141198	353	0	0
T3	0	56	0	0
T4	118482	60	0	0
T5	93426	32	0	0
T6	33828	22	0	0
T16	1363	0	0	0
T18	0	40	0	0
T24	1569	0	0	0
T25	700	0	0	0
T26	1368	0	0	0
T27	1613	0	0	0
T28	0	6	0	0
T32	0	44	0	0
T33	0	18	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	163349174	160749466	0	0
T1	236861	236701	0	0
T2	141198	141171	0	0
T4	118482	5595	0	0
T5	93426	93324	0	0
T6	33828	33807	0	0
T16	1363	1334	0	0
T24	1569	1363	0	0
T25	700	673	0	0
T26	1368	1350	0	0
T27	1613	1580	0	0