Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	959993	0	0
SrcPulseCheck_M	2147483647	955455	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	959993
T1	3783052	6393
T2	2144530	6669
T3	0	1056
T4	464373	200
T5	619289	704
T6	419256	534
T9	0	128
T16	38658	0
T18	0	108
T24	7244	0
T25	16612	0
T26	55160	0
T27	25095	0
T28	0	129
T32	0	130
T33	0	354
T63	16308	1
T64	6112	1
T65	9382	2
T67	8576	2
T69	8496	2
T71	5998	1
T78	0	524
T118	26732	1
T119	7702	1
T120	10652	1
T121	11296	0
T122	11922	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	955455
T1	2406770	6393
T2	1536516	6669
T3	0	1056
T4	267698	200
T5	252636	704
T6	116206	534
T9	0	128
T16	10652	0
T18	0	108
T24	4306	0
T25	4718	0
T26	14273	0
T27	8196	0
T28	0	129
T32	0	130
T33	0	354
T63	13948	1
T64	31572	1
T65	3866	2
T67	7720	2
T69	7276	2
T71	10952	1
T78	0	524
T118	14802	1
T119	20673	1
T120	5160	1
T121	12836	0
T122	4857	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	449209565	25630	0	0
SrcPulseCheck_M	163349174	25630	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	449209565	25630
T1	931869	332
T2	525480	348
T3	0	56
T4	118482	40
T5	129242	32
T6	95338	22
T16	9356	0
T18	0	20
T24	1552	0
T25	4204	0
T26	13139	0
T27	5958	0
T28	0	6
T32	0	26
T33	0	18

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	163349174	25630
T1	236861	332
T2	141198	348
T3	0	56
T4	118482	40
T5	93426	32
T6	33828	22
T16	1363	0
T18	0	20
T24	1569	0
T25	700	0
T26	1368	0
T27	1613	0
T28	0	6
T32	0	26
T33	0	18

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	449209565	31309	0	0
SrcPulseCheck_M	163349174	31314	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	449209565	31309
T1	931869	337
T2	525480	353
T3	0	56
T4	118482	80
T5	129242	32
T6	95338	22
T16	9356	0
T18	0	40
T24	1552	0
T25	4204	0
T26	13139	0
T27	5958	0
T28	0	6
T32	0	52
T33	0	18

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	163349174	31314
T1	236861	337
T2	141198	353
T3	0	56
T4	118482	80
T5	93426	32
T6	33828	22
T16	1363	0
T18	0	40
T24	1569	0
T25	700	0
T26	1368	0
T27	1613	0
T28	0	6
T32	0	52
T33	0	18

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163349174	31302	0	0
SrcPulseCheck_M	449209565	31310	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163349174	31302
T1	236861	337
T2	141198	353
T3	0	56
T4	118482	80
T5	93426	32
T6	33828	22
T16	1363	0
T18	0	40
T24	1569	0
T25	700	0
T26	1368	0
T27	1613	0
T28	0	6
T32	0	52
T33	0	18

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	449209565	31310
T1	931869	337
T2	525480	353
T3	0	56
T4	118482	80
T5	129242	32
T6	95338	22
T16	9356	0
T18	0	40
T24	1552	0
T25	4204	0
T26	13139	0
T27	5958	0
T28	0	6
T32	0	52
T33	0	18

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	223800382	25630	0	0
SrcPulseCheck_M	163349174	25630	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	223800382	25630
T1	466684	332
T2	262760	348
T3	0	56
T4	29710	40
T5	64568	32
T6	47650	22
T16	5198	0
T18	0	20
T24	716	0
T25	2094	0
T26	7705	0
T27	3234	0
T28	0	6
T32	0	26
T33	0	18

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	163349174	25630
T1	236861	332
T2	141198	348
T3	0	56
T4	118482	40
T5	93426	32
T6	33828	22
T16	1363	0
T18	0	20
T24	1569	0
T25	700	0
T26	1368	0
T27	1613	0
T28	0	6
T32	0	26
T33	0	18

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	223800382	31284	0	0
SrcPulseCheck_M	163349174	31314	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	223800382	31284
T1	466684	337
T2	262760	353
T3	0	56
T4	29710	80
T5	64568	32
T6	47650	22
T16	5198	0
T18	0	40
T24	716	0
T25	2094	0
T26	7705	0
T27	3234	0
T28	0	6
T32	0	52
T33	0	18

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	163349174	31314
T1	236861	337
T2	141198	353
T3	0	56
T4	118482	80
T5	93426	32
T6	33828	22
T16	1363	0
T18	0	40
T24	1569	0
T25	700	0
T26	1368	0
T27	1613	0
T28	0	6
T32	0	52
T33	0	18

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163349174	31278	0	0
SrcPulseCheck_M	223800382	31288	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163349174	31278
T1	236861	337
T2	141198	353
T3	0	56
T4	118482	80
T5	93426	32
T6	33828	22
T16	1363	0
T18	0	40
T24	1569	0
T25	700	0
T26	1368	0
T27	1613	0
T28	0	6
T32	0	52
T33	0	18

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	223800382	31288
T1	466684	337
T2	262760	353
T3	0	56
T4	29710	80
T5	64568	32
T6	47650	22
T16	5198	0
T18	0	40
T24	716	0
T25	2094	0
T26	7705	0
T27	3234	0
T28	0	6
T32	0	52
T33	0	18

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	111899548	25630	0	0
SrcPulseCheck_M	163349174	25630	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	111899548	25630
T1	233341	332
T2	131380	348
T3	0	56
T4	14855	40
T5	32284	32
T6	23825	22
T16	2599	0
T18	0	20
T24	358	0
T25	1047	0
T26	3851	0
T27	1616	0
T28	0	6
T32	0	26
T33	0	18

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	163349174	25630
T1	236861	332
T2	141198	348
T3	0	56
T4	118482	40
T5	93426	32
T6	33828	22
T16	1363	0
T18	0	20
T24	1569	0
T25	700	0
T26	1368	0
T27	1613	0
T28	0	6
T32	0	26
T33	0	18

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	111899548	31351	0	0
SrcPulseCheck_M	163349174	31395	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	111899548	31351
T1	233341	337
T2	131380	353
T3	0	56
T4	14855	80
T5	32284	32
T6	23825	22
T16	2599	0
T18	0	40
T24	358	0
T25	1047	0
T26	3851	0
T27	1616	0
T28	0	6
T32	0	52
T33	0	18

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	163349174	31395
T1	236861	337
T2	141198	353
T3	0	56
T4	118482	80
T5	93426	32
T6	33828	22
T16	1363	0
T18	0	40
T24	1569	0
T25	700	0
T26	1368	0
T27	1613	0
T28	0	6
T32	0	52
T33	0	18

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163349174	31349	0	0
SrcPulseCheck_M	111899548	31356	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163349174	31349
T1	236861	337
T2	141198	353
T3	0	56
T4	118482	80
T5	93426	32
T6	33828	22
T16	1363	0
T18	0	40
T24	1569	0
T25	700	0
T26	1368	0
T27	1613	0
T28	0	6
T32	0	52
T33	0	18

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	111899548	31356
T1	233341	337
T2	131380	353
T3	0	56
T4	14855	80
T5	32284	32
T6	23825	22
T16	2599	0
T18	0	40
T24	358	0
T25	1047	0
T26	3851	0
T27	1616	0
T28	0	6
T32	0	52
T33	0	18

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	479031968	25630	0	0
SrcPulseCheck_M	163349174	25630	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	479031968	25630
T1	980929	332
T2	558192	348
T3	0	56
T4	123424	40
T5	170633	32
T6	123315	22
T16	9746	0
T18	0	20
T24	1617	0
T25	4379	0
T26	13687	0
T27	6206	0
T28	0	6
T32	0	26
T33	0	18

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	163349174	25630
T1	236861	332
T2	141198	348
T3	0	56
T4	118482	40
T5	93426	32
T6	33828	22
T16	1363	0
T18	0	20
T24	1569	0
T25	700	0
T26	1368	0
T27	1613	0
T28	0	6
T32	0	26
T33	0	18

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	479031968	31335	0	0
SrcPulseCheck_M	163349174	31347	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	479031968	31335
T1	980929	337
T2	558192	353
T3	0	56
T4	123424	80
T5	170633	32
T6	123315	22
T16	9746	0
T18	0	40
T24	1617	0
T25	4379	0
T26	13687	0
T27	6206	0
T28	0	6
T32	0	52
T33	0	18

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	163349174	31347
T1	236861	337
T2	141198	353
T3	0	56
T4	118482	80
T5	93426	32
T6	33828	22
T16	1363	0
T18	0	40
T24	1569	0
T25	700	0
T26	1368	0
T27	1613	0
T28	0	6
T32	0	52
T33	0	18

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163349174	31326	0	0
SrcPulseCheck_M	479031968	31337	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163349174	31326
T1	236861	337
T2	141198	353
T3	0	56
T4	118482	80
T5	93426	32
T6	33828	22
T16	1363	0
T18	0	40
T24	1569	0
T25	700	0
T26	1368	0
T27	1613	0
T28	0	6
T32	0	52
T33	0	18

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	479031968	31337
T1	980929	337
T2	558192	353
T3	0	56
T4	123424	80
T5	170633	32
T6	123315	22
T16	9746	0
T18	0	40
T24	1617	0
T25	4379	0
T26	13687	0
T27	6206	0
T28	0	6
T32	0	52
T33	0	18

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	230109673	25223	0	0
SrcPulseCheck_M	163349174	25630	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	230109673	25223
T1	470853	332
T2	268224	348
T3	0	56
T4	59244	20
T5	93426	32
T6	62072	22
T16	4678	0
T18	0	20
T24	776	0
T25	2101	0
T26	6570	0
T27	2978	0
T28	0	6
T32	0	13
T33	0	18

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	163349174	25630
T1	236861	332
T2	141198	348
T3	0	56
T4	118482	40
T5	93426	32
T6	33828	22
T16	1363	0
T18	0	20
T24	1569	0
T25	700	0
T26	1368	0
T27	1613	0
T28	0	6
T32	0	26
T33	0	18

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	230109673	31148	0	0
SrcPulseCheck_M	163349174	31353	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	230109673	31148
T1	470853	337
T2	268224	353
T3	0	56
T4	59244	60
T5	93426	32
T6	62072	22
T16	4678	0
T18	0	40
T24	776	0
T25	2101	0
T26	6570	0
T27	2978	0
T28	0	6
T32	0	44
T33	0	18

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	163349174	31353
T1	236861	337
T2	141198	353
T3	0	56
T4	118482	80
T5	93426	32
T6	33828	22
T16	1363	0
T18	0	40
T24	1569	0
T25	700	0
T26	1368	0
T27	1613	0
T28	0	6
T32	0	52
T33	0	18

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T5,T6,T4
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163349174	31058	0	0
SrcPulseCheck_M	230109673	31190	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163349174	31058
T1	236861	337
T2	141198	353
T3	0	56
T4	118482	60
T5	93426	32
T6	33828	22
T16	1363	0
T18	0	40
T24	1569	0
T25	700	0
T26	1368	0
T27	1613	0
T28	0	6
T32	0	44
T33	0	18

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	230109673	31190
T1	470853	337
T2	268224	353
T3	0	56
T4	59244	60
T5	93426	32
T6	62072	22
T16	4678	0
T18	0	40
T24	776	0
T25	2101	0
T26	6570	0
T27	2978	0
T28	0	6
T32	0	47
T33	0	18

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T66,T63,T65
1	0	Covered	T66,T63,T65
1	1	Covered	T123,T124,T125

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T66,T63,T65
1	0	Covered	T123,T124,T125
1	1	Covered	T66,T63,T65

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163349174	29	0	0
SrcPulseCheck_M	449209565	29	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163349174	29
T63	8154	1
T65	4691	1
T66	3826	1
T67	8576	2
T71	5998	1
T119	7702	2
T120	5326	2
T121	5648	1
T126	9348	1
T127	4945	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	449209565	29
T63	15975	1
T65	4503	1
T66	14128	1
T67	16802	2
T71	23031	1
T119	43497	2
T120	5810	2
T121	14268	1
T126	17947	1
T127	31653	1

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T66,T65,T67
1	0	Covered	T66,T65,T67
1	1	Covered	T66,T119,T128

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T66,T65,T67
1	0	Covered	T66,T119,T128
1	1	Covered	T66,T65,T67

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163349174	36	0	0
SrcPulseCheck_M	449209565	36	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163349174	36
T65	4691	1
T66	3826	2
T67	8576	1
T68	7122	1
T71	5998	1
T119	7702	2
T120	5326	2
T121	5648	2
T126	9348	2
T127	4945	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	449209565	36
T65	4503	1
T66	14128	2
T67	16802	1
T68	18478	1
T71	23031	1
T119	43497	2
T120	5810	2
T121	14268	2
T126	17947	2
T127	31653	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T63,T64,T65
1	0	Covered	T63,T64,T65
1	1	Covered	T65,T69,T122

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T63,T64,T65
1	0	Covered	T65,T69,T122
1	1	Covered	T63,T64,T65

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163349174	39	0	0
SrcPulseCheck_M	223800382	39	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163349174	39
T63	8154	1
T64	3056	1
T65	4691	2
T67	8576	2
T69	4248	2
T71	5998	1
T118	13366	1
T119	7702	1
T120	5326	1
T121	5648	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	223800382	39
T63	6974	1
T64	15786	1
T65	1933	2
T67	7720	2
T69	3638	2
T71	10952	1
T118	7401	1
T119	20673	1
T120	2580	1
T121	6418	3

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T63,T64,T65
1	0	Covered	T63,T64,T65
1	1	Covered	T65,T118,T121

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T63,T64,T65
1	0	Covered	T65,T118,T121
1	1	Covered	T63,T64,T65

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163349174	39	0	0
SrcPulseCheck_M	223800382	39	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163349174	39
T63	8154	2
T64	3056	1
T65	4691	2
T69	4248	1
T118	13366	2
T120	5326	1
T121	5648	3
T122	11922	7
T128	7684	1
T129	8432	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	223800382	39
T63	6974	2
T64	15786	1
T65	1933	2
T69	3638	1
T118	7401	2
T120	2580	1
T121	6418	3
T122	4857	7
T128	13712	1
T129	14506	2

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T66,T64,T65
1	0	Covered	T66,T64,T65
1	1	Covered	T65,T130,T120

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T66,T64,T65
1	0	Covered	T65,T130,T120
1	1	Covered	T66,T64,T65

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163349174	41	0	0
SrcPulseCheck_M	111899548	41	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163349174	41
T64	3056	2
T65	4691	3
T66	3826	1
T67	8576	2
T68	7122	1
T69	4248	1
T71	5998	1
T126	9348	1
T130	3130	3
T131	11696	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	111899548	41
T64	7895	2
T65	965	3
T66	3276	1
T67	3861	2
T68	4131	1
T69	1819	1
T71	5475	1
T126	3944	1
T130	3312	3
T131	5281	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T66,T65,T67
1	0	Covered	T66,T65,T67
1	1	Covered	T129,T124,T132

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T66,T65,T67
1	0	Covered	T129,T124,T132
1	1	Covered	T66,T65,T67

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163349174	39	0	0
SrcPulseCheck_M	111899548	39	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163349174	39
T65	4691	1
T66	3826	1
T67	8576	2
T68	7122	1
T69	4248	1
T119	7702	1
T120	5326	2
T126	9348	1
T130	3130	1
T131	11696	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	111899548	39
T65	965	1
T66	3276	1
T67	3861	2
T68	4131	1
T69	1819	1
T119	10337	1
T120	1289	2
T126	3944	1
T130	3312	1
T131	5281	1

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T63,T64,T67
1	0	Covered	T63,T64,T67
1	1	Covered	T64,T121,T122

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T63,T64,T67
1	0	Covered	T64,T121,T122
1	1	Covered	T63,T64,T67

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163349174	38	0	0
SrcPulseCheck_M	479031968	38	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163349174	38
T63	8154	1
T64	3056	2
T67	8576	3
T68	7122	1
T70	5958	1
T71	5998	1
T121	5648	4
T122	11922	4
T131	11696	1
T133	7448	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	479031968	38
T63	16642	1
T64	33969	2
T67	17503	3
T68	19248	1
T70	6081	1
T71	23992	1
T121	14864	4
T122	11922	4
T131	23394	1
T133	17733	1

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T63,T64,T65
1	0	Covered	T63,T64,T65
1	1	Covered	T64,T65,T67

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T63,T64,T65
1	0	Covered	T64,T65,T67
1	1	Covered	T63,T64,T65

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163349174	41	0	0
SrcPulseCheck_M	479031968	41	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163349174	41
T63	8154	2
T64	3056	2
T65	4691	3
T67	8576	3
T68	7122	1
T70	5958	2
T71	5998	1
T127	4945	1
T131	11696	1
T133	7448	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	479031968	41
T63	16642	2
T64	33969	2
T65	4691	3
T67	17503	3
T68	19248	1
T70	6081	2
T71	23992	1
T127	32973	1
T131	23394	1
T133	17733	1

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T63,T64,T67
1	0	Covered	T63,T64,T67
1	1	Covered	T64,T67,T127

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T63,T64,T67
1	0	Covered	T64,T67,T127
1	1	Covered	T63,T64,T67

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163349174	33	0	0
SrcPulseCheck_M	230109673	33	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163349174	33
T63	8154	1
T64	3056	2
T67	8576	2
T68	7122	1
T121	5648	1
T122	11922	1
T123	5489	3
T127	4945	2
T129	8432	1
T134	6581	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	230109673	33
T63	7988	1
T64	16305	2
T67	8402	2
T68	9240	1
T121	7134	1
T122	5722	1
T123	9759	3
T127	15827	2
T129	15567	1
T134	16629	1

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T63,T64,T67
1	0	Covered	T63,T64,T67
1	1	Covered	T64,T127,T121

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T63,T64,T67
1	0	Covered	T64,T127,T121
1	1	Covered	T63,T64,T67

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	163349174	32	0	0
SrcPulseCheck_M	230109673	32	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	163349174	32
T63	8154	1
T64	3056	2
T67	8576	2
T68	7122	1
T121	5648	2
T122	11922	1
T127	4945	2
T128	7684	1
T129	8432	1
T134	6581	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	230109673	32
T63	7988	1
T64	16305	2
T67	8402	2
T68	9240	1
T121	7134	2
T122	5722	1
T127	15827	2
T128	14187	1
T129	15567	1
T134	16629	1

Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4

Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	446837348	96518	0	0
SrcPulseCheck_M	15206557	95121	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	446837348	96518
T1	931869	1354
T2	525480	1380
T3	0	216
T4	118482	0
T5	129242	134
T6	95338	105
T9	0	32
T16	9356	0
T18	0	2
T24	1552	0
T25	4204	0
T26	13139	0
T27	5958	0
T28	0	30
T33	0	60
T78	0	119

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	15206557	95121
T1	366540	1354
T2	247786	1380
T3	0	216
T4	256	0
T5	286	134
T6	213	105
T9	0	32
T16	682	0
T18	0	2
T24	113	0
T25	306	0
T26	958	0
T27	434	0
T28	0	30
T33	0	60
T78	0	119

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4

Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	222662241	95964	0	0
SrcPulseCheck_M	15206557	94581	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	222662241	95964
T1	466684	1340
T2	262760	1369
T3	0	216
T4	29710	0
T5	64568	134
T6	47650	105
T9	0	32
T16	5198	0
T18	0	3
T24	716	0
T25	2094	0
T26	7705	0
T27	3234	0
T28	0	30
T33	0	60
T78	0	119

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	15206557	94581
T1	366540	1340
T2	247786	1369
T3	0	216
T4	256	0
T5	286	134
T6	213	105
T9	0	32
T16	682	0
T18	0	3
T24	113	0
T25	306	0
T26	958	0
T27	434	0
T28	0	30
T33	0	60
T78	0	119

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4

Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	111330503	95101	0	0
SrcPulseCheck_M	15206557	93740	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	111330503	95101
T1	233341	1271
T2	131380	1347
T3	0	216
T4	14855	0
T5	32284	134
T6	23825	105
T9	0	32
T16	2599	0
T18	0	1
T24	358	0
T25	1047	0
T26	3851	0
T27	1616	0
T28	0	27
T33	0	60
T78	0	119

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	15206557	93740
T1	366540	1271
T2	247786	1347
T3	0	216
T4	256	0
T5	286	134
T6	213	105
T9	0	32
T16	682	0
T18	0	1
T24	113	0
T25	306	0
T26	958	0
T27	434	0
T28	0	27
T33	0	60
T78	0	119

Line Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4

Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	476560808	115974	0	0
SrcPulseCheck_M	15373394	115285	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	476560808	115974
T1	980929	1422
T2	558192	1519
T3	0	240
T4	123424	0
T5	170633	206
T6	123315	153
T9	0	32
T16	9746	0
T18	0	2
T24	1617	0
T25	4379	0
T26	13687	0
T27	6206	0
T28	0	24
T33	0	120
T78	0	167

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	15373394	115285
T1	366744	1422
T2	248002	1519
T3	0	240
T4	256	0
T5	358	206
T6	261	153
T9	0	32
T16	682	0
T18	0	2
T24	113	0
T25	306	0
T26	958	0
T27	434	0
T28	0	24
T33	0	120
T78	0	167

Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Covered	T5,T6,T1
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T4
0	Covered	T5,T6,T4

Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	228923556	115586	0	0
SrcPulseCheck_M	15217451	115007	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	228923556	115586
T1	470853	1354
T2	268224	1496
T3	0	200
T4	59244	0
T5	93426	254
T6	62072	164
T9	0	31
T10	0	531
T16	4678	0
T24	776	0
T25	2101	0
T26	6570	0
T27	2978	0
T28	0	24
T33	0	144
T78	0	167

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	15217451	115007
T1	366744	1354
T2	248014	1496
T3	0	200
T4	256	0
T5	406	254
T6	273	164
T9	0	31
T10	0	531
T16	682	0
T24	113	0
T25	306	0
T26	958	0
T27	434	0
T28	0	24
T33	0	144
T78	0	167

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.43	100.00	85.71			100.00	100.00	u_io_meas_ctrl_en_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.92	100.00	91.67			100.00	100.00	u_io_meas_ctrl_shadowed_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb