Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=1,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=6,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Module :
prim_mubi4_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
Branch Coverage for Module :
prim_mubi4_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Module :
prim_mubi4_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22540 |
22540 |
0 |
0 |
T1 |
28 |
28 |
0 |
0 |
T2 |
28 |
28 |
0 |
0 |
T5 |
28 |
28 |
0 |
0 |
T6 |
28 |
28 |
0 |
0 |
T7 |
28 |
28 |
0 |
0 |
T8 |
28 |
28 |
0 |
0 |
T17 |
28 |
28 |
0 |
0 |
T18 |
28 |
28 |
0 |
0 |
T19 |
28 |
28 |
0 |
0 |
T23 |
28 |
28 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
11167355 |
11114304 |
0 |
0 |
T2 |
4747887 |
4745672 |
0 |
0 |
T5 |
4804019 |
4793485 |
0 |
0 |
T6 |
41240 |
38520 |
0 |
0 |
T7 |
69323 |
63306 |
0 |
0 |
T8 |
61987 |
56945 |
0 |
0 |
T17 |
259241 |
257839 |
0 |
0 |
T18 |
31160 |
26686 |
0 |
0 |
T19 |
50504 |
47574 |
0 |
0 |
T23 |
47617 |
43318 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
983552226 |
967623954 |
0 |
14490 |
T1 |
2380230 |
2366976 |
0 |
18 |
T2 |
744972 |
744576 |
0 |
18 |
T5 |
1156944 |
1154334 |
0 |
18 |
T6 |
9306 |
8640 |
0 |
18 |
T7 |
15720 |
14220 |
0 |
18 |
T8 |
14130 |
12852 |
0 |
18 |
T17 |
6804 |
6750 |
0 |
18 |
T18 |
7182 |
6066 |
0 |
18 |
T19 |
11364 |
10620 |
0 |
18 |
T23 |
7284 |
6534 |
0 |
18 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2139115768 |
0 |
16905 |
T1 |
2750881 |
2735560 |
0 |
21 |
T2 |
1480008 |
1479236 |
0 |
21 |
T5 |
1247761 |
1244660 |
0 |
21 |
T6 |
11117 |
10324 |
0 |
21 |
T7 |
18632 |
16852 |
0 |
21 |
T8 |
16505 |
15013 |
0 |
21 |
T17 |
101976 |
101248 |
0 |
21 |
T18 |
8322 |
7027 |
0 |
21 |
T19 |
13578 |
12686 |
0 |
21 |
T23 |
14972 |
13443 |
0 |
21 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
185531 |
0 |
0 |
T1 |
2750881 |
2050 |
0 |
0 |
T2 |
1480008 |
4 |
0 |
0 |
T5 |
1247761 |
180 |
0 |
0 |
T6 |
6464 |
12 |
0 |
0 |
T7 |
10800 |
119 |
0 |
0 |
T8 |
16505 |
253 |
0 |
0 |
T10 |
0 |
495 |
0 |
0 |
T17 |
101976 |
68 |
0 |
0 |
T18 |
8322 |
16 |
0 |
0 |
T19 |
13578 |
71 |
0 |
0 |
T20 |
28908 |
0 |
0 |
0 |
T21 |
4437 |
0 |
0 |
0 |
T22 |
0 |
178 |
0 |
0 |
T23 |
14972 |
37 |
0 |
0 |
T77 |
0 |
115 |
0 |
0 |
T78 |
0 |
14 |
0 |
0 |
T97 |
0 |
106 |
0 |
0 |
T98 |
0 |
54 |
0 |
0 |
T99 |
0 |
65 |
0 |
0 |
T100 |
0 |
24 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
6036244 |
6011729 |
0 |
0 |
T2 |
2522907 |
2521821 |
0 |
0 |
T5 |
2399314 |
2394374 |
0 |
0 |
T6 |
20817 |
19517 |
0 |
0 |
T7 |
34971 |
32195 |
0 |
0 |
T8 |
31352 |
29041 |
0 |
0 |
T17 |
150461 |
149802 |
0 |
0 |
T18 |
15656 |
13554 |
0 |
0 |
T19 |
25562 |
24229 |
0 |
0 |
T23 |
25361 |
23302 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T8,T23,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T8,T23,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T8,T23,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T8,T23,T1 |
Branch Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T23,T1 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T23,T1 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T23,T1 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T23,T1 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_io_step_down_req_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
348369267 |
343952474 |
0 |
0 |
T1 |
371423 |
369451 |
0 |
0 |
T2 |
238384 |
238263 |
0 |
0 |
T5 |
138985 |
138563 |
0 |
0 |
T6 |
1551 |
1443 |
0 |
0 |
T7 |
2592 |
2347 |
0 |
0 |
T8 |
2283 |
2080 |
0 |
0 |
T17 |
18972 |
18837 |
0 |
0 |
T18 |
1140 |
964 |
0 |
0 |
T19 |
1894 |
1773 |
0 |
0 |
T23 |
2428 |
2184 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
348369267 |
343945190 |
0 |
2415 |
T1 |
371423 |
369448 |
0 |
3 |
T2 |
238384 |
238260 |
0 |
3 |
T5 |
138985 |
138554 |
0 |
3 |
T6 |
1551 |
1440 |
0 |
3 |
T7 |
2592 |
2344 |
0 |
3 |
T8 |
2283 |
2077 |
0 |
3 |
T17 |
18972 |
18834 |
0 |
3 |
T18 |
1140 |
961 |
0 |
3 |
T19 |
1894 |
1770 |
0 |
3 |
T23 |
2428 |
2181 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
348369267 |
27025 |
0 |
0 |
T1 |
371423 |
292 |
0 |
0 |
T2 |
238384 |
0 |
0 |
0 |
T5 |
138985 |
0 |
0 |
0 |
T8 |
2283 |
58 |
0 |
0 |
T10 |
0 |
208 |
0 |
0 |
T17 |
18972 |
0 |
0 |
0 |
T18 |
1140 |
0 |
0 |
0 |
T19 |
1894 |
22 |
0 |
0 |
T20 |
14354 |
0 |
0 |
0 |
T21 |
2109 |
0 |
0 |
0 |
T22 |
0 |
63 |
0 |
0 |
T23 |
2428 |
7 |
0 |
0 |
T77 |
0 |
34 |
0 |
0 |
T97 |
0 |
48 |
0 |
0 |
T98 |
0 |
29 |
0 |
0 |
T99 |
0 |
30 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163925371 |
161278095 |
0 |
0 |
T1 |
396705 |
394499 |
0 |
0 |
T2 |
124162 |
124099 |
0 |
0 |
T5 |
192824 |
192398 |
0 |
0 |
T6 |
1551 |
1443 |
0 |
0 |
T7 |
2620 |
2373 |
0 |
0 |
T8 |
2355 |
2145 |
0 |
0 |
T17 |
1134 |
1128 |
0 |
0 |
T18 |
1197 |
1014 |
0 |
0 |
T19 |
1894 |
1773 |
0 |
0 |
T23 |
1214 |
1092 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163925371 |
161278095 |
0 |
0 |
T1 |
396705 |
394499 |
0 |
0 |
T2 |
124162 |
124099 |
0 |
0 |
T5 |
192824 |
192398 |
0 |
0 |
T6 |
1551 |
1443 |
0 |
0 |
T7 |
2620 |
2373 |
0 |
0 |
T8 |
2355 |
2145 |
0 |
0 |
T17 |
1134 |
1128 |
0 |
0 |
T18 |
1197 |
1014 |
0 |
0 |
T19 |
1894 |
1773 |
0 |
0 |
T23 |
1214 |
1092 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163925371 |
161278095 |
0 |
0 |
T1 |
396705 |
394499 |
0 |
0 |
T2 |
124162 |
124099 |
0 |
0 |
T5 |
192824 |
192398 |
0 |
0 |
T6 |
1551 |
1443 |
0 |
0 |
T7 |
2620 |
2373 |
0 |
0 |
T8 |
2355 |
2145 |
0 |
0 |
T17 |
1134 |
1128 |
0 |
0 |
T18 |
1197 |
1014 |
0 |
0 |
T19 |
1894 |
1773 |
0 |
0 |
T23 |
1214 |
1092 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163925371 |
161278095 |
0 |
0 |
T1 |
396705 |
394499 |
0 |
0 |
T2 |
124162 |
124099 |
0 |
0 |
T5 |
192824 |
192398 |
0 |
0 |
T6 |
1551 |
1443 |
0 |
0 |
T7 |
2620 |
2373 |
0 |
0 |
T8 |
2355 |
2145 |
0 |
0 |
T17 |
1134 |
1128 |
0 |
0 |
T18 |
1197 |
1014 |
0 |
0 |
T19 |
1894 |
1773 |
0 |
0 |
T23 |
1214 |
1092 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T8,T23,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T8,T23,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T8,T23,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T8,T23,T1 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T23,T1 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T23,T1 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T23,T1 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T23,T1 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163925371 |
161278095 |
0 |
0 |
T1 |
396705 |
394499 |
0 |
0 |
T2 |
124162 |
124099 |
0 |
0 |
T5 |
192824 |
192398 |
0 |
0 |
T6 |
1551 |
1443 |
0 |
0 |
T7 |
2620 |
2373 |
0 |
0 |
T8 |
2355 |
2145 |
0 |
0 |
T17 |
1134 |
1128 |
0 |
0 |
T18 |
1197 |
1014 |
0 |
0 |
T19 |
1894 |
1773 |
0 |
0 |
T23 |
1214 |
1092 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163925371 |
161270659 |
0 |
2415 |
T1 |
396705 |
394496 |
0 |
3 |
T2 |
124162 |
124096 |
0 |
3 |
T5 |
192824 |
192389 |
0 |
3 |
T6 |
1551 |
1440 |
0 |
3 |
T7 |
2620 |
2370 |
0 |
3 |
T8 |
2355 |
2142 |
0 |
3 |
T17 |
1134 |
1125 |
0 |
3 |
T18 |
1197 |
1011 |
0 |
3 |
T19 |
1894 |
1770 |
0 |
3 |
T23 |
1214 |
1089 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163925371 |
16906 |
0 |
0 |
T1 |
396705 |
195 |
0 |
0 |
T2 |
124162 |
0 |
0 |
0 |
T5 |
192824 |
0 |
0 |
0 |
T8 |
2355 |
52 |
0 |
0 |
T10 |
0 |
121 |
0 |
0 |
T17 |
1134 |
0 |
0 |
0 |
T18 |
1197 |
0 |
0 |
0 |
T19 |
1894 |
0 |
0 |
0 |
T20 |
7277 |
0 |
0 |
0 |
T21 |
1164 |
0 |
0 |
0 |
T22 |
0 |
61 |
0 |
0 |
T23 |
1214 |
7 |
0 |
0 |
T77 |
0 |
39 |
0 |
0 |
T78 |
0 |
14 |
0 |
0 |
T97 |
0 |
27 |
0 |
0 |
T98 |
0 |
13 |
0 |
0 |
T100 |
0 |
24 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T8,T23,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T8,T23,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T8,T23,T1 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T8,T23,T1 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T23,T1 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T23,T1 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T23,T1 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T8,T23,T1 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163925371 |
161278095 |
0 |
0 |
T1 |
396705 |
394499 |
0 |
0 |
T2 |
124162 |
124099 |
0 |
0 |
T5 |
192824 |
192398 |
0 |
0 |
T6 |
1551 |
1443 |
0 |
0 |
T7 |
2620 |
2373 |
0 |
0 |
T8 |
2355 |
2145 |
0 |
0 |
T17 |
1134 |
1128 |
0 |
0 |
T18 |
1197 |
1014 |
0 |
0 |
T19 |
1894 |
1773 |
0 |
0 |
T23 |
1214 |
1092 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163925371 |
161270659 |
0 |
2415 |
T1 |
396705 |
394496 |
0 |
3 |
T2 |
124162 |
124096 |
0 |
3 |
T5 |
192824 |
192389 |
0 |
3 |
T6 |
1551 |
1440 |
0 |
3 |
T7 |
2620 |
2370 |
0 |
3 |
T8 |
2355 |
2142 |
0 |
3 |
T17 |
1134 |
1125 |
0 |
3 |
T18 |
1197 |
1011 |
0 |
3 |
T19 |
1894 |
1770 |
0 |
3 |
T23 |
1214 |
1089 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163925371 |
19200 |
0 |
0 |
T1 |
396705 |
205 |
0 |
0 |
T2 |
124162 |
0 |
0 |
0 |
T5 |
192824 |
0 |
0 |
0 |
T8 |
2355 |
55 |
0 |
0 |
T10 |
0 |
166 |
0 |
0 |
T17 |
1134 |
0 |
0 |
0 |
T18 |
1197 |
0 |
0 |
0 |
T19 |
1894 |
22 |
0 |
0 |
T20 |
7277 |
0 |
0 |
0 |
T21 |
1164 |
0 |
0 |
0 |
T22 |
0 |
54 |
0 |
0 |
T23 |
1214 |
7 |
0 |
0 |
T77 |
0 |
42 |
0 |
0 |
T97 |
0 |
31 |
0 |
0 |
T98 |
0 |
12 |
0 |
0 |
T99 |
0 |
35 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372807150 |
370485106 |
0 |
0 |
T1 |
396512 |
395475 |
0 |
0 |
T2 |
248325 |
248241 |
0 |
0 |
T5 |
180782 |
180528 |
0 |
0 |
T6 |
1616 |
1532 |
0 |
0 |
T7 |
2700 |
2588 |
0 |
0 |
T8 |
2378 |
2295 |
0 |
0 |
T17 |
20184 |
20158 |
0 |
0 |
T18 |
1197 |
1085 |
0 |
0 |
T19 |
1974 |
1933 |
0 |
0 |
T23 |
2529 |
2403 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372807150 |
370485106 |
0 |
0 |
T1 |
396512 |
395475 |
0 |
0 |
T2 |
248325 |
248241 |
0 |
0 |
T5 |
180782 |
180528 |
0 |
0 |
T6 |
1616 |
1532 |
0 |
0 |
T7 |
2700 |
2588 |
0 |
0 |
T8 |
2378 |
2295 |
0 |
0 |
T17 |
20184 |
20158 |
0 |
0 |
T18 |
1197 |
1085 |
0 |
0 |
T19 |
1974 |
1933 |
0 |
0 |
T23 |
2529 |
2403 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
348369267 |
346162412 |
0 |
0 |
T1 |
371423 |
370594 |
0 |
0 |
T2 |
238384 |
238304 |
0 |
0 |
T5 |
138985 |
138741 |
0 |
0 |
T6 |
1551 |
1471 |
0 |
0 |
T7 |
2592 |
2484 |
0 |
0 |
T8 |
2283 |
2203 |
0 |
0 |
T17 |
18972 |
18947 |
0 |
0 |
T18 |
1140 |
1033 |
0 |
0 |
T19 |
1894 |
1855 |
0 |
0 |
T23 |
2428 |
2307 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
348369267 |
346162412 |
0 |
0 |
T1 |
371423 |
370594 |
0 |
0 |
T2 |
238384 |
238304 |
0 |
0 |
T5 |
138985 |
138741 |
0 |
0 |
T6 |
1551 |
1471 |
0 |
0 |
T7 |
2592 |
2484 |
0 |
0 |
T8 |
2283 |
2203 |
0 |
0 |
T17 |
18972 |
18947 |
0 |
0 |
T18 |
1140 |
1033 |
0 |
0 |
T19 |
1894 |
1855 |
0 |
0 |
T23 |
2428 |
2307 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
173334352 |
173334352 |
0 |
0 |
T1 |
185381 |
185381 |
0 |
0 |
T2 |
119152 |
119152 |
0 |
0 |
T5 |
69372 |
69372 |
0 |
0 |
T6 |
736 |
736 |
0 |
0 |
T7 |
1242 |
1242 |
0 |
0 |
T8 |
1272 |
1272 |
0 |
0 |
T17 |
9474 |
9474 |
0 |
0 |
T18 |
517 |
517 |
0 |
0 |
T19 |
991 |
991 |
0 |
0 |
T23 |
1194 |
1194 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
173334352 |
173334352 |
0 |
0 |
T1 |
185381 |
185381 |
0 |
0 |
T2 |
119152 |
119152 |
0 |
0 |
T5 |
69372 |
69372 |
0 |
0 |
T6 |
736 |
736 |
0 |
0 |
T7 |
1242 |
1242 |
0 |
0 |
T8 |
1272 |
1272 |
0 |
0 |
T17 |
9474 |
9474 |
0 |
0 |
T18 |
517 |
517 |
0 |
0 |
T19 |
991 |
991 |
0 |
0 |
T23 |
1194 |
1194 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
86666551 |
86666551 |
0 |
0 |
T1 |
926898 |
926898 |
0 |
0 |
T2 |
59576 |
59576 |
0 |
0 |
T5 |
34686 |
34686 |
0 |
0 |
T6 |
368 |
368 |
0 |
0 |
T7 |
621 |
621 |
0 |
0 |
T8 |
635 |
635 |
0 |
0 |
T17 |
4737 |
4737 |
0 |
0 |
T18 |
258 |
258 |
0 |
0 |
T19 |
496 |
496 |
0 |
0 |
T23 |
596 |
596 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
86666551 |
86666551 |
0 |
0 |
T1 |
926898 |
926898 |
0 |
0 |
T2 |
59576 |
59576 |
0 |
0 |
T5 |
34686 |
34686 |
0 |
0 |
T6 |
368 |
368 |
0 |
0 |
T7 |
621 |
621 |
0 |
0 |
T8 |
635 |
635 |
0 |
0 |
T17 |
4737 |
4737 |
0 |
0 |
T18 |
258 |
258 |
0 |
0 |
T19 |
496 |
496 |
0 |
0 |
T23 |
596 |
596 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
178931655 |
177818069 |
0 |
0 |
T1 |
189752 |
189255 |
0 |
0 |
T2 |
119198 |
119158 |
0 |
0 |
T5 |
95417 |
95295 |
0 |
0 |
T6 |
776 |
736 |
0 |
0 |
T7 |
1296 |
1242 |
0 |
0 |
T8 |
1142 |
1102 |
0 |
0 |
T17 |
9554 |
9542 |
0 |
0 |
T18 |
574 |
521 |
0 |
0 |
T19 |
947 |
928 |
0 |
0 |
T23 |
1214 |
1154 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
178931655 |
177818069 |
0 |
0 |
T1 |
189752 |
189255 |
0 |
0 |
T2 |
119198 |
119158 |
0 |
0 |
T5 |
95417 |
95295 |
0 |
0 |
T6 |
776 |
736 |
0 |
0 |
T7 |
1296 |
1242 |
0 |
0 |
T8 |
1142 |
1102 |
0 |
0 |
T17 |
9554 |
9542 |
0 |
0 |
T18 |
574 |
521 |
0 |
0 |
T19 |
947 |
928 |
0 |
0 |
T23 |
1214 |
1154 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Assert Coverage for Instance : tb.dut.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163925371 |
161278095 |
0 |
0 |
T1 |
396705 |
394499 |
0 |
0 |
T2 |
124162 |
124099 |
0 |
0 |
T5 |
192824 |
192398 |
0 |
0 |
T6 |
1551 |
1443 |
0 |
0 |
T7 |
2620 |
2373 |
0 |
0 |
T8 |
2355 |
2145 |
0 |
0 |
T17 |
1134 |
1128 |
0 |
0 |
T18 |
1197 |
1014 |
0 |
0 |
T19 |
1894 |
1773 |
0 |
0 |
T23 |
1214 |
1092 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163925371 |
161270659 |
0 |
2415 |
T1 |
396705 |
394496 |
0 |
3 |
T2 |
124162 |
124096 |
0 |
3 |
T5 |
192824 |
192389 |
0 |
3 |
T6 |
1551 |
1440 |
0 |
3 |
T7 |
2620 |
2370 |
0 |
3 |
T8 |
2355 |
2142 |
0 |
3 |
T17 |
1134 |
1125 |
0 |
3 |
T18 |
1197 |
1011 |
0 |
3 |
T19 |
1894 |
1770 |
0 |
3 |
T23 |
1214 |
1089 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163925371 |
161278095 |
0 |
0 |
T1 |
396705 |
394499 |
0 |
0 |
T2 |
124162 |
124099 |
0 |
0 |
T5 |
192824 |
192398 |
0 |
0 |
T6 |
1551 |
1443 |
0 |
0 |
T7 |
2620 |
2373 |
0 |
0 |
T8 |
2355 |
2145 |
0 |
0 |
T17 |
1134 |
1128 |
0 |
0 |
T18 |
1197 |
1014 |
0 |
0 |
T19 |
1894 |
1773 |
0 |
0 |
T23 |
1214 |
1092 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163925371 |
161270659 |
0 |
2415 |
T1 |
396705 |
394496 |
0 |
3 |
T2 |
124162 |
124096 |
0 |
3 |
T5 |
192824 |
192389 |
0 |
3 |
T6 |
1551 |
1440 |
0 |
3 |
T7 |
2620 |
2370 |
0 |
3 |
T8 |
2355 |
2142 |
0 |
3 |
T17 |
1134 |
1125 |
0 |
3 |
T18 |
1197 |
1011 |
0 |
3 |
T19 |
1894 |
1770 |
0 |
3 |
T23 |
1214 |
1089 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163925371 |
161278095 |
0 |
0 |
T1 |
396705 |
394499 |
0 |
0 |
T2 |
124162 |
124099 |
0 |
0 |
T5 |
192824 |
192398 |
0 |
0 |
T6 |
1551 |
1443 |
0 |
0 |
T7 |
2620 |
2373 |
0 |
0 |
T8 |
2355 |
2145 |
0 |
0 |
T17 |
1134 |
1128 |
0 |
0 |
T18 |
1197 |
1014 |
0 |
0 |
T19 |
1894 |
1773 |
0 |
0 |
T23 |
1214 |
1092 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163925371 |
161270659 |
0 |
2415 |
T1 |
396705 |
394496 |
0 |
3 |
T2 |
124162 |
124096 |
0 |
3 |
T5 |
192824 |
192389 |
0 |
3 |
T6 |
1551 |
1440 |
0 |
3 |
T7 |
2620 |
2370 |
0 |
3 |
T8 |
2355 |
2142 |
0 |
3 |
T17 |
1134 |
1125 |
0 |
3 |
T18 |
1197 |
1011 |
0 |
3 |
T19 |
1894 |
1770 |
0 |
3 |
T23 |
1214 |
1089 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163925371 |
161278095 |
0 |
0 |
T1 |
396705 |
394499 |
0 |
0 |
T2 |
124162 |
124099 |
0 |
0 |
T5 |
192824 |
192398 |
0 |
0 |
T6 |
1551 |
1443 |
0 |
0 |
T7 |
2620 |
2373 |
0 |
0 |
T8 |
2355 |
2145 |
0 |
0 |
T17 |
1134 |
1128 |
0 |
0 |
T18 |
1197 |
1014 |
0 |
0 |
T19 |
1894 |
1773 |
0 |
0 |
T23 |
1214 |
1092 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163925371 |
161270659 |
0 |
2415 |
T1 |
396705 |
394496 |
0 |
3 |
T2 |
124162 |
124096 |
0 |
3 |
T5 |
192824 |
192389 |
0 |
3 |
T6 |
1551 |
1440 |
0 |
3 |
T7 |
2620 |
2370 |
0 |
3 |
T8 |
2355 |
2142 |
0 |
3 |
T17 |
1134 |
1125 |
0 |
3 |
T18 |
1197 |
1011 |
0 |
3 |
T19 |
1894 |
1770 |
0 |
3 |
T23 |
1214 |
1089 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163925371 |
161278095 |
0 |
0 |
T1 |
396705 |
394499 |
0 |
0 |
T2 |
124162 |
124099 |
0 |
0 |
T5 |
192824 |
192398 |
0 |
0 |
T6 |
1551 |
1443 |
0 |
0 |
T7 |
2620 |
2373 |
0 |
0 |
T8 |
2355 |
2145 |
0 |
0 |
T17 |
1134 |
1128 |
0 |
0 |
T18 |
1197 |
1014 |
0 |
0 |
T19 |
1894 |
1773 |
0 |
0 |
T23 |
1214 |
1092 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163925371 |
161270659 |
0 |
2415 |
T1 |
396705 |
394496 |
0 |
3 |
T2 |
124162 |
124096 |
0 |
3 |
T5 |
192824 |
192389 |
0 |
3 |
T6 |
1551 |
1440 |
0 |
3 |
T7 |
2620 |
2370 |
0 |
3 |
T8 |
2355 |
2142 |
0 |
3 |
T17 |
1134 |
1125 |
0 |
3 |
T18 |
1197 |
1011 |
0 |
3 |
T19 |
1894 |
1770 |
0 |
3 |
T23 |
1214 |
1089 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163925371 |
161278095 |
0 |
0 |
T1 |
396705 |
394499 |
0 |
0 |
T2 |
124162 |
124099 |
0 |
0 |
T5 |
192824 |
192398 |
0 |
0 |
T6 |
1551 |
1443 |
0 |
0 |
T7 |
2620 |
2373 |
0 |
0 |
T8 |
2355 |
2145 |
0 |
0 |
T17 |
1134 |
1128 |
0 |
0 |
T18 |
1197 |
1014 |
0 |
0 |
T19 |
1894 |
1773 |
0 |
0 |
T23 |
1214 |
1092 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163925371 |
161270659 |
0 |
2415 |
T1 |
396705 |
394496 |
0 |
3 |
T2 |
124162 |
124096 |
0 |
3 |
T5 |
192824 |
192389 |
0 |
3 |
T6 |
1551 |
1440 |
0 |
3 |
T7 |
2620 |
2370 |
0 |
3 |
T8 |
2355 |
2142 |
0 |
3 |
T17 |
1134 |
1125 |
0 |
3 |
T18 |
1197 |
1011 |
0 |
3 |
T19 |
1894 |
1770 |
0 |
3 |
T23 |
1214 |
1089 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163925371 |
161278095 |
0 |
0 |
T1 |
396705 |
394499 |
0 |
0 |
T2 |
124162 |
124099 |
0 |
0 |
T5 |
192824 |
192398 |
0 |
0 |
T6 |
1551 |
1443 |
0 |
0 |
T7 |
2620 |
2373 |
0 |
0 |
T8 |
2355 |
2145 |
0 |
0 |
T17 |
1134 |
1128 |
0 |
0 |
T18 |
1197 |
1014 |
0 |
0 |
T19 |
1894 |
1773 |
0 |
0 |
T23 |
1214 |
1092 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163925371 |
161278095 |
0 |
0 |
T1 |
396705 |
394499 |
0 |
0 |
T2 |
124162 |
124099 |
0 |
0 |
T5 |
192824 |
192398 |
0 |
0 |
T6 |
1551 |
1443 |
0 |
0 |
T7 |
2620 |
2373 |
0 |
0 |
T8 |
2355 |
2145 |
0 |
0 |
T17 |
1134 |
1128 |
0 |
0 |
T18 |
1197 |
1014 |
0 |
0 |
T19 |
1894 |
1773 |
0 |
0 |
T23 |
1214 |
1092 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163925371 |
161278095 |
0 |
0 |
T1 |
396705 |
394499 |
0 |
0 |
T2 |
124162 |
124099 |
0 |
0 |
T5 |
192824 |
192398 |
0 |
0 |
T6 |
1551 |
1443 |
0 |
0 |
T7 |
2620 |
2373 |
0 |
0 |
T8 |
2355 |
2145 |
0 |
0 |
T17 |
1134 |
1128 |
0 |
0 |
T18 |
1197 |
1014 |
0 |
0 |
T19 |
1894 |
1773 |
0 |
0 |
T23 |
1214 |
1092 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163925371 |
161278095 |
0 |
0 |
T1 |
396705 |
394499 |
0 |
0 |
T2 |
124162 |
124099 |
0 |
0 |
T5 |
192824 |
192398 |
0 |
0 |
T6 |
1551 |
1443 |
0 |
0 |
T7 |
2620 |
2373 |
0 |
0 |
T8 |
2355 |
2145 |
0 |
0 |
T17 |
1134 |
1128 |
0 |
0 |
T18 |
1197 |
1014 |
0 |
0 |
T19 |
1894 |
1773 |
0 |
0 |
T23 |
1214 |
1092 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163925371 |
161278095 |
0 |
0 |
T1 |
396705 |
394499 |
0 |
0 |
T2 |
124162 |
124099 |
0 |
0 |
T5 |
192824 |
192398 |
0 |
0 |
T6 |
1551 |
1443 |
0 |
0 |
T7 |
2620 |
2373 |
0 |
0 |
T8 |
2355 |
2145 |
0 |
0 |
T17 |
1134 |
1128 |
0 |
0 |
T18 |
1197 |
1014 |
0 |
0 |
T19 |
1894 |
1773 |
0 |
0 |
T23 |
1214 |
1092 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163925371 |
161278095 |
0 |
0 |
T1 |
396705 |
394499 |
0 |
0 |
T2 |
124162 |
124099 |
0 |
0 |
T5 |
192824 |
192398 |
0 |
0 |
T6 |
1551 |
1443 |
0 |
0 |
T7 |
2620 |
2373 |
0 |
0 |
T8 |
2355 |
2145 |
0 |
0 |
T17 |
1134 |
1128 |
0 |
0 |
T18 |
1197 |
1014 |
0 |
0 |
T19 |
1894 |
1773 |
0 |
0 |
T23 |
1214 |
1092 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163925371 |
161278095 |
0 |
0 |
T1 |
396705 |
394499 |
0 |
0 |
T2 |
124162 |
124099 |
0 |
0 |
T5 |
192824 |
192398 |
0 |
0 |
T6 |
1551 |
1443 |
0 |
0 |
T7 |
2620 |
2373 |
0 |
0 |
T8 |
2355 |
2145 |
0 |
0 |
T17 |
1134 |
1128 |
0 |
0 |
T18 |
1197 |
1014 |
0 |
0 |
T19 |
1894 |
1773 |
0 |
0 |
T23 |
1214 |
1092 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
163925371 |
161278095 |
0 |
0 |
T1 |
396705 |
394499 |
0 |
0 |
T2 |
124162 |
124099 |
0 |
0 |
T5 |
192824 |
192398 |
0 |
0 |
T6 |
1551 |
1443 |
0 |
0 |
T7 |
2620 |
2373 |
0 |
0 |
T8 |
2355 |
2145 |
0 |
0 |
T17 |
1134 |
1128 |
0 |
0 |
T18 |
1197 |
1014 |
0 |
0 |
T19 |
1894 |
1773 |
0 |
0 |
T23 |
1214 |
1092 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372807150 |
368164639 |
0 |
0 |
T1 |
396512 |
394283 |
0 |
0 |
T2 |
248325 |
248199 |
0 |
0 |
T5 |
180782 |
180341 |
0 |
0 |
T6 |
1616 |
1504 |
0 |
0 |
T7 |
2700 |
2445 |
0 |
0 |
T8 |
2378 |
2166 |
0 |
0 |
T17 |
20184 |
20044 |
0 |
0 |
T18 |
1197 |
1014 |
0 |
0 |
T19 |
1974 |
1847 |
0 |
0 |
T23 |
2529 |
2274 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372807150 |
368157315 |
0 |
2415 |
T1 |
396512 |
394280 |
0 |
3 |
T2 |
248325 |
248196 |
0 |
3 |
T5 |
180782 |
180332 |
0 |
3 |
T6 |
1616 |
1501 |
0 |
3 |
T7 |
2700 |
2442 |
0 |
3 |
T8 |
2378 |
2163 |
0 |
3 |
T17 |
20184 |
20041 |
0 |
3 |
T18 |
1197 |
1011 |
0 |
3 |
T19 |
1974 |
1844 |
0 |
3 |
T23 |
2529 |
2271 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372807150 |
30596 |
0 |
0 |
T1 |
396512 |
345 |
0 |
0 |
T2 |
248325 |
1 |
0 |
0 |
T5 |
180782 |
37 |
0 |
0 |
T6 |
1616 |
3 |
0 |
0 |
T7 |
2700 |
26 |
0 |
0 |
T8 |
2378 |
23 |
0 |
0 |
T17 |
20184 |
21 |
0 |
0 |
T18 |
1197 |
5 |
0 |
0 |
T19 |
1974 |
3 |
0 |
0 |
T23 |
2529 |
5 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372807150 |
368164639 |
0 |
0 |
T1 |
396512 |
394283 |
0 |
0 |
T2 |
248325 |
248199 |
0 |
0 |
T5 |
180782 |
180341 |
0 |
0 |
T6 |
1616 |
1504 |
0 |
0 |
T7 |
2700 |
2445 |
0 |
0 |
T8 |
2378 |
2166 |
0 |
0 |
T17 |
20184 |
20044 |
0 |
0 |
T18 |
1197 |
1014 |
0 |
0 |
T19 |
1974 |
1847 |
0 |
0 |
T23 |
2529 |
2274 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372807150 |
368164639 |
0 |
0 |
T1 |
396512 |
394283 |
0 |
0 |
T2 |
248325 |
248199 |
0 |
0 |
T5 |
180782 |
180341 |
0 |
0 |
T6 |
1616 |
1504 |
0 |
0 |
T7 |
2700 |
2445 |
0 |
0 |
T8 |
2378 |
2166 |
0 |
0 |
T17 |
20184 |
20044 |
0 |
0 |
T18 |
1197 |
1014 |
0 |
0 |
T19 |
1974 |
1847 |
0 |
0 |
T23 |
2529 |
2274 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372807150 |
368164639 |
0 |
0 |
T1 |
396512 |
394283 |
0 |
0 |
T2 |
248325 |
248199 |
0 |
0 |
T5 |
180782 |
180341 |
0 |
0 |
T6 |
1616 |
1504 |
0 |
0 |
T7 |
2700 |
2445 |
0 |
0 |
T8 |
2378 |
2166 |
0 |
0 |
T17 |
20184 |
20044 |
0 |
0 |
T18 |
1197 |
1014 |
0 |
0 |
T19 |
1974 |
1847 |
0 |
0 |
T23 |
2529 |
2274 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372807150 |
368157315 |
0 |
2415 |
T1 |
396512 |
394280 |
0 |
3 |
T2 |
248325 |
248196 |
0 |
3 |
T5 |
180782 |
180332 |
0 |
3 |
T6 |
1616 |
1501 |
0 |
3 |
T7 |
2700 |
2442 |
0 |
3 |
T8 |
2378 |
2163 |
0 |
3 |
T17 |
20184 |
20041 |
0 |
3 |
T18 |
1197 |
1011 |
0 |
3 |
T19 |
1974 |
1844 |
0 |
3 |
T23 |
2529 |
2271 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372807150 |
30536 |
0 |
0 |
T1 |
396512 |
355 |
0 |
0 |
T2 |
248325 |
1 |
0 |
0 |
T5 |
180782 |
55 |
0 |
0 |
T6 |
1616 |
3 |
0 |
0 |
T7 |
2700 |
29 |
0 |
0 |
T8 |
2378 |
19 |
0 |
0 |
T17 |
20184 |
9 |
0 |
0 |
T18 |
1197 |
5 |
0 |
0 |
T19 |
1974 |
10 |
0 |
0 |
T23 |
2529 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372807150 |
368164639 |
0 |
0 |
T1 |
396512 |
394283 |
0 |
0 |
T2 |
248325 |
248199 |
0 |
0 |
T5 |
180782 |
180341 |
0 |
0 |
T6 |
1616 |
1504 |
0 |
0 |
T7 |
2700 |
2445 |
0 |
0 |
T8 |
2378 |
2166 |
0 |
0 |
T17 |
20184 |
20044 |
0 |
0 |
T18 |
1197 |
1014 |
0 |
0 |
T19 |
1974 |
1847 |
0 |
0 |
T23 |
2529 |
2274 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372807150 |
368164639 |
0 |
0 |
T1 |
396512 |
394283 |
0 |
0 |
T2 |
248325 |
248199 |
0 |
0 |
T5 |
180782 |
180341 |
0 |
0 |
T6 |
1616 |
1504 |
0 |
0 |
T7 |
2700 |
2445 |
0 |
0 |
T8 |
2378 |
2166 |
0 |
0 |
T17 |
20184 |
20044 |
0 |
0 |
T18 |
1197 |
1014 |
0 |
0 |
T19 |
1974 |
1847 |
0 |
0 |
T23 |
2529 |
2274 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372807150 |
368164639 |
0 |
0 |
T1 |
396512 |
394283 |
0 |
0 |
T2 |
248325 |
248199 |
0 |
0 |
T5 |
180782 |
180341 |
0 |
0 |
T6 |
1616 |
1504 |
0 |
0 |
T7 |
2700 |
2445 |
0 |
0 |
T8 |
2378 |
2166 |
0 |
0 |
T17 |
20184 |
20044 |
0 |
0 |
T18 |
1197 |
1014 |
0 |
0 |
T19 |
1974 |
1847 |
0 |
0 |
T23 |
2529 |
2274 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372807150 |
368157315 |
0 |
2415 |
T1 |
396512 |
394280 |
0 |
3 |
T2 |
248325 |
248196 |
0 |
3 |
T5 |
180782 |
180332 |
0 |
3 |
T6 |
1616 |
1501 |
0 |
3 |
T7 |
2700 |
2442 |
0 |
3 |
T8 |
2378 |
2163 |
0 |
3 |
T17 |
20184 |
20041 |
0 |
3 |
T18 |
1197 |
1011 |
0 |
3 |
T19 |
1974 |
1844 |
0 |
3 |
T23 |
2529 |
2271 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372807150 |
30757 |
0 |
0 |
T1 |
396512 |
319 |
0 |
0 |
T2 |
248325 |
1 |
0 |
0 |
T5 |
180782 |
47 |
0 |
0 |
T6 |
1616 |
3 |
0 |
0 |
T7 |
2700 |
31 |
0 |
0 |
T8 |
2378 |
19 |
0 |
0 |
T17 |
20184 |
17 |
0 |
0 |
T18 |
1197 |
5 |
0 |
0 |
T19 |
1974 |
6 |
0 |
0 |
T23 |
2529 |
5 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372807150 |
368164639 |
0 |
0 |
T1 |
396512 |
394283 |
0 |
0 |
T2 |
248325 |
248199 |
0 |
0 |
T5 |
180782 |
180341 |
0 |
0 |
T6 |
1616 |
1504 |
0 |
0 |
T7 |
2700 |
2445 |
0 |
0 |
T8 |
2378 |
2166 |
0 |
0 |
T17 |
20184 |
20044 |
0 |
0 |
T18 |
1197 |
1014 |
0 |
0 |
T19 |
1974 |
1847 |
0 |
0 |
T23 |
2529 |
2274 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372807150 |
368164639 |
0 |
0 |
T1 |
396512 |
394283 |
0 |
0 |
T2 |
248325 |
248199 |
0 |
0 |
T5 |
180782 |
180341 |
0 |
0 |
T6 |
1616 |
1504 |
0 |
0 |
T7 |
2700 |
2445 |
0 |
0 |
T8 |
2378 |
2166 |
0 |
0 |
T17 |
20184 |
20044 |
0 |
0 |
T18 |
1197 |
1014 |
0 |
0 |
T19 |
1974 |
1847 |
0 |
0 |
T23 |
2529 |
2274 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372807150 |
368164639 |
0 |
0 |
T1 |
396512 |
394283 |
0 |
0 |
T2 |
248325 |
248199 |
0 |
0 |
T5 |
180782 |
180341 |
0 |
0 |
T6 |
1616 |
1504 |
0 |
0 |
T7 |
2700 |
2445 |
0 |
0 |
T8 |
2378 |
2166 |
0 |
0 |
T17 |
20184 |
20044 |
0 |
0 |
T18 |
1197 |
1014 |
0 |
0 |
T19 |
1974 |
1847 |
0 |
0 |
T23 |
2529 |
2274 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372807150 |
368157315 |
0 |
2415 |
T1 |
396512 |
394280 |
0 |
3 |
T2 |
248325 |
248196 |
0 |
3 |
T5 |
180782 |
180332 |
0 |
3 |
T6 |
1616 |
1501 |
0 |
3 |
T7 |
2700 |
2442 |
0 |
3 |
T8 |
2378 |
2163 |
0 |
3 |
T17 |
20184 |
20041 |
0 |
3 |
T18 |
1197 |
1011 |
0 |
3 |
T19 |
1974 |
1844 |
0 |
3 |
T23 |
2529 |
2271 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372807150 |
30511 |
0 |
0 |
T1 |
396512 |
339 |
0 |
0 |
T2 |
248325 |
1 |
0 |
0 |
T5 |
180782 |
41 |
0 |
0 |
T6 |
1616 |
3 |
0 |
0 |
T7 |
2700 |
33 |
0 |
0 |
T8 |
2378 |
27 |
0 |
0 |
T17 |
20184 |
21 |
0 |
0 |
T18 |
1197 |
1 |
0 |
0 |
T19 |
1974 |
8 |
0 |
0 |
T23 |
2529 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T19 |
1 |
1 |
0 |
0 |
T23 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372807150 |
368164639 |
0 |
0 |
T1 |
396512 |
394283 |
0 |
0 |
T2 |
248325 |
248199 |
0 |
0 |
T5 |
180782 |
180341 |
0 |
0 |
T6 |
1616 |
1504 |
0 |
0 |
T7 |
2700 |
2445 |
0 |
0 |
T8 |
2378 |
2166 |
0 |
0 |
T17 |
20184 |
20044 |
0 |
0 |
T18 |
1197 |
1014 |
0 |
0 |
T19 |
1974 |
1847 |
0 |
0 |
T23 |
2529 |
2274 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372807150 |
368164639 |
0 |
0 |
T1 |
396512 |
394283 |
0 |
0 |
T2 |
248325 |
248199 |
0 |
0 |
T5 |
180782 |
180341 |
0 |
0 |
T6 |
1616 |
1504 |
0 |
0 |
T7 |
2700 |
2445 |
0 |
0 |
T8 |
2378 |
2166 |
0 |
0 |
T17 |
20184 |
20044 |
0 |
0 |
T18 |
1197 |
1014 |
0 |
0 |
T19 |
1974 |
1847 |
0 |
0 |
T23 |
2529 |
2274 |
0 |
0 |