Line Coverage for Module :
clkmgr_trans
| Line No. | Total | Covered | Percent |
TOTAL | | 9 | 9 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 46 | 1 | 1 | 100.00 |
ALWAYS | 140 | 4 | 4 | 100.00 |
ALWAYS | 158 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
45 |
1 |
1 |
46 |
1 |
1 |
140 |
1 |
1 |
141 |
1 |
1 |
142 |
1 |
1 |
143 |
1 |
1 |
|
|
|
MISSING_ELSE |
158 |
1 |
1 |
159 |
1 |
1 |
161 |
1 |
1 |
Cond Coverage for Module :
clkmgr_trans
| Total | Covered | Percent |
Conditions | 10 | 10 | 100.00 |
Logical | 10 | 10 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (idle_cnt == 4'(TransIdleCnt))
---------------1--------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 46
EXPRESSION (sw_hint_synced | ((~idle_valid)))
-------1------ -------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T7,T1,T5 |
0 | 1 | Covered | T6,T7,T8 |
1 | 0 | Covered | T6,T7,T8 |
LINE 106
EXPRESSION (local_en & en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T1,T5 |
1 | 0 | Covered | T6,T7,T8 |
1 | 1 | Covered | T6,T7,T8 |
LINE 125
EXPRESSION (combined_en_d ? MuBi4False : MuBi4True)
------1------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
Branch Coverage for Module :
clkmgr_trans
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
125 |
2 |
2 |
100.00 |
IF |
140 |
3 |
3 |
100.00 |
IF |
158 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 125 (combined_en_d) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 140 if ((!rst_ni))
-2-: 142 if (cnt_err)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T6,T7,T8 |
0 |
1 |
Covered |
T35,T36,T37 |
0 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 158 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans
| Line No. | Total | Covered | Percent |
TOTAL | | 9 | 9 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 46 | 1 | 1 | 100.00 |
ALWAYS | 140 | 4 | 4 | 100.00 |
ALWAYS | 158 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
45 |
1 |
1 |
46 |
1 |
1 |
140 |
1 |
1 |
141 |
1 |
1 |
142 |
1 |
1 |
143 |
1 |
1 |
|
|
|
MISSING_ELSE |
158 |
1 |
1 |
159 |
1 |
1 |
161 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans
| Total | Covered | Percent |
Conditions | 10 | 10 | 100.00 |
Logical | 10 | 10 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (idle_cnt == 4'(TransIdleCnt))
---------------1--------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 46
EXPRESSION (sw_hint_synced | ((~idle_valid)))
-------1------ -------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T7,T1,T5 |
0 | 1 | Covered | T6,T7,T8 |
1 | 0 | Covered | T6,T7,T8 |
LINE 106
EXPRESSION (local_en & en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T1,T5 |
1 | 0 | Covered | T6,T7,T8 |
1 | 1 | Covered | T6,T7,T8 |
LINE 125
EXPRESSION (combined_en_d ? MuBi4False : MuBi4True)
------1------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
125 |
2 |
2 |
100.00 |
IF |
140 |
3 |
3 |
100.00 |
IF |
158 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 125 (combined_en_d) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 140 if ((!rst_ni))
-2-: 142 if (cnt_err)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T6,T7,T8 |
0 |
1 |
Covered |
T35,T36,T37 |
0 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 158 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans
| Line No. | Total | Covered | Percent |
TOTAL | | 9 | 9 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 46 | 1 | 1 | 100.00 |
ALWAYS | 140 | 4 | 4 | 100.00 |
ALWAYS | 158 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
45 |
1 |
1 |
46 |
1 |
1 |
140 |
1 |
1 |
141 |
1 |
1 |
142 |
1 |
1 |
143 |
1 |
1 |
|
|
|
MISSING_ELSE |
158 |
1 |
1 |
159 |
1 |
1 |
161 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans
| Total | Covered | Percent |
Conditions | 10 | 10 | 100.00 |
Logical | 10 | 10 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (idle_cnt == 4'(TransIdleCnt))
---------------1--------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 46
EXPRESSION (sw_hint_synced | ((~idle_valid)))
-------1------ -------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T7,T1,T5 |
0 | 1 | Covered | T6,T7,T8 |
1 | 0 | Covered | T6,T7,T8 |
LINE 106
EXPRESSION (local_en & en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T1,T5 |
1 | 0 | Covered | T6,T7,T8 |
1 | 1 | Covered | T6,T7,T8 |
LINE 125
EXPRESSION (combined_en_d ? MuBi4False : MuBi4True)
------1------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
125 |
2 |
2 |
100.00 |
IF |
140 |
3 |
3 |
100.00 |
IF |
158 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 125 (combined_en_d) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 140 if ((!rst_ni))
-2-: 142 if (cnt_err)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T6,T7,T8 |
0 |
1 |
Covered |
T35,T36,T37 |
0 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 158 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans
| Line No. | Total | Covered | Percent |
TOTAL | | 9 | 9 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 46 | 1 | 1 | 100.00 |
ALWAYS | 140 | 4 | 4 | 100.00 |
ALWAYS | 158 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
45 |
1 |
1 |
46 |
1 |
1 |
140 |
1 |
1 |
141 |
1 |
1 |
142 |
1 |
1 |
143 |
1 |
1 |
|
|
|
MISSING_ELSE |
158 |
1 |
1 |
159 |
1 |
1 |
161 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans
| Total | Covered | Percent |
Conditions | 10 | 10 | 100.00 |
Logical | 10 | 10 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (idle_cnt == 4'(TransIdleCnt))
---------------1--------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 46
EXPRESSION (sw_hint_synced | ((~idle_valid)))
-------1------ -------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T7,T1,T5 |
0 | 1 | Covered | T6,T7,T8 |
1 | 0 | Covered | T6,T7,T8 |
LINE 106
EXPRESSION (local_en & en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T1,T5 |
1 | 0 | Covered | T6,T7,T8 |
1 | 1 | Covered | T6,T7,T8 |
LINE 125
EXPRESSION (combined_en_d ? MuBi4False : MuBi4True)
------1------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
125 |
2 |
2 |
100.00 |
IF |
140 |
3 |
3 |
100.00 |
IF |
158 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 125 (combined_en_d) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 140 if ((!rst_ni))
-2-: 142 if (cnt_err)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T6,T7,T8 |
0 |
1 |
Covered |
T35,T36,T37 |
0 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 158 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans
| Line No. | Total | Covered | Percent |
TOTAL | | 9 | 9 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 46 | 1 | 1 | 100.00 |
ALWAYS | 140 | 4 | 4 | 100.00 |
ALWAYS | 158 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
45 |
1 |
1 |
46 |
1 |
1 |
140 |
1 |
1 |
141 |
1 |
1 |
142 |
1 |
1 |
143 |
1 |
1 |
|
|
|
MISSING_ELSE |
158 |
1 |
1 |
159 |
1 |
1 |
161 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans
| Total | Covered | Percent |
Conditions | 10 | 10 | 100.00 |
Logical | 10 | 10 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 45
EXPRESSION (idle_cnt == 4'(TransIdleCnt))
---------------1--------------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
LINE 46
EXPRESSION (sw_hint_synced | ((~idle_valid)))
-------1------ -------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T7,T1,T5 |
0 | 1 | Covered | T6,T7,T8 |
1 | 0 | Covered | T6,T7,T8 |
LINE 106
EXPRESSION (local_en & en_i)
----1--- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T1,T5 |
1 | 0 | Covered | T6,T7,T8 |
1 | 1 | Covered | T6,T7,T8 |
LINE 125
EXPRESSION (combined_en_d ? MuBi4False : MuBi4True)
------1------
-1- | Status | Tests |
0 | Covered | T6,T7,T8 |
1 | Covered | T6,T7,T8 |
Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
125 |
2 |
2 |
100.00 |
IF |
140 |
3 |
3 |
100.00 |
IF |
158 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 125 (combined_en_d) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 140 if ((!rst_ni))
-2-: 142 if (cnt_err)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T6,T7,T8 |
0 |
1 |
Covered |
T35,T36,T37 |
0 |
0 |
Covered |
T6,T7,T8 |
LineNo. Expression
-1-: 158 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T7,T8 |
0 |
Covered |
T6,T7,T8 |