Module Definition
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Module Instance : tb.dut.u_clkmgr_byp.u_io_byp_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_clkmgr_byp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00
gen_sec_buf.u_prim_sec_buf 100.00 100.00



Module Instance : tb.dut.u_clkmgr_byp.u_all_byp_req

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_clkmgr_byp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00
gen_sec_buf.u_prim_sec_buf 100.00 100.00



Module Instance : tb.dut.u_clkmgr_byp.u_hi_speed_sel

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_clkmgr_byp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_infra

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_main_infra

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_usb_infra

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_infra

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_infra

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_secure

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_main_secure

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_timers

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_peri

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_peri

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_peri

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prim_mubi4_sender_clk_usb_peri

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_aes_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_hmac_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_kmac_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_clk_main_otbn_trans


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00

Line Coverage for Module : prim_mubi4_sender ( parameter AsyncOn=1,EnSecBuf=1,ResetValue=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_clkmgr_byp.u_io_byp_req

SCORELINE
100.00 100.00
tb.dut.u_clkmgr_byp.u_all_byp_req

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
85 1 1


Line Coverage for Module : prim_mubi4_sender ( parameter AsyncOn=1,EnSecBuf=0,ResetValue=6 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_clkmgr_byp.u_hi_speed_sel

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_io_div4_infra

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_main_infra

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_usb_infra

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_io_infra

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_io_div2_infra

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_io_div4_secure

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_main_secure

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_io_div4_timers

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_io_div4_peri

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_io_div2_peri

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_io_peri

SCORELINE
100.00 100.00
tb.dut.u_prim_mubi4_sender_clk_usb_peri

SCORELINE
100.00 100.00
tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender

SCORELINE
100.00 100.00
tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender

SCORELINE
100.00 100.00
tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender

SCORELINE
100.00 100.00
tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender

Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Module : prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 2147483647 2147483647 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 8769891 8731235 0 0
T2 3054208 3052819 0 0
T5 2409456 2403904 0 0
T6 21947 20571 0 0
T7 36804 33525 0 0
T8 33267 30507 0 0
T17 219454 217970 0 0
T18 16267 13954 0 0
T19 27174 25521 0 0
T23 30872 27996 0 0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_byp_req
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_byp_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 163925371 161278095 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 163925371 161278095 0 0
T1 396705 394499 0 0
T2 124162 124099 0 0
T5 192824 192398 0 0
T6 1551 1443 0 0
T7 2620 2373 0 0
T8 2355 2145 0 0
T17 1134 1128 0 0
T18 1197 1014 0 0
T19 1894 1773 0 0
T23 1214 1092 0 0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_byp_req
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_byp_req
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 163925371 161278095 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 163925371 161278095 0 0
T1 396705 394499 0 0
T2 124162 124099 0 0
T5 192824 192398 0 0
T6 1551 1443 0 0
T7 2620 2373 0 0
T8 2355 2145 0 0
T17 1134 1128 0 0
T18 1197 1014 0 0
T19 1894 1773 0 0
T23 1214 1092 0 0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_hi_speed_sel
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_hi_speed_sel
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 163925371 161278095 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 163925371 161278095 0 0
T1 396705 394499 0 0
T2 124162 124099 0 0
T5 192824 192398 0 0
T6 1551 1443 0 0
T7 2620 2373 0 0
T8 2355 2145 0 0
T17 1134 1128 0 0
T18 1197 1014 0 0
T19 1894 1773 0 0
T23 1214 1092 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_infra
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_infra
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 86666551 86113888 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 86666551 86113888 0 0
T1 926898 924039 0 0
T2 59576 59566 0 0
T5 34686 34641 0 0
T6 368 361 0 0
T7 621 587 0 0
T8 635 604 0 0
T17 4737 4709 0 0
T18 258 241 0 0
T19 496 475 0 0
T23 596 565 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_infra
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_infra
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 372807150 368164639 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 372807150 368164639 0 0
T1 396512 394283 0 0
T2 248325 248199 0 0
T5 180782 180341 0 0
T6 1616 1504 0 0
T7 2700 2445 0 0
T8 2378 2166 0 0
T17 20184 20044 0 0
T18 1197 1014 0 0
T19 1974 1847 0 0
T23 2529 2274 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_infra
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_infra
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 178931655 176703991 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 178931655 176703991 0 0
T1 189752 188683 0 0
T2 119198 119138 0 0
T5 95417 95205 0 0
T6 776 722 0 0
T7 1296 1174 0 0
T8 1142 1040 0 0
T17 9554 9487 0 0
T18 574 486 0 0
T19 947 887 0 0
T23 1214 1092 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_infra
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_infra
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 348369267 343952474 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 348369267 343952474 0 0
T1 371423 369451 0 0
T2 238384 238263 0 0
T5 138985 138563 0 0
T6 1551 1443 0 0
T7 2592 2347 0 0
T8 2283 2080 0 0
T17 18972 18837 0 0
T18 1140 964 0 0
T19 1894 1773 0 0
T23 2428 2184 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_infra
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_infra
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 173334352 172228894 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 173334352 172228894 0 0
T1 185381 184808 0 0
T2 119152 119131 0 0
T5 69372 69282 0 0
T6 736 722 0 0
T7 1242 1173 0 0
T8 1272 1210 0 0
T17 9474 9419 0 0
T18 517 482 0 0
T19 991 950 0 0
T23 1194 1132 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_secure
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_secure
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 86666551 86113888 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 86666551 86113888 0 0
T1 926898 924039 0 0
T2 59576 59566 0 0
T5 34686 34641 0 0
T6 368 361 0 0
T7 621 587 0 0
T8 635 604 0 0
T17 4737 4709 0 0
T18 258 241 0 0
T19 496 475 0 0
T23 596 565 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_secure
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_secure
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 372807150 368164639 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 372807150 368164639 0 0
T1 396512 394283 0 0
T2 248325 248199 0 0
T5 180782 180341 0 0
T6 1616 1504 0 0
T7 2700 2445 0 0
T8 2378 2166 0 0
T17 20184 20044 0 0
T18 1197 1014 0 0
T19 1974 1847 0 0
T23 2529 2274 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_timers
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_timers
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 86666551 86113888 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 86666551 86113888 0 0
T1 926898 924039 0 0
T2 59576 59566 0 0
T5 34686 34641 0 0
T6 368 361 0 0
T7 621 587 0 0
T8 635 604 0 0
T17 4737 4709 0 0
T18 258 241 0 0
T19 496 475 0 0
T23 596 565 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_peri
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_peri
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 86666551 86113888 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 86666551 86113888 0 0
T1 926898 924039 0 0
T2 59576 59566 0 0
T5 34686 34641 0 0
T6 368 361 0 0
T7 621 587 0 0
T8 635 604 0 0
T17 4737 4709 0 0
T18 258 241 0 0
T19 496 475 0 0
T23 596 565 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_peri
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_peri
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 173334352 172228894 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 173334352 172228894 0 0
T1 185381 184808 0 0
T2 119152 119131 0 0
T5 69372 69282 0 0
T6 736 722 0 0
T7 1242 1173 0 0
T8 1272 1210 0 0
T17 9474 9419 0 0
T18 517 482 0 0
T19 991 950 0 0
T23 1194 1132 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_peri
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_peri
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 348369267 343952474 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 348369267 343952474 0 0
T1 371423 369451 0 0
T2 238384 238263 0 0
T5 138985 138563 0 0
T6 1551 1443 0 0
T7 2592 2347 0 0
T8 2283 2080 0 0
T17 18972 18837 0 0
T18 1140 964 0 0
T19 1894 1773 0 0
T23 2428 2184 0 0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_peri
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_peri
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 178931655 176703991 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 178931655 176703991 0 0
T1 189752 188683 0 0
T2 119198 119138 0 0
T5 95417 95205 0 0
T6 776 722 0 0
T7 1296 1174 0 0
T8 1142 1040 0 0
T17 9554 9487 0 0
T18 574 486 0 0
T19 947 887 0 0
T23 1214 1092 0 0

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 372807150 368164639 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 372807150 368164639 0 0
T1 396512 394283 0 0
T2 248325 248199 0 0
T5 180782 180341 0 0
T6 1616 1504 0 0
T7 2700 2445 0 0
T8 2378 2166 0 0
T17 20184 20044 0 0
T18 1197 1014 0 0
T19 1974 1847 0 0
T23 2529 2274 0 0

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 372807150 368164639 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 372807150 368164639 0 0
T1 396512 394283 0 0
T2 248325 248199 0 0
T5 180782 180341 0 0
T6 1616 1504 0 0
T7 2700 2445 0 0
T8 2378 2166 0 0
T17 20184 20044 0 0
T18 1197 1014 0 0
T19 1974 1847 0 0
T23 2529 2274 0 0

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 372807150 368164639 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 372807150 368164639 0 0
T1 396512 394283 0 0
T2 248325 248199 0 0
T5 180782 180341 0 0
T6 1616 1504 0 0
T7 2700 2445 0 0
T8 2378 2166 0 0
T17 20184 20044 0 0
T18 1197 1014 0 0
T19 1974 1847 0 0
T23 2529 2274 0 0

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 372807150 368164639 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 372807150 368164639 0 0
T1 396512 394283 0 0
T2 248325 248199 0 0
T5 180782 180341 0 0
T6 1616 1504 0 0
T7 2700 2445 0 0
T8 2378 2166 0 0
T17 20184 20044 0 0
T18 1197 1014 0 0
T19 1974 1847 0 0
T23 2529 2274 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%