Line Coverage for Module :
prim_reg_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Module :
prim_reg_cdc
| Total | Covered | Percent |
Conditions | 15 | 13 | 86.67 |
Logical | 15 | 13 | 86.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Covered | T1,T2,T20 |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T5 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_reg_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T1,T5 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T1,T5 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T1,T5 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T1,T5 |
Assert Coverage for Module :
prim_reg_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1625600830 |
1433991 |
0 |
0 |
T1 |
3147040 |
13917 |
0 |
0 |
T2 |
3515880 |
38490 |
0 |
0 |
T3 |
4230550 |
7536 |
0 |
0 |
T5 |
12700 |
0 |
0 |
0 |
T9 |
0 |
1812 |
0 |
0 |
T10 |
0 |
1386 |
0 |
0 |
T16 |
20130 |
0 |
0 |
0 |
T17 |
10920 |
0 |
0 |
0 |
T18 |
6810 |
0 |
0 |
0 |
T19 |
24310 |
0 |
0 |
0 |
T20 |
85780 |
409 |
0 |
0 |
T21 |
707620 |
3127 |
0 |
0 |
T22 |
0 |
252 |
0 |
0 |
T26 |
0 |
4313 |
0 |
0 |
T27 |
0 |
1041 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
4280632 |
4263908 |
0 |
0 |
T2 |
3628038 |
3598314 |
0 |
0 |
T3 |
5352672 |
5343292 |
0 |
0 |
T4 |
33408 |
32308 |
0 |
0 |
T5 |
32036 |
30974 |
0 |
0 |
T16 |
12838 |
11732 |
0 |
0 |
T17 |
13900 |
13102 |
0 |
0 |
T18 |
17108 |
15820 |
0 |
0 |
T19 |
15828 |
14492 |
0 |
0 |
T20 |
207016 |
63420 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1625600830 |
267375 |
0 |
0 |
T1 |
3147040 |
2075 |
0 |
0 |
T2 |
3515880 |
4600 |
0 |
0 |
T3 |
4230550 |
1440 |
0 |
0 |
T5 |
12700 |
0 |
0 |
0 |
T9 |
0 |
220 |
0 |
0 |
T10 |
0 |
400 |
0 |
0 |
T16 |
20130 |
0 |
0 |
0 |
T17 |
10920 |
0 |
0 |
0 |
T18 |
6810 |
0 |
0 |
0 |
T19 |
24310 |
0 |
0 |
0 |
T20 |
85780 |
118 |
0 |
0 |
T21 |
707620 |
482 |
0 |
0 |
T22 |
0 |
80 |
0 |
0 |
T26 |
0 |
493 |
0 |
0 |
T27 |
0 |
310 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1625600830 |
1597877870 |
0 |
0 |
T1 |
3147040 |
3127530 |
0 |
0 |
T2 |
3515880 |
3478090 |
0 |
0 |
T3 |
4230550 |
4222500 |
0 |
0 |
T4 |
12520 |
12080 |
0 |
0 |
T5 |
12700 |
12250 |
0 |
0 |
T16 |
20130 |
18200 |
0 |
0 |
T17 |
10920 |
10160 |
0 |
0 |
T18 |
6810 |
6250 |
0 |
0 |
T19 |
24310 |
22010 |
0 |
0 |
T20 |
85780 |
24120 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc
| Total | Covered | Percent |
Conditions | 14 | 12 | 85.71 |
Logical | 14 | 12 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T5 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T1,T5 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T1,T5 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T1,T5 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T1,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162560083 |
87986 |
0 |
0 |
T1 |
314704 |
866 |
0 |
0 |
T2 |
351588 |
2712 |
0 |
0 |
T3 |
423055 |
508 |
0 |
0 |
T5 |
1270 |
0 |
0 |
0 |
T9 |
0 |
129 |
0 |
0 |
T10 |
0 |
104 |
0 |
0 |
T16 |
2013 |
0 |
0 |
0 |
T17 |
1092 |
0 |
0 |
0 |
T18 |
681 |
0 |
0 |
0 |
T19 |
2431 |
0 |
0 |
0 |
T20 |
8578 |
20 |
0 |
0 |
T21 |
70762 |
143 |
0 |
0 |
T22 |
0 |
18 |
0 |
0 |
T26 |
0 |
178 |
0 |
0 |
T27 |
0 |
52 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
367770873 |
363054976 |
0 |
0 |
T1 |
381519 |
379883 |
0 |
0 |
T2 |
321061 |
317631 |
0 |
0 |
T3 |
794231 |
792617 |
0 |
0 |
T4 |
5010 |
4834 |
0 |
0 |
T5 |
4881 |
4705 |
0 |
0 |
T16 |
1971 |
1782 |
0 |
0 |
T17 |
2139 |
1990 |
0 |
0 |
T18 |
2620 |
2403 |
0 |
0 |
T19 |
2431 |
2201 |
0 |
0 |
T20 |
34316 |
9633 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162560083 |
23811 |
0 |
0 |
T1 |
314704 |
201 |
0 |
0 |
T2 |
351588 |
454 |
0 |
0 |
T3 |
423055 |
144 |
0 |
0 |
T5 |
1270 |
0 |
0 |
0 |
T9 |
0 |
22 |
0 |
0 |
T10 |
0 |
40 |
0 |
0 |
T16 |
2013 |
0 |
0 |
0 |
T17 |
1092 |
0 |
0 |
0 |
T18 |
681 |
0 |
0 |
0 |
T19 |
2431 |
0 |
0 |
0 |
T20 |
8578 |
8 |
0 |
0 |
T21 |
70762 |
34 |
0 |
0 |
T22 |
0 |
8 |
0 |
0 |
T26 |
0 |
34 |
0 |
0 |
T27 |
0 |
22 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162560083 |
159787787 |
0 |
0 |
T1 |
314704 |
312753 |
0 |
0 |
T2 |
351588 |
347809 |
0 |
0 |
T3 |
423055 |
422250 |
0 |
0 |
T4 |
1252 |
1208 |
0 |
0 |
T5 |
1270 |
1225 |
0 |
0 |
T16 |
2013 |
1820 |
0 |
0 |
T17 |
1092 |
1016 |
0 |
0 |
T18 |
681 |
625 |
0 |
0 |
T19 |
2431 |
2201 |
0 |
0 |
T20 |
8578 |
2412 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc
| Total | Covered | Percent |
Conditions | 14 | 12 | 85.71 |
Logical | 14 | 12 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T5 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T1,T5 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T1,T5 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T1,T5 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T1,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162560083 |
129322 |
0 |
0 |
T1 |
314704 |
1343 |
0 |
0 |
T2 |
351588 |
3868 |
0 |
0 |
T3 |
423055 |
726 |
0 |
0 |
T5 |
1270 |
0 |
0 |
0 |
T9 |
0 |
188 |
0 |
0 |
T10 |
0 |
140 |
0 |
0 |
T16 |
2013 |
0 |
0 |
0 |
T17 |
1092 |
0 |
0 |
0 |
T18 |
681 |
0 |
0 |
0 |
T19 |
2431 |
0 |
0 |
0 |
T20 |
8578 |
28 |
0 |
0 |
T21 |
70762 |
222 |
0 |
0 |
T22 |
0 |
26 |
0 |
0 |
T26 |
0 |
284 |
0 |
0 |
T27 |
0 |
73 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
182936896 |
181772518 |
0 |
0 |
T1 |
190611 |
190131 |
0 |
0 |
T2 |
159861 |
158927 |
0 |
0 |
T3 |
397135 |
396741 |
0 |
0 |
T4 |
2647 |
2578 |
0 |
0 |
T5 |
2408 |
2353 |
0 |
0 |
T16 |
939 |
891 |
0 |
0 |
T17 |
1009 |
995 |
0 |
0 |
T18 |
1263 |
1201 |
0 |
0 |
T19 |
1155 |
1100 |
0 |
0 |
T20 |
10858 |
4817 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162560083 |
23811 |
0 |
0 |
T1 |
314704 |
201 |
0 |
0 |
T2 |
351588 |
454 |
0 |
0 |
T3 |
423055 |
144 |
0 |
0 |
T5 |
1270 |
0 |
0 |
0 |
T9 |
0 |
22 |
0 |
0 |
T10 |
0 |
40 |
0 |
0 |
T16 |
2013 |
0 |
0 |
0 |
T17 |
1092 |
0 |
0 |
0 |
T18 |
681 |
0 |
0 |
0 |
T19 |
2431 |
0 |
0 |
0 |
T20 |
8578 |
8 |
0 |
0 |
T21 |
70762 |
34 |
0 |
0 |
T22 |
0 |
8 |
0 |
0 |
T26 |
0 |
34 |
0 |
0 |
T27 |
0 |
22 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162560083 |
159787787 |
0 |
0 |
T1 |
314704 |
312753 |
0 |
0 |
T2 |
351588 |
347809 |
0 |
0 |
T3 |
423055 |
422250 |
0 |
0 |
T4 |
1252 |
1208 |
0 |
0 |
T5 |
1270 |
1225 |
0 |
0 |
T16 |
2013 |
1820 |
0 |
0 |
T17 |
1092 |
1016 |
0 |
0 |
T18 |
681 |
625 |
0 |
0 |
T19 |
2431 |
2201 |
0 |
0 |
T20 |
8578 |
2412 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc
| Total | Covered | Percent |
Conditions | 14 | 12 | 85.71 |
Logical | 14 | 12 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T5 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T1,T5 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T1,T5 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T1,T5 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T1,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162560083 |
209541 |
0 |
0 |
T1 |
314704 |
2309 |
0 |
0 |
T2 |
351588 |
6568 |
0 |
0 |
T3 |
423055 |
1165 |
0 |
0 |
T5 |
1270 |
0 |
0 |
0 |
T9 |
0 |
313 |
0 |
0 |
T10 |
0 |
206 |
0 |
0 |
T16 |
2013 |
0 |
0 |
0 |
T17 |
1092 |
0 |
0 |
0 |
T18 |
681 |
0 |
0 |
0 |
T19 |
2431 |
0 |
0 |
0 |
T20 |
8578 |
40 |
0 |
0 |
T21 |
70762 |
372 |
0 |
0 |
T22 |
0 |
36 |
0 |
0 |
T26 |
0 |
499 |
0 |
0 |
T27 |
0 |
99 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
91467859 |
90885786 |
0 |
0 |
T1 |
953038 |
950642 |
0 |
0 |
T2 |
799302 |
794631 |
0 |
0 |
T3 |
198565 |
198369 |
0 |
0 |
T4 |
1323 |
1289 |
0 |
0 |
T5 |
1204 |
1176 |
0 |
0 |
T16 |
470 |
446 |
0 |
0 |
T17 |
505 |
498 |
0 |
0 |
T18 |
632 |
601 |
0 |
0 |
T19 |
578 |
551 |
0 |
0 |
T20 |
5429 |
2408 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162560083 |
23811 |
0 |
0 |
T1 |
314704 |
201 |
0 |
0 |
T2 |
351588 |
454 |
0 |
0 |
T3 |
423055 |
144 |
0 |
0 |
T5 |
1270 |
0 |
0 |
0 |
T9 |
0 |
22 |
0 |
0 |
T10 |
0 |
40 |
0 |
0 |
T16 |
2013 |
0 |
0 |
0 |
T17 |
1092 |
0 |
0 |
0 |
T18 |
681 |
0 |
0 |
0 |
T19 |
2431 |
0 |
0 |
0 |
T20 |
8578 |
8 |
0 |
0 |
T21 |
70762 |
34 |
0 |
0 |
T22 |
0 |
8 |
0 |
0 |
T26 |
0 |
34 |
0 |
0 |
T27 |
0 |
22 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162560083 |
159787787 |
0 |
0 |
T1 |
314704 |
312753 |
0 |
0 |
T2 |
351588 |
347809 |
0 |
0 |
T3 |
423055 |
422250 |
0 |
0 |
T4 |
1252 |
1208 |
0 |
0 |
T5 |
1270 |
1225 |
0 |
0 |
T16 |
2013 |
1820 |
0 |
0 |
T17 |
1092 |
1016 |
0 |
0 |
T18 |
681 |
625 |
0 |
0 |
T19 |
2431 |
2201 |
0 |
0 |
T20 |
8578 |
2412 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc
| Total | Covered | Percent |
Conditions | 14 | 12 | 85.71 |
Logical | 14 | 12 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T5 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T1,T5 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T1,T5 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T1,T5 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T1,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162560083 |
86891 |
0 |
0 |
T1 |
314704 |
840 |
0 |
0 |
T2 |
351588 |
2206 |
0 |
0 |
T3 |
423055 |
502 |
0 |
0 |
T5 |
1270 |
0 |
0 |
0 |
T9 |
0 |
105 |
0 |
0 |
T10 |
0 |
99 |
0 |
0 |
T16 |
2013 |
0 |
0 |
0 |
T17 |
1092 |
0 |
0 |
0 |
T18 |
681 |
0 |
0 |
0 |
T19 |
2431 |
0 |
0 |
0 |
T20 |
8578 |
20 |
0 |
0 |
T21 |
70762 |
143 |
0 |
0 |
T22 |
0 |
18 |
0 |
0 |
T26 |
0 |
206 |
0 |
0 |
T27 |
0 |
52 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393526195 |
388543939 |
0 |
0 |
T1 |
417195 |
414594 |
0 |
0 |
T2 |
361449 |
357512 |
0 |
0 |
T3 |
863350 |
861669 |
0 |
0 |
T4 |
5219 |
5036 |
0 |
0 |
T5 |
5085 |
4901 |
0 |
0 |
T16 |
2053 |
1856 |
0 |
0 |
T17 |
2228 |
2073 |
0 |
0 |
T18 |
2729 |
2503 |
0 |
0 |
T19 |
2534 |
2293 |
0 |
0 |
T20 |
35747 |
10035 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162560083 |
23811 |
0 |
0 |
T1 |
314704 |
201 |
0 |
0 |
T2 |
351588 |
454 |
0 |
0 |
T3 |
423055 |
144 |
0 |
0 |
T5 |
1270 |
0 |
0 |
0 |
T9 |
0 |
22 |
0 |
0 |
T10 |
0 |
40 |
0 |
0 |
T16 |
2013 |
0 |
0 |
0 |
T17 |
1092 |
0 |
0 |
0 |
T18 |
681 |
0 |
0 |
0 |
T19 |
2431 |
0 |
0 |
0 |
T20 |
8578 |
8 |
0 |
0 |
T21 |
70762 |
34 |
0 |
0 |
T22 |
0 |
8 |
0 |
0 |
T26 |
0 |
34 |
0 |
0 |
T27 |
0 |
22 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162560083 |
159787787 |
0 |
0 |
T1 |
314704 |
312753 |
0 |
0 |
T2 |
351588 |
347809 |
0 |
0 |
T3 |
423055 |
422250 |
0 |
0 |
T4 |
1252 |
1208 |
0 |
0 |
T5 |
1270 |
1225 |
0 |
0 |
T16 |
2013 |
1820 |
0 |
0 |
T17 |
1092 |
1016 |
0 |
0 |
T18 |
681 |
625 |
0 |
0 |
T19 |
2431 |
2201 |
0 |
0 |
T20 |
8578 |
2412 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc
| Total | Covered | Percent |
Conditions | 14 | 12 | 85.71 |
Logical | 14 | 12 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T5 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T1,T5 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T1,T5 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T1,T5 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T1,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162560083 |
126913 |
0 |
0 |
T1 |
314704 |
1344 |
0 |
0 |
T2 |
351588 |
3627 |
0 |
0 |
T3 |
423055 |
870 |
0 |
0 |
T5 |
1270 |
0 |
0 |
0 |
T9 |
0 |
173 |
0 |
0 |
T10 |
0 |
143 |
0 |
0 |
T16 |
2013 |
0 |
0 |
0 |
T17 |
1092 |
0 |
0 |
0 |
T18 |
681 |
0 |
0 |
0 |
T19 |
2431 |
0 |
0 |
0 |
T20 |
8578 |
23 |
0 |
0 |
T21 |
70762 |
132 |
0 |
0 |
T22 |
0 |
28 |
0 |
0 |
T26 |
0 |
209 |
0 |
0 |
T27 |
0 |
48 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
188847735 |
186460301 |
0 |
0 |
T1 |
197953 |
196704 |
0 |
0 |
T2 |
172346 |
170456 |
0 |
0 |
T3 |
423055 |
422250 |
0 |
0 |
T4 |
2505 |
2417 |
0 |
0 |
T5 |
2440 |
2352 |
0 |
0 |
T16 |
986 |
891 |
0 |
0 |
T17 |
1069 |
995 |
0 |
0 |
T18 |
1310 |
1202 |
0 |
0 |
T19 |
1216 |
1101 |
0 |
0 |
T20 |
17158 |
4817 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162560083 |
23295 |
0 |
0 |
T1 |
314704 |
201 |
0 |
0 |
T2 |
351588 |
454 |
0 |
0 |
T3 |
423055 |
144 |
0 |
0 |
T5 |
1270 |
0 |
0 |
0 |
T9 |
0 |
22 |
0 |
0 |
T10 |
0 |
40 |
0 |
0 |
T16 |
2013 |
0 |
0 |
0 |
T17 |
1092 |
0 |
0 |
0 |
T18 |
681 |
0 |
0 |
0 |
T19 |
2431 |
0 |
0 |
0 |
T20 |
8578 |
6 |
0 |
0 |
T21 |
70762 |
17 |
0 |
0 |
T22 |
0 |
8 |
0 |
0 |
T26 |
0 |
20 |
0 |
0 |
T27 |
0 |
11 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162560083 |
159787787 |
0 |
0 |
T1 |
314704 |
312753 |
0 |
0 |
T2 |
351588 |
347809 |
0 |
0 |
T3 |
423055 |
422250 |
0 |
0 |
T4 |
1252 |
1208 |
0 |
0 |
T5 |
1270 |
1225 |
0 |
0 |
T16 |
2013 |
1820 |
0 |
0 |
T17 |
1092 |
1016 |
0 |
0 |
T18 |
681 |
625 |
0 |
0 |
T19 |
2431 |
2201 |
0 |
0 |
T20 |
8578 |
2412 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc
| Total | Covered | Percent |
Conditions | 12 | 11 | 91.67 |
Logical | 12 | 11 | 91.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Covered | T1,T2,T20 |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T5 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T1,T5 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T1,T5 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T1,T5 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T1,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162560083 |
109289 |
0 |
0 |
T1 |
314704 |
932 |
0 |
0 |
T2 |
351588 |
2780 |
0 |
0 |
T3 |
423055 |
506 |
0 |
0 |
T5 |
1270 |
0 |
0 |
0 |
T9 |
0 |
130 |
0 |
0 |
T10 |
0 |
103 |
0 |
0 |
T16 |
2013 |
0 |
0 |
0 |
T17 |
1092 |
0 |
0 |
0 |
T18 |
681 |
0 |
0 |
0 |
T19 |
2431 |
0 |
0 |
0 |
T20 |
8578 |
41 |
0 |
0 |
T21 |
70762 |
276 |
0 |
0 |
T22 |
0 |
18 |
0 |
0 |
T26 |
0 |
359 |
0 |
0 |
T27 |
0 |
107 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
367770873 |
363054976 |
0 |
0 |
T1 |
381519 |
379883 |
0 |
0 |
T2 |
321061 |
317631 |
0 |
0 |
T3 |
794231 |
792617 |
0 |
0 |
T4 |
5010 |
4834 |
0 |
0 |
T5 |
4881 |
4705 |
0 |
0 |
T16 |
1971 |
1782 |
0 |
0 |
T17 |
2139 |
1990 |
0 |
0 |
T18 |
2620 |
2403 |
0 |
0 |
T19 |
2431 |
2201 |
0 |
0 |
T20 |
34316 |
9633 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162560083 |
29880 |
0 |
0 |
T1 |
314704 |
214 |
0 |
0 |
T2 |
351588 |
466 |
0 |
0 |
T3 |
423055 |
144 |
0 |
0 |
T5 |
1270 |
0 |
0 |
0 |
T9 |
0 |
22 |
0 |
0 |
T10 |
0 |
40 |
0 |
0 |
T16 |
2013 |
0 |
0 |
0 |
T17 |
1092 |
0 |
0 |
0 |
T18 |
681 |
0 |
0 |
0 |
T19 |
2431 |
0 |
0 |
0 |
T20 |
8578 |
16 |
0 |
0 |
T21 |
70762 |
68 |
0 |
0 |
T22 |
0 |
8 |
0 |
0 |
T26 |
0 |
68 |
0 |
0 |
T27 |
0 |
44 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162560083 |
159787787 |
0 |
0 |
T1 |
314704 |
312753 |
0 |
0 |
T2 |
351588 |
347809 |
0 |
0 |
T3 |
423055 |
422250 |
0 |
0 |
T4 |
1252 |
1208 |
0 |
0 |
T5 |
1270 |
1225 |
0 |
0 |
T16 |
2013 |
1820 |
0 |
0 |
T17 |
1092 |
1016 |
0 |
0 |
T18 |
681 |
625 |
0 |
0 |
T19 |
2431 |
2201 |
0 |
0 |
T20 |
8578 |
2412 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc
| Total | Covered | Percent |
Conditions | 12 | 11 | 91.67 |
Logical | 12 | 11 | 91.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Covered | T1,T2,T20 |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T5 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T1,T5 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T1,T5 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T1,T5 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T1,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162560083 |
158551 |
0 |
0 |
T1 |
314704 |
1430 |
0 |
0 |
T2 |
351588 |
3948 |
0 |
0 |
T3 |
423055 |
724 |
0 |
0 |
T5 |
1270 |
0 |
0 |
0 |
T9 |
0 |
183 |
0 |
0 |
T10 |
0 |
144 |
0 |
0 |
T16 |
2013 |
0 |
0 |
0 |
T17 |
1092 |
0 |
0 |
0 |
T18 |
681 |
0 |
0 |
0 |
T19 |
2431 |
0 |
0 |
0 |
T20 |
8578 |
57 |
0 |
0 |
T21 |
70762 |
429 |
0 |
0 |
T22 |
0 |
26 |
0 |
0 |
T26 |
0 |
586 |
0 |
0 |
T27 |
0 |
149 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
182936896 |
181772518 |
0 |
0 |
T1 |
190611 |
190131 |
0 |
0 |
T2 |
159861 |
158927 |
0 |
0 |
T3 |
397135 |
396741 |
0 |
0 |
T4 |
2647 |
2578 |
0 |
0 |
T5 |
2408 |
2353 |
0 |
0 |
T16 |
939 |
891 |
0 |
0 |
T17 |
1009 |
995 |
0 |
0 |
T18 |
1263 |
1201 |
0 |
0 |
T19 |
1155 |
1100 |
0 |
0 |
T20 |
10858 |
4817 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162560083 |
29611 |
0 |
0 |
T1 |
314704 |
214 |
0 |
0 |
T2 |
351588 |
466 |
0 |
0 |
T3 |
423055 |
144 |
0 |
0 |
T5 |
1270 |
0 |
0 |
0 |
T9 |
0 |
22 |
0 |
0 |
T10 |
0 |
40 |
0 |
0 |
T16 |
2013 |
0 |
0 |
0 |
T17 |
1092 |
0 |
0 |
0 |
T18 |
681 |
0 |
0 |
0 |
T19 |
2431 |
0 |
0 |
0 |
T20 |
8578 |
16 |
0 |
0 |
T21 |
70762 |
68 |
0 |
0 |
T22 |
0 |
8 |
0 |
0 |
T26 |
0 |
68 |
0 |
0 |
T27 |
0 |
44 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162560083 |
159787787 |
0 |
0 |
T1 |
314704 |
312753 |
0 |
0 |
T2 |
351588 |
347809 |
0 |
0 |
T3 |
423055 |
422250 |
0 |
0 |
T4 |
1252 |
1208 |
0 |
0 |
T5 |
1270 |
1225 |
0 |
0 |
T16 |
2013 |
1820 |
0 |
0 |
T17 |
1092 |
1016 |
0 |
0 |
T18 |
681 |
625 |
0 |
0 |
T19 |
2431 |
2201 |
0 |
0 |
T20 |
8578 |
2412 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc
| Total | Covered | Percent |
Conditions | 12 | 11 | 91.67 |
Logical | 12 | 11 | 91.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Covered | T1,T2,T20 |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T5 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T1,T5 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T1,T5 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T1,T5 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T1,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162560083 |
257515 |
0 |
0 |
T1 |
314704 |
2490 |
0 |
0 |
T2 |
351588 |
6813 |
0 |
0 |
T3 |
423055 |
1166 |
0 |
0 |
T5 |
1270 |
0 |
0 |
0 |
T9 |
0 |
311 |
0 |
0 |
T10 |
0 |
204 |
0 |
0 |
T16 |
2013 |
0 |
0 |
0 |
T17 |
1092 |
0 |
0 |
0 |
T18 |
681 |
0 |
0 |
0 |
T19 |
2431 |
0 |
0 |
0 |
T20 |
8578 |
82 |
0 |
0 |
T21 |
70762 |
730 |
0 |
0 |
T22 |
0 |
38 |
0 |
0 |
T26 |
0 |
1008 |
0 |
0 |
T27 |
0 |
211 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
91467859 |
90885786 |
0 |
0 |
T1 |
953038 |
950642 |
0 |
0 |
T2 |
799302 |
794631 |
0 |
0 |
T3 |
198565 |
198369 |
0 |
0 |
T4 |
1323 |
1289 |
0 |
0 |
T5 |
1204 |
1176 |
0 |
0 |
T16 |
470 |
446 |
0 |
0 |
T17 |
505 |
498 |
0 |
0 |
T18 |
632 |
601 |
0 |
0 |
T19 |
578 |
551 |
0 |
0 |
T20 |
5429 |
2408 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162560083 |
29743 |
0 |
0 |
T1 |
314704 |
214 |
0 |
0 |
T2 |
351588 |
466 |
0 |
0 |
T3 |
423055 |
144 |
0 |
0 |
T5 |
1270 |
0 |
0 |
0 |
T9 |
0 |
22 |
0 |
0 |
T10 |
0 |
40 |
0 |
0 |
T16 |
2013 |
0 |
0 |
0 |
T17 |
1092 |
0 |
0 |
0 |
T18 |
681 |
0 |
0 |
0 |
T19 |
2431 |
0 |
0 |
0 |
T20 |
8578 |
16 |
0 |
0 |
T21 |
70762 |
68 |
0 |
0 |
T22 |
0 |
8 |
0 |
0 |
T26 |
0 |
68 |
0 |
0 |
T27 |
0 |
44 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162560083 |
159787787 |
0 |
0 |
T1 |
314704 |
312753 |
0 |
0 |
T2 |
351588 |
347809 |
0 |
0 |
T3 |
423055 |
422250 |
0 |
0 |
T4 |
1252 |
1208 |
0 |
0 |
T5 |
1270 |
1225 |
0 |
0 |
T16 |
2013 |
1820 |
0 |
0 |
T17 |
1092 |
1016 |
0 |
0 |
T18 |
681 |
625 |
0 |
0 |
T19 |
2431 |
2201 |
0 |
0 |
T20 |
8578 |
2412 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc
| Total | Covered | Percent |
Conditions | 12 | 11 | 91.67 |
Logical | 12 | 11 | 91.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Covered | T1,T2,T20 |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T5 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T1,T5 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T1,T5 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T1,T5 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T1,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162560083 |
108541 |
0 |
0 |
T1 |
314704 |
910 |
0 |
0 |
T2 |
351588 |
2262 |
0 |
0 |
T3 |
423055 |
501 |
0 |
0 |
T5 |
1270 |
0 |
0 |
0 |
T9 |
0 |
106 |
0 |
0 |
T10 |
0 |
100 |
0 |
0 |
T16 |
2013 |
0 |
0 |
0 |
T17 |
1092 |
0 |
0 |
0 |
T18 |
681 |
0 |
0 |
0 |
T19 |
2431 |
0 |
0 |
0 |
T20 |
8578 |
41 |
0 |
0 |
T21 |
70762 |
271 |
0 |
0 |
T22 |
0 |
18 |
0 |
0 |
T26 |
0 |
416 |
0 |
0 |
T27 |
0 |
107 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393526195 |
388543939 |
0 |
0 |
T1 |
417195 |
414594 |
0 |
0 |
T2 |
361449 |
357512 |
0 |
0 |
T3 |
863350 |
861669 |
0 |
0 |
T4 |
5219 |
5036 |
0 |
0 |
T5 |
5085 |
4901 |
0 |
0 |
T16 |
2053 |
1856 |
0 |
0 |
T17 |
2228 |
2073 |
0 |
0 |
T18 |
2729 |
2503 |
0 |
0 |
T19 |
2534 |
2293 |
0 |
0 |
T20 |
35747 |
10035 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162560083 |
29933 |
0 |
0 |
T1 |
314704 |
214 |
0 |
0 |
T2 |
351588 |
466 |
0 |
0 |
T3 |
423055 |
144 |
0 |
0 |
T5 |
1270 |
0 |
0 |
0 |
T9 |
0 |
22 |
0 |
0 |
T10 |
0 |
40 |
0 |
0 |
T16 |
2013 |
0 |
0 |
0 |
T17 |
1092 |
0 |
0 |
0 |
T18 |
681 |
0 |
0 |
0 |
T19 |
2431 |
0 |
0 |
0 |
T20 |
8578 |
16 |
0 |
0 |
T21 |
70762 |
68 |
0 |
0 |
T22 |
0 |
8 |
0 |
0 |
T26 |
0 |
68 |
0 |
0 |
T27 |
0 |
44 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162560083 |
159787787 |
0 |
0 |
T1 |
314704 |
312753 |
0 |
0 |
T2 |
351588 |
347809 |
0 |
0 |
T3 |
423055 |
422250 |
0 |
0 |
T4 |
1252 |
1208 |
0 |
0 |
T5 |
1270 |
1225 |
0 |
0 |
T16 |
2013 |
1820 |
0 |
0 |
T17 |
1092 |
1016 |
0 |
0 |
T18 |
681 |
625 |
0 |
0 |
T19 |
2431 |
2201 |
0 |
0 |
T20 |
8578 |
2412 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc
| Total | Covered | Percent |
Conditions | 12 | 11 | 91.67 |
Logical | 12 | 11 | 91.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Covered | T1,T2,T20 |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T1,T5 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T1,T5 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T1,T5 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T1,T5 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T1,T5 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T1,T5 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162560083 |
159442 |
0 |
0 |
T1 |
314704 |
1453 |
0 |
0 |
T2 |
351588 |
3706 |
0 |
0 |
T3 |
423055 |
868 |
0 |
0 |
T5 |
1270 |
0 |
0 |
0 |
T9 |
0 |
174 |
0 |
0 |
T10 |
0 |
143 |
0 |
0 |
T16 |
2013 |
0 |
0 |
0 |
T17 |
1092 |
0 |
0 |
0 |
T18 |
681 |
0 |
0 |
0 |
T19 |
2431 |
0 |
0 |
0 |
T20 |
8578 |
57 |
0 |
0 |
T21 |
70762 |
409 |
0 |
0 |
T22 |
0 |
26 |
0 |
0 |
T26 |
0 |
568 |
0 |
0 |
T27 |
0 |
143 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
188847735 |
186460301 |
0 |
0 |
T1 |
197953 |
196704 |
0 |
0 |
T2 |
172346 |
170456 |
0 |
0 |
T3 |
423055 |
422250 |
0 |
0 |
T4 |
2505 |
2417 |
0 |
0 |
T5 |
2440 |
2352 |
0 |
0 |
T16 |
986 |
891 |
0 |
0 |
T17 |
1069 |
995 |
0 |
0 |
T18 |
1310 |
1202 |
0 |
0 |
T19 |
1216 |
1101 |
0 |
0 |
T20 |
17158 |
4817 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162560083 |
29669 |
0 |
0 |
T1 |
314704 |
214 |
0 |
0 |
T2 |
351588 |
466 |
0 |
0 |
T3 |
423055 |
144 |
0 |
0 |
T5 |
1270 |
0 |
0 |
0 |
T9 |
0 |
22 |
0 |
0 |
T10 |
0 |
40 |
0 |
0 |
T16 |
2013 |
0 |
0 |
0 |
T17 |
1092 |
0 |
0 |
0 |
T18 |
681 |
0 |
0 |
0 |
T19 |
2431 |
0 |
0 |
0 |
T20 |
8578 |
16 |
0 |
0 |
T21 |
70762 |
57 |
0 |
0 |
T22 |
0 |
8 |
0 |
0 |
T26 |
0 |
65 |
0 |
0 |
T27 |
0 |
35 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
162560083 |
159787787 |
0 |
0 |
T1 |
314704 |
312753 |
0 |
0 |
T2 |
351588 |
347809 |
0 |
0 |
T3 |
423055 |
422250 |
0 |
0 |
T4 |
1252 |
1208 |
0 |
0 |
T5 |
1270 |
1225 |
0 |
0 |
T16 |
2013 |
1820 |
0 |
0 |
T17 |
1092 |
1016 |
0 |
0 |
T18 |
681 |
625 |
0 |
0 |
T19 |
2431 |
2201 |
0 |
0 |
T20 |
8578 |
2412 |
0 |
0 |