Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T30
0	1	Covered	T6,T67,T2
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T30,T67
1	0	Covered	T7,T39,T40
1	1	Covered	T5,T6,T7

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	499663806	9265	0	0
GateOpen_A	499663806	15767	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499663806	9265	0	0
T2	0	60	0	0
T3	0	1	0	0
T6	9530	23	0	0
T7	12824	6	0	0
T11	0	160	0	0
T12	0	212	0	0
T15	0	25	0	0
T24	9168	0	0	0
T25	9382	0	0	0
T26	5350	0	0	0
T27	12321	0	0	0
T28	3182	0	0	0
T29	7724	0	0	0
T30	4585	4	0	0
T67	6230	10	0	0
T77	0	26	0	0
T78	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	499663806	15767	0	0
T2	0	76	0	0
T5	9609	4	0	0
T6	9530	23	0	0
T7	12824	10	0	0
T18	0	4	0	0
T21	0	4	0	0
T24	9168	4	0	0
T25	9382	0	0	0
T26	5350	0	0	0
T27	12321	0	0	0
T28	3182	0	0	0
T29	7724	4	0	0
T30	4585	4	0	0
T67	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T30
0	1	Covered	T6,T67,T2
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T30,T67
1	0	Covered	T7,T39,T40
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	54977893	2208	0	0
GateOpen_A	54977893	3833	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54977893	2208	0	0
T2	0	15	0	0
T6	1046	5	0	0
T7	1417	1	0	0
T11	0	41	0	0
T12	0	49	0	0
T15	0	8	0	0
T24	1006	0	0	0
T25	1025	0	0	0
T26	644	0	0	0
T27	1396	0	0	0
T28	350	0	0	0
T29	912	0	0	0
T30	492	1	0	0
T67	688	3	0	0
T77	0	7	0	0
T78	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54977893	3833	0	0
T2	0	19	0	0
T5	1093	1	0	0
T6	1046	5	0	0
T7	1417	2	0	0
T18	0	1	0	0
T21	0	1	0	0
T24	1006	1	0	0
T25	1025	0	0	0
T26	644	0	0	0
T27	1396	0	0	0
T28	350	0	0	0
T29	912	1	0	0
T30	492	1	0	0
T67	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T30
0	1	Covered	T6,T67,T2
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T30,T67
1	0	Covered	T7,T39,T40
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	109956206	2343	0	0
GateOpen_A	109956206	3968	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	109956206	2343	0	0
T2	0	15	0	0
T6	2091	6	0	0
T7	2833	1	0	0
T11	0	38	0	0
T12	0	56	0	0
T15	0	9	0	0
T24	2011	0	0	0
T25	2049	0	0	0
T26	1291	0	0	0
T27	2793	0	0	0
T28	699	0	0	0
T29	1827	0	0	0
T30	983	1	0	0
T67	1376	2	0	0
T77	0	7	0	0
T78	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	109956206	3968	0	0
T2	0	19	0	0
T5	2185	1	0	0
T6	2091	6	0	0
T7	2833	2	0	0
T18	0	1	0	0
T21	0	1	0	0
T24	2011	1	0	0
T25	2049	0	0	0
T26	1291	0	0	0
T27	2793	0	0	0
T28	699	0	0	0
T29	1827	1	0	0
T30	983	1	0	0
T67	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T30
0	1	Covered	T6,T67,T2
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T30,T67
1	0	Covered	T7,T39,T40
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	221351331	2339	0	0
GateOpen_A	221351331	3965	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221351331	2339	0	0
T2	0	15	0	0
T3	0	1	0	0
T6	4262	6	0	0
T7	5787	1	0	0
T11	0	39	0	0
T12	0	51	0	0
T24	4100	0	0	0
T25	4205	0	0	0
T26	2277	0	0	0
T27	5421	0	0	0
T28	1422	0	0	0
T29	3324	0	0	0
T30	2073	1	0	0
T67	2777	2	0	0
T77	0	6	0	0
T78	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221351331	3965	0	0
T2	0	19	0	0
T5	4221	1	0	0
T6	4262	6	0	0
T7	5787	2	0	0
T18	0	1	0	0
T21	0	1	0	0
T24	4100	1	0	0
T25	4205	0	0	0
T26	2277	0	0	0
T27	5421	0	0	0
T28	1422	0	0	0
T29	3324	1	0	0
T30	2073	1	0	0
T67	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T30
0	1	Covered	T6,T67,T2
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T30,T67
1	0	Covered	T7,T39,T40
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	113378376	2375	0	0
GateOpen_A	113378376	4001	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113378376	2375	0	0
T2	0	15	0	0
T6	2131	6	0	0
T7	2787	3	0	0
T11	0	42	0	0
T12	0	56	0	0
T15	0	8	0	0
T24	2051	0	0	0
T25	2103	0	0	0
T26	1138	0	0	0
T27	2711	0	0	0
T28	711	0	0	0
T29	1661	0	0	0
T30	1037	1	0	0
T67	1389	3	0	0
T77	0	6	0	0
T78	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113378376	4001	0	0
T2	0	19	0	0
T5	2110	1	0	0
T6	2131	6	0	0
T7	2787	4	0	0
T18	0	1	0	0
T21	0	1	0	0
T24	2051	1	0	0
T25	2103	0	0	0
T26	1138	0	0	0
T27	2711	0	0	0
T28	711	0	0	0
T29	1661	1	0	0
T30	1037	1	0	0
T67	0	3	0	0