Line Coverage for Module :
clkmgr
| Line No. | Total | Covered | Percent |
TOTAL | | 34 | 34 | 100.00 |
CONT_ASSIGN | 260 | 1 | 1 | 100.00 |
CONT_ASSIGN | 266 | 1 | 1 | 100.00 |
CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
CONT_ASSIGN | 309 | 1 | 1 | 100.00 |
CONT_ASSIGN | 310 | 1 | 1 | 100.00 |
CONT_ASSIGN | 408 | 1 | 1 | 100.00 |
CONT_ASSIGN | 413 | 1 | 1 | 100.00 |
CONT_ASSIGN | 414 | 1 | 1 | 100.00 |
CONT_ASSIGN | 415 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 437 | 1 | 1 | 100.00 |
CONT_ASSIGN | 462 | 1 | 1 | 100.00 |
CONT_ASSIGN | 474 | 1 | 1 | 100.00 |
CONT_ASSIGN | 486 | 1 | 1 | 100.00 |
CONT_ASSIGN | 511 | 1 | 1 | 100.00 |
ALWAYS | 552 | 5 | 5 | 100.00 |
CONT_ASSIGN | 699 | 1 | 1 | 100.00 |
CONT_ASSIGN | 710 | 1 | 1 | 100.00 |
CONT_ASSIGN | 721 | 1 | 1 | 100.00 |
CONT_ASSIGN | 732 | 1 | 1 | 100.00 |
CONT_ASSIGN | 743 | 1 | 1 | 100.00 |
CONT_ASSIGN | 754 | 1 | 1 | 100.00 |
CONT_ASSIGN | 765 | 1 | 1 | 100.00 |
CONT_ASSIGN | 776 | 1 | 1 | 100.00 |
CONT_ASSIGN | 819 | 1 | 1 | 100.00 |
CONT_ASSIGN | 861 | 1 | 1 | 100.00 |
CONT_ASSIGN | 903 | 1 | 1 | 100.00 |
CONT_ASSIGN | 945 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1062 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1071 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
260 |
1 |
1 |
266 |
1 |
1 |
279 |
1 |
1 |
309 |
1 |
1 |
310 |
1 |
1 |
408 |
1 |
1 |
413 |
1 |
1 |
414 |
1 |
1 |
415 |
1 |
1 |
418 |
1 |
1 |
437 |
1 |
1 |
462 |
1 |
1 |
474 |
1 |
1 |
486 |
1 |
1 |
511 |
1 |
1 |
552 |
1 |
1 |
553 |
1 |
1 |
555 |
1 |
1 |
556 |
1 |
1 |
557 |
1 |
1 |
|
|
|
MISSING_ELSE |
699 |
1 |
1 |
710 |
1 |
1 |
721 |
1 |
1 |
732 |
1 |
1 |
743 |
1 |
1 |
754 |
1 |
1 |
765 |
1 |
1 |
776 |
1 |
1 |
819 |
1 |
1 |
861 |
1 |
1 |
903 |
1 |
1 |
945 |
1 |
1 |
1062 |
1 |
1 |
1071 |
1 |
1 |
Cond Coverage for Module :
clkmgr
| Total | Covered | Percent |
Conditions | 148 | 138 | 93.24 |
Logical | 148 | 138 | 93.24 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 37
EXPRESSION (scanmode_i == MuBi4True)
------------1------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T6,T25,T26 |
LINE 46
EXPRESSION (scanmode_i == MuBi4True)
------------1------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T6,T25,T26 |
LINE 55
EXPRESSION (scanmode_i == MuBi4True)
------------1------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T6,T25,T26 |
LINE 64
EXPRESSION (scanmode_i == MuBi4True)
------------1------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T6,T25,T26 |
LINE 74
EXPRESSION (idle_i[HintMainAes] == MuBi4True)
-----------------1----------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 74
EXPRESSION (scanmode_i == MuBi4True)
------------1------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T6,T25,T26 |
LINE 84
EXPRESSION (idle_i[HintMainHmac] == MuBi4True)
-----------------1-----------------
-1- | Status | Tests |
0 | Covered | T6,T7,T24 |
1 | Covered | T5,T6,T7 |
LINE 84
EXPRESSION (scanmode_i == MuBi4True)
------------1------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T6,T25,T26 |
LINE 94
EXPRESSION (idle_i[HintMainKmac] == MuBi4True)
-----------------1-----------------
-1- | Status | Tests |
0 | Covered | T6,T7,T24 |
1 | Covered | T5,T6,T7 |
LINE 94
EXPRESSION (scanmode_i == MuBi4True)
------------1------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T6,T25,T26 |
LINE 104
EXPRESSION (idle_i[HintMainOtbn] == MuBi4True)
-----------------1-----------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 104
EXPRESSION (scanmode_i == MuBi4True)
------------1------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T6,T25,T26 |
LINE 128
EXPRESSION (div_step_down_req_i == MuBi4True)
-----------------1----------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T26,T27 |
LINE 128
EXPRESSION (scanmode_i == MuBi4True)
------------1------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T6,T25,T26 |
LINE 139
EXPRESSION (div_step_down_req_i == MuBi4True)
-----------------1----------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T26,T27 |
LINE 139
EXPRESSION (scanmode_i == MuBi4True)
------------1------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T6,T25,T26 |
LINE 148
EXPRESSION (cg_en_o.aon_peri == MuBi4True)
---------------1---------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Not Covered | |
LINE 152
EXPRESSION (cg_en_o.aon_powerup == MuBi4True)
-----------------1----------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Not Covered | |
LINE 156
EXPRESSION (cg_en_o.aon_secure == MuBi4True)
----------------1----------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Not Covered | |
LINE 160
EXPRESSION (cg_en_o.aon_timers == MuBi4True)
----------------1----------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Not Covered | |
LINE 164
EXPRESSION (cg_en_o.io_div2_powerup == MuBi4True)
-------------------1------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Not Covered | |
LINE 168
EXPRESSION (cg_en_o.io_div4_powerup == MuBi4True)
-------------------1------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Not Covered | |
LINE 172
EXPRESSION (cg_en_o.io_powerup == MuBi4True)
----------------1----------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Not Covered | |
LINE 176
EXPRESSION (cg_en_o.main_powerup == MuBi4True)
-----------------1-----------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Not Covered | |
LINE 180
EXPRESSION (cg_en_o.usb_powerup == MuBi4True)
-----------------1----------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Not Covered | |
LINE 185
EXPRESSION (cg_en_o.io_div2_infra == MuBi4True)
------------------1-----------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 194
EXPRESSION (cg_en_o.io_div4_infra == MuBi4True)
------------------1-----------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 203
EXPRESSION (cg_en_o.io_div4_secure == MuBi4True)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 212
EXPRESSION (cg_en_o.io_div4_timers == MuBi4True)
------------------1------------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 221
EXPRESSION (cg_en_o.io_infra == MuBi4True)
---------------1---------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 230
EXPRESSION (cg_en_o.main_infra == MuBi4True)
----------------1----------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 239
EXPRESSION (cg_en_o.main_secure == MuBi4True)
-----------------1----------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 248
EXPRESSION (cg_en_o.usb_infra == MuBi4True)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 258
EXPRESSION (cg_en_o.io_div4_peri == MuBi4True)
-----------------1-----------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 260
SUB-EXPRESSION (reg2hw.alert_test.fatal_fault.q & reg2hw.alert_test.fatal_fault.qe)
---------------1--------------- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T24,T25,T36 |
1 | 0 | Covered | T5,T6,T24 |
1 | 1 | Covered | T24,T25,T36 |
LINE 260
SUB-EXPRESSION (reg2hw.alert_test.recov_fault.q & reg2hw.alert_test.recov_fault.qe)
---------------1--------------- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T24,T25,T36 |
1 | 0 | Covered | T5,T6,T24 |
1 | 1 | Covered | T24,T25,T36 |
LINE 266
EXPRESSION
Number Term
1 hw2reg.recov_err_code.io_measure_err.de |
2 hw2reg.recov_err_code.io_timeout_err.de |
3 hw2reg.recov_err_code.io_div2_measure_err.de |
4 hw2reg.recov_err_code.io_div2_timeout_err.de |
5 hw2reg.recov_err_code.io_div4_measure_err.de |
6 hw2reg.recov_err_code.io_div4_timeout_err.de |
7 hw2reg.recov_err_code.main_measure_err.de |
8 hw2reg.recov_err_code.main_timeout_err.de |
9 hw2reg.recov_err_code.usb_measure_err.de |
10 hw2reg.recov_err_code.usb_timeout_err.de |
11 hw2reg.recov_err_code.shadow_update_err.de)
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | Status | Tests |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T5,T6,T7 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | Not Covered | |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | Covered | T2,T11,T12 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | Covered | T2,T3,T11 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | Covered | T11,T12,T33 |
0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | Covered | T2,T11,T12 |
0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T1,T2,T11 |
0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T15,T37,T38 |
0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T15,T37,T38 |
1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T2,T3,T11 |
LINE 267
EXPRESSION (cg_en_o.io_div2_peri == MuBi4True)
-----------------1-----------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 276
EXPRESSION (cg_en_o.io_peri == MuBi4True)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 285
EXPRESSION (cg_en_o.usb_peri == MuBi4True)
---------------1---------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 295
EXPRESSION (clkmgr.u_clk_main_aes_trans.sw_hint_synced || ((!clkmgr.u_clk_main_aes_trans.idle_valid)))
---------------------1-------------------- ---------------------2---------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T30,T2,T20 |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T5,T6,T7 |
LINE 295
EXPRESSION (cg_en_o.main_aes == MuBi4True)
---------------1---------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 304
EXPRESSION (clkmgr.u_clk_main_hmac_trans.sw_hint_synced || ((!clkmgr.u_clk_main_hmac_trans.idle_valid)))
---------------------1--------------------- ----------------------2---------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T30,T2,T20 |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T5,T6,T7 |
LINE 304
EXPRESSION (cg_en_o.main_hmac == MuBi4True)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 313
EXPRESSION (clkmgr.u_clk_main_kmac_trans.sw_hint_synced || ((!clkmgr.u_clk_main_kmac_trans.idle_valid)))
---------------------1--------------------- ----------------------2---------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T30,T2,T20 |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T5,T6,T7 |
LINE 313
EXPRESSION (cg_en_o.main_kmac == MuBi4True)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 322
EXPRESSION (clkmgr.u_clk_main_otbn_trans.sw_hint_synced || ((!clkmgr.u_clk_main_otbn_trans.idle_valid)))
---------------------1--------------------- ----------------------2---------------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T30,T2,T20 |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T5,T6,T7 |
LINE 322
EXPRESSION (cg_en_o.main_otbn == MuBi4True)
----------------1---------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 704
EXPRESSION (clk_io_div4_en ? MuBi4False : MuBi4True)
-------1------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 715
EXPRESSION (clk_main_en ? MuBi4False : MuBi4True)
-----1-----
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 726
EXPRESSION (clk_usb_en ? MuBi4False : MuBi4True)
-----1----
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 737
EXPRESSION (clk_io_en ? MuBi4False : MuBi4True)
----1----
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 748
EXPRESSION (clk_io_div2_en ? MuBi4False : MuBi4True)
-------1------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 759
EXPRESSION (clk_io_div4_en ? MuBi4False : MuBi4True)
-------1------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 770
EXPRESSION (clk_main_en ? MuBi4False : MuBi4True)
-----1-----
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 781
EXPRESSION (clk_io_div4_en ? MuBi4False : MuBi4True)
-------1------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 819
EXPRESSION (clk_io_div4_peri_sw_en & clk_io_div4_en)
-----------1---------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T7,T39,T40 |
1 | 1 | Covered | T5,T6,T7 |
LINE 832
EXPRESSION (clk_io_div4_peri_combined_en ? MuBi4False : MuBi4True)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 861
EXPRESSION (clk_io_div2_peri_sw_en & clk_io_div2_en)
-----------1---------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T7,T39,T40 |
1 | 1 | Covered | T5,T6,T7 |
LINE 874
EXPRESSION (clk_io_div2_peri_combined_en ? MuBi4False : MuBi4True)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 903
EXPRESSION (clk_io_peri_sw_en & clk_io_en)
--------1-------- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T7,T39,T40 |
1 | 1 | Covered | T5,T6,T7 |
LINE 916
EXPRESSION (clk_io_peri_combined_en ? MuBi4False : MuBi4True)
-----------1-----------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
LINE 945
EXPRESSION (clk_usb_peri_sw_en & clk_usb_en)
---------1-------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T7,T39,T40 |
1 | 1 | Covered | T5,T6,T7 |
LINE 958
EXPRESSION (clk_usb_peri_combined_en ? MuBi4False : MuBi4True)
------------1-----------
-1- | Status | Tests |
0 | Covered | T5,T6,T7 |
1 | Covered | T5,T6,T7 |
Toggle Coverage for Module :
clkmgr
| Total | Covered | Percent |
Totals |
106 |
106 |
100.00 |
Total Bits |
660 |
660 |
100.00 |
Total Bits 0->1 |
330 |
330 |
100.00 |
Total Bits 1->0 |
330 |
330 |
100.00 |
| | | |
Ports |
106 |
106 |
100.00 |
Port Bits |
660 |
660 |
100.00 |
Port Bits 0->1 |
330 |
330 |
100.00 |
Port Bits 1->0 |
330 |
330 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
INPUT |
rst_ni |
Yes |
Yes |
T2,T4,T3 |
Yes |
T5,T6,T7 |
INPUT |
rst_shadowed_ni |
Yes |
Yes |
T2,T4,T3 |
Yes |
T5,T6,T7 |
INPUT |
clk_main_i |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
INPUT |
rst_main_ni |
Yes |
Yes |
T2,T4,T3 |
Yes |
T5,T6,T7 |
INPUT |
clk_io_i |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
INPUT |
rst_io_ni |
Yes |
Yes |
T2,T4,T3 |
Yes |
T5,T6,T7 |
INPUT |
clk_usb_i |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
INPUT |
rst_usb_ni |
Yes |
Yes |
T2,T4,T3 |
Yes |
T5,T6,T7 |
INPUT |
clk_aon_i |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
INPUT |
rst_aon_ni |
Yes |
Yes |
T2,T4,T3 |
Yes |
T5,T6,T7 |
INPUT |
rst_io_div2_ni |
Yes |
Yes |
T2,T4,T3 |
Yes |
T5,T6,T7 |
INPUT |
rst_io_div4_ni |
Yes |
Yes |
T2,T4,T3 |
Yes |
T5,T6,T7 |
INPUT |
rst_root_ni |
Yes |
Yes |
T2,T4,T3 |
Yes |
T5,T6,T7 |
INPUT |
rst_root_main_ni |
Yes |
Yes |
T2,T4,T3 |
Yes |
T5,T6,T7 |
INPUT |
rst_root_io_ni |
Yes |
Yes |
T2,T4,T3 |
Yes |
T5,T6,T7 |
INPUT |
rst_root_io_div2_ni |
Yes |
Yes |
T2,T4,T3 |
Yes |
T5,T6,T7 |
INPUT |
rst_root_io_div4_ni |
Yes |
Yes |
T2,T4,T3 |
Yes |
T5,T6,T7 |
INPUT |
rst_root_usb_ni |
Yes |
Yes |
T2,T4,T3 |
Yes |
T5,T6,T7 |
INPUT |
tl_i.d_ready |
Yes |
Yes |
T5,T24,T25 |
Yes |
T5,T6,T7 |
INPUT |
tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T5,T6,T24 |
Yes |
T5,T6,T24 |
INPUT |
tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T5,T6,T24 |
Yes |
T5,T6,T24 |
INPUT |
tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T25,T27,T30 |
Yes |
T25,T27,T30 |
INPUT |
tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_data[31:0] |
Yes |
Yes |
T5,T6,T24 |
Yes |
T6,T24,T25 |
INPUT |
tl_i.a_mask[3:0] |
Yes |
Yes |
T5,T25,T26 |
Yes |
T5,T25,T26 |
INPUT |
tl_i.a_address[31:0] |
Yes |
Yes |
T5,T25,T26 |
Yes |
T5,T25,T26 |
INPUT |
tl_i.a_source[7:0] |
Yes |
Yes |
T6,T24,T25 |
Yes |
T6,T24,T25 |
INPUT |
tl_i.a_size[1:0] |
Yes |
Yes |
T5,T6,T24 |
Yes |
T5,T6,T24 |
INPUT |
tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_opcode[2:0] |
Yes |
Yes |
T6,T24,T25 |
Yes |
T6,T24,T25 |
INPUT |
tl_i.a_valid |
Yes |
Yes |
T5,T6,T24 |
Yes |
T5,T6,T24 |
INPUT |
tl_o.a_ready |
Yes |
Yes |
T5,T6,T24 |
Yes |
T5,T6,T24 |
OUTPUT |
tl_o.d_error |
Yes |
Yes |
T11,T12,T41 |
Yes |
T11,T12,T41 |
OUTPUT |
tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T26,T27,T28 |
Yes |
T26,T27,T28 |
OUTPUT |
tl_o.d_user.rsp_intg[5:0] |
Yes |
Yes |
*T5,*T6,*T24 |
Yes |
T5,T6,T24 |
OUTPUT |
tl_o.d_user.rsp_intg[6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_data[31:0] |
Yes |
Yes |
T5,T26,T27 |
Yes |
T5,T6,T24 |
OUTPUT |
tl_o.d_sink |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_source[7:0] |
Yes |
Yes |
T6,T24,T25 |
Yes |
T5,T6,T24 |
OUTPUT |
tl_o.d_size[1:0] |
Yes |
Yes |
T5,T6,T24 |
Yes |
T5,T6,T24 |
OUTPUT |
tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_opcode[0] |
Yes |
Yes |
*T5,*T26,*T27 |
Yes |
T5,T26,T27 |
OUTPUT |
tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_valid |
Yes |
Yes |
T5,T6,T24 |
Yes |
T5,T6,T24 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T24,T25,T1 |
Yes |
T24,T25,T1 |
INPUT |
alert_rx_i[0].ping_n |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_rx_i[0].ping_p |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_rx_i[1].ack_n |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
INPUT |
alert_rx_i[1].ack_p |
Yes |
Yes |
T24,T25,T36 |
Yes |
T24,T25,T36 |
INPUT |
alert_rx_i[1].ping_n |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_rx_i[1].ping_p |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T24,T25,T1 |
Yes |
T24,T25,T1 |
OUTPUT |
alert_tx_o[1].alert_n |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
OUTPUT |
alert_tx_o[1].alert_p |
Yes |
Yes |
T24,T25,T36 |
Yes |
T24,T25,T36 |
OUTPUT |
pwr_i.usb_ip_clk_en |
Yes |
Yes |
T7,T39,T40 |
Yes |
T7,T39,T40 |
INPUT |
pwr_i.io_ip_clk_en |
Yes |
Yes |
T7,T39,T40 |
Yes |
T7,T39,T40 |
INPUT |
pwr_i.main_ip_clk_en |
Yes |
Yes |
T7,T39,T40 |
Yes |
T7,T39,T40 |
INPUT |
pwr_o.usb_status |
Yes |
Yes |
T7,T2,T4 |
Yes |
T5,T6,T7 |
OUTPUT |
pwr_o.io_status |
Yes |
Yes |
T7,T2,T4 |
Yes |
T5,T6,T7 |
OUTPUT |
pwr_o.main_status |
Yes |
Yes |
T7,T2,T4 |
Yes |
T5,T6,T7 |
OUTPUT |
scanmode_i[3:0] |
Yes |
Yes |
T6,T26,T27 |
Yes |
T6,T25,T26 |
INPUT |
lc_hw_debug_en_i[3:0] |
Yes |
Yes |
T26,T27,T28 |
Yes |
T5,T26,T27 |
INPUT |
lc_clk_byp_req_i[3:0] |
Yes |
Yes |
T26,T27,T28 |
Yes |
T26,T27,T28 |
INPUT |
lc_clk_byp_ack_o[3:0] |
Yes |
Yes |
T26,T27,T29 |
Yes |
T26,T27,T29 |
OUTPUT |
io_clk_byp_req_o[3:0] |
Yes |
Yes |
T26,T27,T28 |
Yes |
T26,T27,T28 |
OUTPUT |
io_clk_byp_ack_i[3:0] |
Yes |
Yes |
T26,T27,T28 |
Yes |
T26,T27,T28 |
INPUT |
all_clk_byp_req_o[3:0] |
Yes |
Yes |
T5,T26,T27 |
Yes |
T26,T27,T28 |
OUTPUT |
all_clk_byp_ack_i[3:0] |
Yes |
Yes |
T5,T26,T27 |
Yes |
T5,T26,T27 |
INPUT |
hi_speed_sel_o[3:0] |
Yes |
Yes |
T5,T26,T27 |
Yes |
T5,T6,T7 |
OUTPUT |
calib_rdy_i[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
jitter_en_o[3:0] |
Yes |
Yes |
T30,T2,T3 |
Yes |
T30,T2,T3 |
OUTPUT |
div_step_down_req_i[3:0] |
Yes |
Yes |
T5,T26,T27 |
Yes |
T5,T26,T27 |
INPUT |
cg_en_o.usb_peri[3:0] |
Yes |
Yes |
T6,T7,T30 |
Yes |
T5,T6,T7 |
OUTPUT |
cg_en_o.io_peri[3:0] |
Yes |
Yes |
T6,T7,T30 |
Yes |
T5,T6,T7 |
OUTPUT |
cg_en_o.io_div2_peri[3:0] |
Yes |
Yes |
T6,T7,T30 |
Yes |
T5,T6,T7 |
OUTPUT |
cg_en_o.io_div4_peri[3:0] |
Yes |
Yes |
T6,T7,T30 |
Yes |
T5,T6,T7 |
OUTPUT |
cg_en_o.io_div4_timers[3:0] |
Yes |
Yes |
T7,T2,T4 |
Yes |
T5,T6,T7 |
OUTPUT |
cg_en_o.main_secure[3:0] |
Yes |
Yes |
T7,T2,T4 |
Yes |
T5,T6,T7 |
OUTPUT |
cg_en_o.io_div4_secure[3:0] |
Yes |
Yes |
T7,T2,T4 |
Yes |
T5,T6,T7 |
OUTPUT |
cg_en_o.io_div2_infra[3:0] |
Yes |
Yes |
T7,T2,T4 |
Yes |
T5,T6,T7 |
OUTPUT |
cg_en_o.io_infra[3:0] |
Yes |
Yes |
T7,T2,T4 |
Yes |
T5,T6,T7 |
OUTPUT |
cg_en_o.usb_infra[3:0] |
Yes |
Yes |
T7,T2,T4 |
Yes |
T5,T6,T7 |
OUTPUT |
cg_en_o.main_infra[3:0] |
Yes |
Yes |
T7,T2,T4 |
Yes |
T5,T6,T7 |
OUTPUT |
cg_en_o.io_div4_infra[3:0] |
Yes |
Yes |
T7,T2,T4 |
Yes |
T5,T6,T7 |
OUTPUT |
cg_en_o.main_otbn[3:0] |
Yes |
Yes |
T7,T30,T2 |
Yes |
T5,T6,T7 |
OUTPUT |
cg_en_o.main_kmac[3:0] |
Yes |
Yes |
T7,T30,T2 |
Yes |
T5,T6,T7 |
OUTPUT |
cg_en_o.main_hmac[3:0] |
Yes |
Yes |
T7,T30,T2 |
Yes |
T5,T6,T7 |
OUTPUT |
cg_en_o.main_aes[3:0] |
Yes |
Yes |
T7,T30,T2 |
Yes |
T5,T6,T7 |
OUTPUT |
cg_en_o.aon_timers[3:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
cg_en_o.aon_peri[3:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
cg_en_o.aon_secure[3:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
cg_en_o.io_div2_powerup[3:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
cg_en_o.usb_powerup[3:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
cg_en_o.io_powerup[3:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
cg_en_o.main_powerup[3:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
cg_en_o.aon_powerup[3:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
cg_en_o.io_div4_powerup[3:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
clocks_o.clk_usb_peri |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
OUTPUT |
clocks_o.clk_io_peri |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
OUTPUT |
clocks_o.clk_io_div2_peri |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
OUTPUT |
clocks_o.clk_io_div4_peri |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
OUTPUT |
clocks_o.clk_io_div4_timers |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
OUTPUT |
clocks_o.clk_main_secure |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
OUTPUT |
clocks_o.clk_io_div4_secure |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
OUTPUT |
clocks_o.clk_io_div2_infra |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
OUTPUT |
clocks_o.clk_io_infra |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
OUTPUT |
clocks_o.clk_usb_infra |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
OUTPUT |
clocks_o.clk_main_infra |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
OUTPUT |
clocks_o.clk_io_div4_infra |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
OUTPUT |
clocks_o.clk_main_otbn |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
OUTPUT |
clocks_o.clk_main_kmac |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
OUTPUT |
clocks_o.clk_main_hmac |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
OUTPUT |
clocks_o.clk_main_aes |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
OUTPUT |
clocks_o.clk_aon_timers |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
OUTPUT |
clocks_o.clk_aon_peri |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
OUTPUT |
clocks_o.clk_aon_secure |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
OUTPUT |
clocks_o.clk_io_div2_powerup |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
OUTPUT |
clocks_o.clk_usb_powerup |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
OUTPUT |
clocks_o.clk_io_powerup |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
OUTPUT |
clocks_o.clk_main_powerup |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
OUTPUT |
clocks_o.clk_aon_powerup |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
OUTPUT |
clocks_o.clk_io_div4_powerup |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
OUTPUT |
*Tests covering at least one bit in the range
Branch Coverage for Module :
clkmgr
| Line No. | Total | Covered | Percent |
Branches |
|
26 |
26 |
100.00 |
TERNARY |
704 |
2 |
2 |
100.00 |
TERNARY |
715 |
2 |
2 |
100.00 |
TERNARY |
726 |
2 |
2 |
100.00 |
TERNARY |
737 |
2 |
2 |
100.00 |
TERNARY |
748 |
2 |
2 |
100.00 |
TERNARY |
759 |
2 |
2 |
100.00 |
TERNARY |
770 |
2 |
2 |
100.00 |
TERNARY |
781 |
2 |
2 |
100.00 |
TERNARY |
832 |
2 |
2 |
100.00 |
TERNARY |
874 |
2 |
2 |
100.00 |
TERNARY |
916 |
2 |
2 |
100.00 |
TERNARY |
958 |
2 |
2 |
100.00 |
IF |
555 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 704 (clk_io_div4_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 715 (clk_main_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 726 (clk_usb_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 737 (clk_io_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 748 (clk_io_div2_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 759 (clk_io_div4_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 770 (clk_main_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 781 (clk_io_div4_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 832 (clk_io_div4_peri_combined_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 874 (clk_io_div2_peri_combined_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 916 (clk_io_peri_combined_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 958 (clk_usb_peri_combined_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 555 if (prim_mubi_pkg::mubi4_test_false_strict(calib_rdy[BaseIdx]))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Module :
clkmgr
Assertion Details
AlertsKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
72901641 |
70846916 |
0 |
0 |
T5 |
1098 |
1053 |
0 |
0 |
T6 |
1153 |
1095 |
0 |
0 |
T7 |
1037 |
994 |
0 |
0 |
T24 |
1153 |
1112 |
0 |
0 |
T25 |
1050 |
993 |
0 |
0 |
T26 |
2371 |
2288 |
0 |
0 |
T27 |
1354 |
1314 |
0 |
0 |
T28 |
1437 |
1356 |
0 |
0 |
T29 |
2423 |
2255 |
0 |
0 |
T30 |
2138 |
1985 |
0 |
0 |
AllClkBypReqKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
72901641 |
70846916 |
0 |
0 |
T5 |
1098 |
1053 |
0 |
0 |
T6 |
1153 |
1095 |
0 |
0 |
T7 |
1037 |
994 |
0 |
0 |
T24 |
1153 |
1112 |
0 |
0 |
T25 |
1050 |
993 |
0 |
0 |
T26 |
2371 |
2288 |
0 |
0 |
T27 |
1354 |
1314 |
0 |
0 |
T28 |
1437 |
1356 |
0 |
0 |
T29 |
2423 |
2255 |
0 |
0 |
T30 |
2138 |
1985 |
0 |
0 |
CgEnKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
72901641 |
70846916 |
0 |
0 |
T5 |
1098 |
1053 |
0 |
0 |
T6 |
1153 |
1095 |
0 |
0 |
T7 |
1037 |
994 |
0 |
0 |
T24 |
1153 |
1112 |
0 |
0 |
T25 |
1050 |
993 |
0 |
0 |
T26 |
2371 |
2288 |
0 |
0 |
T27 |
1354 |
1314 |
0 |
0 |
T28 |
1437 |
1356 |
0 |
0 |
T29 |
2423 |
2255 |
0 |
0 |
T30 |
2138 |
1985 |
0 |
0 |
ClocksKownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
72901641 |
70846916 |
0 |
0 |
T5 |
1098 |
1053 |
0 |
0 |
T6 |
1153 |
1095 |
0 |
0 |
T7 |
1037 |
994 |
0 |
0 |
T24 |
1153 |
1112 |
0 |
0 |
T25 |
1050 |
993 |
0 |
0 |
T26 |
2371 |
2288 |
0 |
0 |
T27 |
1354 |
1314 |
0 |
0 |
T28 |
1437 |
1356 |
0 |
0 |
T29 |
2423 |
2255 |
0 |
0 |
T30 |
2138 |
1985 |
0 |
0 |
FpvSecCmClkMainAesCountCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
72901641 |
77 |
0 |
0 |
T42 |
14743 |
8 |
0 |
0 |
T43 |
0 |
11 |
0 |
0 |
T44 |
0 |
20 |
0 |
0 |
T45 |
0 |
18 |
0 |
0 |
T46 |
0 |
20 |
0 |
0 |
T47 |
13212 |
0 |
0 |
0 |
T48 |
1793 |
0 |
0 |
0 |
T49 |
76328 |
0 |
0 |
0 |
T50 |
1291 |
0 |
0 |
0 |
T51 |
1442 |
0 |
0 |
0 |
T52 |
1393 |
0 |
0 |
0 |
T53 |
2041 |
0 |
0 |
0 |
T54 |
1437 |
0 |
0 |
0 |
T55 |
2113 |
0 |
0 |
0 |
FpvSecCmClkMainHmacCountCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
72901641 |
82 |
0 |
0 |
T42 |
14743 |
9 |
0 |
0 |
T43 |
0 |
14 |
0 |
0 |
T44 |
0 |
19 |
0 |
0 |
T45 |
0 |
20 |
0 |
0 |
T46 |
0 |
20 |
0 |
0 |
T47 |
13212 |
0 |
0 |
0 |
T48 |
1793 |
0 |
0 |
0 |
T49 |
76328 |
0 |
0 |
0 |
T50 |
1291 |
0 |
0 |
0 |
T51 |
1442 |
0 |
0 |
0 |
T52 |
1393 |
0 |
0 |
0 |
T53 |
2041 |
0 |
0 |
0 |
T54 |
1437 |
0 |
0 |
0 |
T55 |
2113 |
0 |
0 |
0 |
FpvSecCmClkMainKmacCountCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
72901641 |
79 |
0 |
0 |
T42 |
14743 |
9 |
0 |
0 |
T43 |
0 |
14 |
0 |
0 |
T44 |
0 |
18 |
0 |
0 |
T45 |
0 |
19 |
0 |
0 |
T46 |
0 |
19 |
0 |
0 |
T47 |
13212 |
0 |
0 |
0 |
T48 |
1793 |
0 |
0 |
0 |
T49 |
76328 |
0 |
0 |
0 |
T50 |
1291 |
0 |
0 |
0 |
T51 |
1442 |
0 |
0 |
0 |
T52 |
1393 |
0 |
0 |
0 |
T53 |
2041 |
0 |
0 |
0 |
T54 |
1437 |
0 |
0 |
0 |
T55 |
2113 |
0 |
0 |
0 |
FpvSecCmClkMainOtbnCountCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
72901641 |
82 |
0 |
0 |
T42 |
14743 |
9 |
0 |
0 |
T43 |
0 |
16 |
0 |
0 |
T44 |
0 |
18 |
0 |
0 |
T45 |
0 |
19 |
0 |
0 |
T46 |
0 |
20 |
0 |
0 |
T47 |
13212 |
0 |
0 |
0 |
T48 |
1793 |
0 |
0 |
0 |
T49 |
76328 |
0 |
0 |
0 |
T50 |
1291 |
0 |
0 |
0 |
T51 |
1442 |
0 |
0 |
0 |
T52 |
1393 |
0 |
0 |
0 |
T53 |
2041 |
0 |
0 |
0 |
T54 |
1437 |
0 |
0 |
0 |
T55 |
2113 |
0 |
0 |
0 |
FpvSecCmRegWeOnehotCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
72901641 |
90 |
0 |
0 |
T42 |
14743 |
10 |
0 |
0 |
T43 |
0 |
20 |
0 |
0 |
T44 |
0 |
20 |
0 |
0 |
T45 |
0 |
20 |
0 |
0 |
T46 |
0 |
20 |
0 |
0 |
T47 |
13212 |
0 |
0 |
0 |
T48 |
1793 |
0 |
0 |
0 |
T49 |
76328 |
0 |
0 |
0 |
T50 |
1291 |
0 |
0 |
0 |
T51 |
1442 |
0 |
0 |
0 |
T52 |
1393 |
0 |
0 |
0 |
T53 |
2041 |
0 |
0 |
0 |
T54 |
1437 |
0 |
0 |
0 |
T55 |
2113 |
0 |
0 |
0 |
IoClkBypReqKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
72901641 |
70846916 |
0 |
0 |
T5 |
1098 |
1053 |
0 |
0 |
T6 |
1153 |
1095 |
0 |
0 |
T7 |
1037 |
994 |
0 |
0 |
T24 |
1153 |
1112 |
0 |
0 |
T25 |
1050 |
993 |
0 |
0 |
T26 |
2371 |
2288 |
0 |
0 |
T27 |
1354 |
1314 |
0 |
0 |
T28 |
1437 |
1356 |
0 |
0 |
T29 |
2423 |
2255 |
0 |
0 |
T30 |
2138 |
1985 |
0 |
0 |
JitterEnableKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
72901641 |
70846916 |
0 |
0 |
T5 |
1098 |
1053 |
0 |
0 |
T6 |
1153 |
1095 |
0 |
0 |
T7 |
1037 |
994 |
0 |
0 |
T24 |
1153 |
1112 |
0 |
0 |
T25 |
1050 |
993 |
0 |
0 |
T26 |
2371 |
2288 |
0 |
0 |
T27 |
1354 |
1314 |
0 |
0 |
T28 |
1437 |
1356 |
0 |
0 |
T29 |
2423 |
2255 |
0 |
0 |
T30 |
2138 |
1985 |
0 |
0 |
LcCtrlClkBypAckKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
72901641 |
70846916 |
0 |
0 |
T5 |
1098 |
1053 |
0 |
0 |
T6 |
1153 |
1095 |
0 |
0 |
T7 |
1037 |
994 |
0 |
0 |
T24 |
1153 |
1112 |
0 |
0 |
T25 |
1050 |
993 |
0 |
0 |
T26 |
2371 |
2288 |
0 |
0 |
T27 |
1354 |
1314 |
0 |
0 |
T28 |
1437 |
1356 |
0 |
0 |
T29 |
2423 |
2255 |
0 |
0 |
T30 |
2138 |
1985 |
0 |
0 |
PwrMgrKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
72901641 |
70846916 |
0 |
0 |
T5 |
1098 |
1053 |
0 |
0 |
T6 |
1153 |
1095 |
0 |
0 |
T7 |
1037 |
994 |
0 |
0 |
T24 |
1153 |
1112 |
0 |
0 |
T25 |
1050 |
993 |
0 |
0 |
T26 |
2371 |
2288 |
0 |
0 |
T27 |
1354 |
1314 |
0 |
0 |
T28 |
1437 |
1356 |
0 |
0 |
T29 |
2423 |
2255 |
0 |
0 |
T30 |
2138 |
1985 |
0 |
0 |
TlAReadyKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
72901641 |
70846916 |
0 |
0 |
T5 |
1098 |
1053 |
0 |
0 |
T6 |
1153 |
1095 |
0 |
0 |
T7 |
1037 |
994 |
0 |
0 |
T24 |
1153 |
1112 |
0 |
0 |
T25 |
1050 |
993 |
0 |
0 |
T26 |
2371 |
2288 |
0 |
0 |
T27 |
1354 |
1314 |
0 |
0 |
T28 |
1437 |
1356 |
0 |
0 |
T29 |
2423 |
2255 |
0 |
0 |
T30 |
2138 |
1985 |
0 |
0 |
TlDValidKnownO_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
72901641 |
70846916 |
0 |
0 |
T5 |
1098 |
1053 |
0 |
0 |
T6 |
1153 |
1095 |
0 |
0 |
T7 |
1037 |
994 |
0 |
0 |
T24 |
1153 |
1112 |
0 |
0 |
T25 |
1050 |
993 |
0 |
0 |
T26 |
2371 |
2288 |
0 |
0 |
T27 |
1354 |
1314 |
0 |
0 |
T28 |
1437 |
1356 |
0 |
0 |
T29 |
2423 |
2255 |
0 |
0 |
T30 |
2138 |
1985 |
0 |
0 |