Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	364508205	38876	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364508205	38876	0	0
T1	147585	139	0	0
T2	1949610	1147	0	0
T3	1466305	570	0	0
T4	37360	0	0	0
T11	0	297	0	0
T12	0	204	0	0
T13	0	98	0	0
T14	0	401	0	0
T15	0	74	0	0
T16	0	94	0	0
T17	0	41	0	0
T18	7680	0	0	0
T19	10290	0	0	0
T20	6875	0	0	0
T21	6215	0	0	0
T22	10850	0	0	0
T23	3365	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	72901641	5850	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72901641	5850	0	0
T1	29517	22	0	0
T2	389922	165	0	0
T3	293261	74	0	0
T4	7472	0	0	0
T11	0	48	0	0
T12	0	35	0	0
T13	0	16	0	0
T14	0	59	0	0
T15	0	11	0	0
T16	0	15	0	0
T17	0	7	0	0
T18	1536	0	0	0
T19	2058	0	0	0
T20	1375	0	0	0
T21	1243	0	0	0
T22	2170	0	0	0
T23	673	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	72901641	5698	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72901641	5698	0	0
T1	29517	22	0	0
T2	389922	163	0	0
T3	293261	73	0	0
T4	7472	0	0	0
T11	0	47	0	0
T12	0	32	0	0
T13	0	15	0	0
T14	0	50	0	0
T15	0	11	0	0
T16	0	14	0	0
T17	0	7	0	0
T18	1536	0	0	0
T19	2058	0	0	0
T20	1375	0	0	0
T21	1243	0	0	0
T22	2170	0	0	0
T23	673	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	72901641	7856	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72901641	7856	0	0
T1	29517	28	0	0
T2	389922	257	0	0
T3	293261	114	0	0
T4	7472	0	0	0
T11	0	59	0	0
T12	0	41	0	0
T13	0	20	0	0
T14	0	78	0	0
T15	0	15	0	0
T16	0	19	0	0
T17	0	8	0	0
T18	1536	0	0	0
T19	2058	0	0	0
T20	1375	0	0	0
T21	1243	0	0	0
T22	2170	0	0	0
T23	673	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	72901641	7822	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72901641	7822	0	0
T1	29517	28	0	0
T2	389922	223	0	0
T3	293261	115	0	0
T4	7472	0	0	0
T11	0	61	0	0
T12	0	40	0	0
T13	0	19	0	0
T14	0	83	0	0
T15	0	15	0	0
T16	0	20	0	0
T17	0	9	0	0
T18	1536	0	0	0
T19	2058	0	0	0
T20	1375	0	0	0
T21	1243	0	0	0
T22	2170	0	0	0
T23	673	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	72901641	11650	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72901641	11650	0	0
T1	29517	39	0	0
T2	389922	339	0	0
T3	293261	194	0	0
T4	7472	0	0	0
T11	0	82	0	0
T12	0	56	0	0
T13	0	28	0	0
T14	0	131	0	0
T15	0	22	0	0
T16	0	26	0	0
T17	0	10	0	0
T18	1536	0	0	0
T19	2058	0	0	0
T20	1375	0	0	0
T21	1243	0	0	0
T22	2170	0	0	0
T23	673	0	0	0