Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T2,T4,T3

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	72901641	70764862	0	0
AllClkBypReqTrue_A	72901641	79865	0	0
IoClkBypReqFalse_A	72901641	70709310	0	2322
IoClkBypReqTrue_A	72901641	131039	0	0
LcClkBypAckFalse_A	72901641	70770704	0	0
LcClkBypAckTrue_A	72901641	74023	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72901641	70764862	0	0
T5	1098	988	0	0
T6	1153	1094	0	0
T7	1037	993	0	0
T24	1153	1111	0	0
T25	1050	992	0	0
T26	2371	2143	0	0
T27	1354	1313	0	0
T28	1437	1355	0	0
T29	2423	2072	0	0
T30	2138	1984	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72901641	79865	0	0
T3	0	373	0	0
T5	1098	64	0	0
T6	1153	0	0	0
T7	1037	0	0	0
T18	0	156	0	0
T19	0	165	0	0
T21	0	146	0	0
T22	0	355	0	0
T23	0	14	0	0
T24	1153	0	0	0
T25	1050	0	0	0
T26	2371	144	0	0
T27	1354	0	0	0
T28	1437	0	0	0
T29	2423	182	0	0
T30	2138	0	0	0
T35	0	172	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72901641	70709310	0	2322
T5	1098	1050	0	3
T6	1153	1092	0	3
T7	1037	991	0	3
T24	1153	1109	0	3
T25	1050	990	0	3
T26	2371	1943	0	3
T27	1354	1137	0	3
T28	1437	1301	0	3
T29	2423	1862	0	3
T30	2138	1982	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72901641	131039	0	0
T1	29517	0	0	0
T2	389922	0	0	0
T3	0	831	0	0
T18	1536	286	0	0
T19	2058	379	0	0
T21	0	151	0	0
T22	0	314	0	0
T26	2371	342	0	0
T27	1354	174	0	0
T28	1437	52	0	0
T29	2423	390	0	0
T30	2138	0	0	0
T35	0	236	0	0
T67	693	0	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72901641	70770704	0	0
T5	1098	1052	0	0
T6	1153	1094	0	0
T7	1037	993	0	0
T24	1153	1111	0	0
T25	1050	992	0	0
T26	2371	2120	0	0
T27	1354	1284	0	0
T28	1437	1355	0	0
T29	2423	2021	0	0
T30	2138	1984	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72901641	74023	0	0
T1	29517	0	0	0
T2	389922	0	0	0
T3	0	467	0	0
T18	1536	100	0	0
T19	2058	200	0	0
T21	0	119	0	0
T22	0	225	0	0
T26	2371	167	0	0
T27	1354	29	0	0
T28	1437	0	0	0
T29	2423	233	0	0
T30	2138	0	0	0
T35	0	151	0	0
T67	693	0	0	0
T111	0	102	0	0