Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	945936660	9267	0	0
TransStop_A	945936660	4812	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	945936660	9267	0	0
T1	491976	0	0	0
T2	3249300	17	0	0
T3	0	29	0	0
T4	119576	0	0	0
T11	0	223	0	0
T12	0	183	0	0
T15	0	18	0	0
T18	38416	0	0	0
T19	8320	0	0	0
T20	22016	10	0	0
T21	19900	0	0	0
T22	8684	0	0	0
T30	8640	4	0	0
T32	0	10	0	0
T67	11572	0	0	0
T78	0	4	0	0
T112	0	2	0	0
T113	0	15	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	945936660	4812	0	0
T1	491976	0	0	0
T2	3249300	13	0	0
T3	0	22	0	0
T4	119576	0	0	0
T11	0	133	0	0
T12	0	130	0	0
T15	0	15	0	0
T18	38416	0	0	0
T19	8320	0	0	0
T20	22016	3	0	0
T21	19900	0	0	0
T22	8684	0	0	0
T30	8640	4	0	0
T32	0	3	0	0
T67	11572	0	0	0
T78	0	4	0	0
T112	0	2	0	0
T113	0	17	0	0
T114	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	236484165	2289	0	0
TransStop_A	236484165	1171	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236484165	2289	0	0
T1	122994	0	0	0
T2	812325	5	0	0
T3	0	8	0	0
T4	29894	0	0	0
T11	0	60	0	0
T12	0	41	0	0
T15	0	4	0	0
T18	9604	0	0	0
T19	2080	0	0	0
T20	5504	6	0	0
T21	4975	0	0	0
T22	2171	0	0	0
T30	2160	1	0	0
T32	0	3	0	0
T67	2893	0	0	0
T78	0	1	0	0
T113	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236484165	1171	0	0
T1	122994	0	0	0
T2	812325	4	0	0
T3	0	6	0	0
T4	29894	0	0	0
T11	0	36	0	0
T12	0	29	0	0
T15	0	3	0	0
T18	9604	0	0	0
T19	2080	0	0	0
T20	5504	2	0	0
T21	4975	0	0	0
T22	2171	0	0	0
T30	2160	1	0	0
T32	0	1	0	0
T67	2893	0	0	0
T78	0	1	0	0
T113	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	236484165	2326	0	0
TransStop_A	236484165	1196	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236484165	2326	0	0
T1	122994	0	0	0
T2	812325	6	0	0
T3	0	6	0	0
T4	29894	0	0	0
T11	0	56	0	0
T12	0	51	0	0
T15	0	5	0	0
T18	9604	0	0	0
T19	2080	0	0	0
T20	5504	1	0	0
T21	4975	0	0	0
T22	2171	0	0	0
T30	2160	1	0	0
T32	0	2	0	0
T67	2893	0	0	0
T78	0	1	0	0
T113	0	9	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236484165	1196	0	0
T1	122994	0	0	0
T2	812325	5	0	0
T3	0	5	0	0
T4	29894	0	0	0
T11	0	34	0	0
T12	0	36	0	0
T15	0	4	0	0
T18	9604	0	0	0
T19	2080	0	0	0
T20	5504	1	0	0
T21	4975	0	0	0
T22	2171	0	0	0
T30	2160	1	0	0
T32	0	1	0	0
T67	2893	0	0	0
T78	0	1	0	0
T113	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	236484165	2340	0	0
TransStop_A	236484165	1236	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236484165	2340	0	0
T1	122994	0	0	0
T2	812325	3	0	0
T3	0	5	0	0
T4	29894	0	0	0
T11	0	60	0	0
T12	0	49	0	0
T15	0	4	0	0
T18	9604	0	0	0
T19	2080	0	0	0
T20	5504	2	0	0
T21	4975	0	0	0
T22	2171	0	0	0
T30	2160	1	0	0
T32	0	2	0	0
T67	2893	0	0	0
T78	0	1	0	0
T112	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236484165	1236	0	0
T1	122994	0	0	0
T2	812325	2	0	0
T3	0	4	0	0
T4	29894	0	0	0
T11	0	36	0	0
T12	0	37	0	0
T15	0	4	0	0
T18	9604	0	0	0
T19	2080	0	0	0
T20	5504	0	0	0
T21	4975	0	0	0
T22	2171	0	0	0
T30	2160	1	0	0
T67	2893	0	0	0
T78	0	1	0	0
T112	0	1	0	0
T113	0	5	0	0
T114	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	236484165	2312	0	0
TransStop_A	236484165	1209	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236484165	2312	0	0
T1	122994	0	0	0
T2	812325	3	0	0
T3	0	10	0	0
T4	29894	0	0	0
T11	0	47	0	0
T12	0	42	0	0
T15	0	5	0	0
T18	9604	0	0	0
T19	2080	0	0	0
T20	5504	1	0	0
T21	4975	0	0	0
T22	2171	0	0	0
T30	2160	1	0	0
T32	0	3	0	0
T67	2893	0	0	0
T78	0	1	0	0
T112	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236484165	1209	0	0
T1	122994	0	0	0
T2	812325	2	0	0
T3	0	7	0	0
T4	29894	0	0	0
T11	0	27	0	0
T12	0	28	0	0
T15	0	4	0	0
T18	9604	0	0	0
T19	2080	0	0	0
T20	5504	0	0	0
T21	4975	0	0	0
T22	2171	0	0	0
T30	2160	1	0	0
T32	0	1	0	0
T67	2893	0	0	0
T78	0	1	0	0
T112	0	1	0	0
T113	0	6	0	0