Unified Coverage Report :: Module :: prim_mubi4_sender

Module : prim_mubi4_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_clkmgr_byp.u_io_byp_req	100.00	100.00					100.00
tb.dut.u_clkmgr_byp.u_all_byp_req	100.00	100.00					100.00
tb.dut.u_clkmgr_byp.u_hi_speed_sel	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_io_div4_infra	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_main_infra	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_usb_infra	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_io_infra	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_io_div2_infra	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_io_div4_secure	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_main_secure	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_io_div4_timers	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_io_div4_peri	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_io_div2_peri	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_io_peri	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_usb_peri	100.00	100.00					100.00
tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender	100.00	100.00					100.00

---

Module Instance : tb.dut.u_clkmgr_byp.u_io_byp_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_clkmgr_byp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00
gen_sec_buf.u_prim_sec_buf	100.00	100.00

---

Module Instance : tb.dut.u_clkmgr_byp.u_all_byp_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_clkmgr_byp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00
gen_sec_buf.u_prim_sec_buf	100.00	100.00

---

Module Instance : tb.dut.u_clkmgr_byp.u_hi_speed_sel

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_clkmgr_byp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_aes_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_hmac_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_kmac_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_otbn_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

Line Coverage for Module : prim_mubi4_sender ( parameter AsyncOn=1,EnSecBuf=1,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_clkmgr_byp.u_io_byp_req

SCORE	LINE
100.00	100.00

tb.dut.u_clkmgr_byp.u_all_byp_req

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
85	1	1

---

Line Coverage for Module : prim_mubi4_sender ( parameter AsyncOn=1,EnSecBuf=0,ResetValue=6 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_clkmgr_byp.u_hi_speed_sel

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_io_div4_infra

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_main_infra

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_usb_infra

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_io_infra

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_io_div2_infra

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_io_div4_secure

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_main_secure

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_io_div4_timers

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_io_div4_peri

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_io_div2_peri

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_io_peri

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_usb_peri

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Module : prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T5	51070	49145	0	0
T6	51239	48785	0	0
T7	65775	63134	0	0
T24	49425	47792	0	0
T25	50236	47685	0	0
T26	33323	32252	0	0
T27	65364	63520	0	0
T28	20251	19164	0	0
T29	45307	42417	0	0
T30	29514	27599	0	0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_byp_req

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_byp_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	72901641	70846916	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72901641	70846916	0	0
T5	1098	1053	0	0
T6	1153	1095	0	0
T7	1037	994	0	0
T24	1153	1112	0	0
T25	1050	993	0	0
T26	2371	2288	0	0
T27	1354	1314	0	0
T28	1437	1356	0	0
T29	2423	2255	0	0
T30	2138	1985	0	0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_byp_req

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_byp_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	72901641	70846916	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72901641	70846916	0	0
T5	1098	1053	0	0
T6	1153	1095	0	0
T7	1037	994	0	0
T24	1153	1112	0	0
T25	1050	993	0	0
T26	2371	2288	0	0
T27	1354	1314	0	0
T28	1437	1356	0	0
T29	2423	2255	0	0
T30	2138	1985	0	0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_hi_speed_sel

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_hi_speed_sel

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	72901641	70846916	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72901641	70846916	0	0
T5	1098	1053	0	0
T6	1153	1095	0	0
T7	1037	994	0	0
T24	1153	1112	0	0
T25	1050	993	0	0
T26	2371	2288	0	0
T27	1354	1314	0	0
T28	1437	1356	0	0
T29	2423	2255	0	0
T30	2138	1985	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	54977509	54532269	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54977509	54532269	0	0
T5	1092	1071	0	0
T6	1045	1011	0	0
T7	1416	1385	0	0
T24	1005	988	0	0
T25	1024	993	0	0
T26	644	633	0	0
T27	1395	1367	0	0
T28	349	335	0	0
T29	911	880	0	0
T30	491	481	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_infra

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	236483738	232746377	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236483738	232746377	0	0
T5	4396	4213	0	0
T6	4439	4213	0	0
T7	5698	5443	0	0
T24	4271	4116	0	0
T25	4380	4140	0	0
T26	2371	2288	0	0
T27	5646	5477	0	0
T28	1481	1398	0	0
T29	3462	3221	0	0
T30	2159	2004	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	113377980	111587976	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113377980	111587976	0	0
T5	2110	2023	0	0
T6	2131	2023	0	0
T7	2787	2665	0	0
T24	2050	1976	0	0
T25	2102	1987	0	0
T26	1138	1099	0	0
T27	2710	2629	0	0
T28	710	671	0	0
T29	1661	1546	0	0
T30	1036	962	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_infra

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	221350909	217768842	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221350909	217768842	0	0
T5	4221	4045	0	0
T6	4261	4044	0	0
T7	5786	5541	0	0
T24	4100	3952	0	0
T25	4204	3973	0	0
T26	2276	2196	0	0
T27	5420	5257	0	0
T28	1421	1342	0	0
T29	3323	3092	0	0
T30	2072	1924	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	109955818	109065216	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	109955818	109065216	0	0
T5	2185	2144	0	0
T6	2091	2022	0	0
T7	2833	2771	0	0
T24	2010	1976	0	0
T25	2049	1987	0	0
T26	1290	1269	0	0
T27	2793	2738	0	0
T28	698	671	0	0
T29	1827	1765	0	0
T30	983	962	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	54977509	54532269	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54977509	54532269	0	0
T5	1092	1071	0	0
T6	1045	1011	0	0
T7	1416	1385	0	0
T24	1005	988	0	0
T25	1024	993	0	0
T26	644	633	0	0
T27	1395	1367	0	0
T28	349	335	0	0
T29	911	880	0	0
T30	491	481	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_secure

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	236483738	232746377	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236483738	232746377	0	0
T5	4396	4213	0	0
T6	4439	4213	0	0
T7	5698	5443	0	0
T24	4271	4116	0	0
T25	4380	4140	0	0
T26	2371	2288	0	0
T27	5646	5477	0	0
T28	1481	1398	0	0
T29	3462	3221	0	0
T30	2159	2004	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	54977509	54532269	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54977509	54532269	0	0
T5	1092	1071	0	0
T6	1045	1011	0	0
T7	1416	1385	0	0
T24	1005	988	0	0
T25	1024	993	0	0
T26	644	633	0	0
T27	1395	1367	0	0
T28	349	335	0	0
T29	911	880	0	0
T30	491	481	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	54977509	54532269	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54977509	54532269	0	0
T5	1092	1071	0	0
T6	1045	1011	0	0
T7	1416	1385	0	0
T24	1005	988	0	0
T25	1024	993	0	0
T26	644	633	0	0
T27	1395	1367	0	0
T28	349	335	0	0
T29	911	880	0	0
T30	491	481	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	109955818	109065216	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	109955818	109065216	0	0
T5	2185	2144	0	0
T6	2091	2022	0	0
T7	2833	2771	0	0
T24	2010	1976	0	0
T25	2049	1987	0	0
T26	1290	1269	0	0
T27	2793	2738	0	0
T28	698	671	0	0
T29	1827	1765	0	0
T30	983	962	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_peri

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	221350909	217768842	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221350909	217768842	0	0
T5	4221	4045	0	0
T6	4261	4044	0	0
T7	5786	5541	0	0
T24	4100	3952	0	0
T25	4204	3973	0	0
T26	2276	2196	0	0
T27	5420	5257	0	0
T28	1421	1342	0	0
T29	3323	3092	0	0
T30	2072	1924	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	113377980	111587976	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113377980	111587976	0	0
T5	2110	2023	0	0
T6	2131	2023	0	0
T7	2787	2665	0	0
T24	2050	1976	0	0
T25	2102	1987	0	0
T26	1138	1099	0	0
T27	2710	2629	0	0
T28	710	671	0	0
T29	1661	1546	0	0
T30	1036	962	0	0

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	236483738	232746377	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236483738	232746377	0	0
T5	4396	4213	0	0
T6	4439	4213	0	0
T7	5698	5443	0	0
T24	4271	4116	0	0
T25	4380	4140	0	0
T26	2371	2288	0	0
T27	5646	5477	0	0
T28	1481	1398	0	0
T29	3462	3221	0	0
T30	2159	2004	0	0

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	236483738	232746377	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236483738	232746377	0	0
T5	4396	4213	0	0
T6	4439	4213	0	0
T7	5698	5443	0	0
T24	4271	4116	0	0
T25	4380	4140	0	0
T26	2371	2288	0	0
T27	5646	5477	0	0
T28	1481	1398	0	0
T29	3462	3221	0	0
T30	2159	2004	0	0

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	236483738	232746377	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236483738	232746377	0	0
T5	4396	4213	0	0
T6	4439	4213	0	0
T7	5698	5443	0	0
T24	4271	4116	0	0
T25	4380	4140	0	0
T26	2371	2288	0	0
T27	5646	5477	0	0
T28	1481	1398	0	0
T29	3462	3221	0	0
T30	2159	2004	0	0

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	236483738	232746377	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236483738	232746377	0	0
T5	4396	4213	0	0
T6	4439	4213	0	0
T7	5698	5443	0	0
T24	4271	4116	0	0
T25	4380	4140	0	0
T26	2371	2288	0	0
T27	5646	5477	0	0
T28	1481	1398	0	0
T29	3462	3221	0	0
T30	2159	2004	0	0