Module Definition
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Module Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 100.00 100.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 100.00 100.00 100.00 66.67 u_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_out 100.00 100.00 100.00
u_ref_timeout 87.50 100.00 100.00 100.00 50.00



Module Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 100.00 100.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 100.00 100.00 100.00 66.67 u_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_out 100.00 100.00 100.00
u_ref_timeout 87.50 100.00 100.00 100.00 50.00



Module Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 100.00 100.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 100.00 100.00 100.00 66.67 u_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_out 100.00 100.00 100.00
u_ref_timeout 87.50 100.00 100.00 100.00 50.00



Module Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 100.00 100.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 100.00 100.00 100.00 66.67 u_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_out 100.00 100.00 100.00
u_ref_timeout 87.50 100.00 100.00 100.00 50.00



Module Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 100.00 100.00 100.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.33 100.00 100.00 100.00 100.00 66.67 u_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_out 100.00 100.00 100.00
u_ref_timeout 87.50 100.00 100.00 100.00 50.00

Line Coverage for Module : prim_clock_timeout
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3000
ALWAYS3277100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
30 unreachable
32 1 1
33 1 1
34 1 1
35 1 1
36 1 1
37 unreachable
38 1 1
39 1 1
==> MISSING_ELSE


Cond Coverage for Module : prim_clock_timeout
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (ack || ((!en_i)))
             -1-    ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T6,T7
10CoveredT1,T2,T3

Branch Coverage for Module : prim_clock_timeout
Line No.TotalCoveredPercent
Branches 4 3 75.00
IF 32 4 3 75.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 32 if ((!rst_ni)) -2-: 34 if ((ack || (!en_i))) -3-: 36 if (timeout) -4-: 38 if (en_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T5,T6,T7
0 1 - - Covered T5,T6,T7
0 0 1 - Unreachable T2,T11,T12
0 0 0 1 Covered T1,T2,T3
0 0 0 0 Not Covered

Line Coverage for Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3000
ALWAYS3277100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
30 unreachable
32 1 1
33 1 1
34 1 1
35 1 1
36 1 1
37 unreachable
38 1 1
39 1 1
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (ack || ((!en_i)))
             -1-    ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T6,T7
10CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk
Line No.TotalCoveredPercent
Branches 3 3 100.00
IF 32 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 32 if ((!rst_ni)) -2-: 34 if ((ack || (!en_i))) -3-: 36 if (timeout) -4-: 38 if (en_i)

Branches:
-1--2--3--4-StatusTestsExclude Annotation
1 - - - Covered T5,T6,T7
0 1 - - Covered T5,T6,T7
0 0 1 - Unreachable T2,T11,T12
0 0 0 1 Covered T1,T2,T3
0 0 0 0 Excluded VC_COV_UNR

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3000
ALWAYS3277100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
30 unreachable
32 1 1
33 1 1
34 1 1
35 1 1
36 1 1
37 unreachable
38 1 1
39 1 1
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (ack || ((!en_i)))
             -1-    ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T6,T7
10CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk
Line No.TotalCoveredPercent
Branches 3 3 100.00
IF 32 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 32 if ((!rst_ni)) -2-: 34 if ((ack || (!en_i))) -3-: 36 if (timeout) -4-: 38 if (en_i)

Branches:
-1--2--3--4-StatusTestsExclude Annotation
1 - - - Covered T5,T6,T7
0 1 - - Covered T5,T6,T7
0 0 1 - Unreachable T2,T11,T12
0 0 0 1 Covered T1,T2,T3
0 0 0 0 Excluded VC_COV_UNR

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3000
ALWAYS3277100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
30 unreachable
32 1 1
33 1 1
34 1 1
35 1 1
36 1 1
37 unreachable
38 1 1
39 1 1
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (ack || ((!en_i)))
             -1-    ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T6,T7
10CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk
Line No.TotalCoveredPercent
Branches 3 3 100.00
IF 32 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 32 if ((!rst_ni)) -2-: 34 if ((ack || (!en_i))) -3-: 36 if (timeout) -4-: 38 if (en_i)

Branches:
-1--2--3--4-StatusTestsExclude Annotation
1 - - - Covered T5,T6,T7
0 1 - - Covered T5,T6,T7
0 0 1 - Unreachable T2,T11,T12
0 0 0 1 Covered T1,T2,T3
0 0 0 0 Excluded VC_COV_UNR

Line Coverage for Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3000
ALWAYS3277100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
30 unreachable
32 1 1
33 1 1
34 1 1
35 1 1
36 1 1
37 unreachable
38 1 1
39 1 1
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (ack || ((!en_i)))
             -1-    ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T6,T7
10CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk
Line No.TotalCoveredPercent
Branches 3 3 100.00
IF 32 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 32 if ((!rst_ni)) -2-: 34 if ((ack || (!en_i))) -3-: 36 if (timeout) -4-: 38 if (en_i)

Branches:
-1--2--3--4-StatusTestsExclude Annotation
1 - - - Covered T5,T6,T7
0 1 - - Covered T5,T6,T7
0 0 1 - Unreachable T11,T12,T33
0 0 0 1 Covered T1,T2,T3
0 0 0 0 Excluded VC_COV_UNR

Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN3000
ALWAYS3277100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
30 unreachable
32 1 1
33 1 1
34 1 1
35 1 1
36 1 1
37 unreachable
38 1 1
39 1 1
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (ack || ((!en_i)))
             -1-    ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T6,T7
10CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk
Line No.TotalCoveredPercent
Branches 3 3 100.00
IF 32 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv' or '../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 32 if ((!rst_ni)) -2-: 34 if ((ack || (!en_i))) -3-: 36 if (timeout) -4-: 38 if (en_i)

Branches:
-1--2--3--4-StatusTestsExclude Annotation
1 - - - Covered T5,T6,T7
0 1 - - Covered T5,T6,T7
0 0 1 - Unreachable T2,T11,T12
0 0 0 1 Covered T1,T2,T3
0 0 0 0 Excluded VC_COV_UNR

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