Unified Coverage Report :: Module :: prim_sync_reqack

Module : prim_sync_reqack

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00	50.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout	87.50	100.00	100.00			100.00	50.00
tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout	87.50	100.00	100.00			100.00	50.00
tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout	87.50	100.00	100.00			100.00	50.00
tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout	87.50	100.00	100.00			100.00	50.00
tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout	87.50	100.00	100.00			100.00	50.00
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync	93.75	100.00	75.00			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync	93.75	100.00	75.00			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync	93.75	100.00	75.00			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync	93.75	100.00	75.00			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync	93.75	100.00	75.00			100.00	100.00
tb.dut.u_io_meas.u_err_sync	93.75	100.00	75.00			100.00	100.00
tb.dut.u_io_div2_meas.u_err_sync	93.75	100.00	75.00			100.00	100.00
tb.dut.u_io_div4_meas.u_err_sync	93.75	100.00	75.00			100.00	100.00
tb.dut.u_main_meas.u_err_sync	93.75	100.00	75.00			100.00	100.00
tb.dut.u_usb_meas.u_err_sync	93.75	100.00	75.00			100.00	100.00

---

Module Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00	100.00			100.00	50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00	100.00			100.00	50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		gen_clk_timeout_chk.u_timeout_ref_to_clk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_nrz_hs_protocol.ack_sync	100.00	100.00				100.00
gen_nrz_hs_protocol.req_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00	100.00			100.00	50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00	100.00			100.00	50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		gen_clk_timeout_chk.u_timeout_ref_to_clk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_nrz_hs_protocol.ack_sync	100.00	100.00				100.00
gen_nrz_hs_protocol.req_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00	100.00			100.00	50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00	100.00			100.00	50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		gen_clk_timeout_chk.u_timeout_ref_to_clk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_nrz_hs_protocol.ack_sync	100.00	100.00				100.00
gen_nrz_hs_protocol.req_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00	100.00			100.00	50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00	100.00			100.00	50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		gen_clk_timeout_chk.u_timeout_ref_to_clk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_nrz_hs_protocol.ack_sync	100.00	100.00				100.00
gen_nrz_hs_protocol.req_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00	100.00			100.00	50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00	100.00			100.00	50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		gen_clk_timeout_chk.u_timeout_ref_to_clk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_nrz_hs_protocol.ack_sync	100.00	100.00				100.00
gen_nrz_hs_protocol.req_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
73.61	90.00	76.19			78.26	50.00	u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_nrz_hs_protocol.ack_sync	100.00	100.00				100.00
gen_nrz_hs_protocol.req_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
73.61	90.00	76.19			78.26	50.00	u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_nrz_hs_protocol.ack_sync	100.00	100.00				100.00
gen_nrz_hs_protocol.req_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
79.17	94.00	85.71			86.96	50.00	u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_nrz_hs_protocol.ack_sync	100.00	100.00				100.00
gen_nrz_hs_protocol.req_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
73.61	90.00	76.19			78.26	50.00	u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_nrz_hs_protocol.ack_sync	100.00	100.00				100.00
gen_nrz_hs_protocol.req_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
73.61	90.00	76.19			78.26	50.00	u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_nrz_hs_protocol.ack_sync	100.00	100.00				100.00
gen_nrz_hs_protocol.req_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_io_meas.u_err_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33			100.00		u_io_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_nrz_hs_protocol.ack_sync	100.00	100.00				100.00
gen_nrz_hs_protocol.req_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_io_div2_meas.u_err_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33			100.00		u_io_div2_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_nrz_hs_protocol.ack_sync	100.00	100.00				100.00
gen_nrz_hs_protocol.req_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_io_div4_meas.u_err_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33			100.00		u_io_div4_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_nrz_hs_protocol.ack_sync	100.00	100.00				100.00
gen_nrz_hs_protocol.req_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_main_meas.u_err_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33			100.00		u_main_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_nrz_hs_protocol.ack_sync	100.00	100.00				100.00
gen_nrz_hs_protocol.req_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_usb_meas.u_err_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33			100.00		u_usb_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_nrz_hs_protocol.ack_sync	100.00	100.00				100.00
gen_nrz_hs_protocol.req_sync	100.00	100.00				100.00

Line Coverage for Module : prim_sync_reqack

	Line No.	Total	Covered	Percent
TOTAL		36	36	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
ALWAYS	219	12	12	100.00
ALWAYS	263	12	12	100.00
ALWAYS	307	5	5	100.00
ALWAYS	316	5	5	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
194	1	1
195	1	1
219	1	1
222	1	1
223	1	1
225	1	1
229	1	1
230	1	1
233	1	1
234	1	1
			MISSING_ELSE
241	1	1
242	1	1
245	1	1
246	1	1
			MISSING_ELSE
263	1	1
266	1	1
267	1	1
269	1	1
273	1	1
274	1	1
277	1	1
278	1	1
			MISSING_ELSE
285	1	1
286	1	1
289	1	1
290	1	1
			MISSING_ELSE
307	1	1
308	1	1
309	1	1
311	1	1
312	1	1
316	1	1
317	1	1
318	1	1
320	1	1
321	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Module : prim_sync_reqack

	Total	Covered	Percent
Conditions	6	3	50.00
Logical	6	3	50.00
Non-Logical	0	0
Event	0	0

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T5,T6,T7

---

Branch Coverage for Module : prim_sync_reqack

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
CASE	225	4	4	100.00
CASE	269	4	4	100.00
IF	307	2	2	100.00
IF	316	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	225	case (gen_nrz_hs_protocol.src_fsm_cs)
-2-:	233	if (gen_nrz_hs_protocol.src_handshake)
-3-:	245	if (gen_nrz_hs_protocol.src_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T5,T6,T7
EVEN	0	-	Covered	T5,T6,T7
ODD	-	1	Covered	T5,T6,T7
ODD	-	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	269	case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-:	277	if (gen_nrz_hs_protocol.dst_handshake)
-3-:	289	if (gen_nrz_hs_protocol.dst_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T5,T6,T7
EVEN	0	-	Covered	T5,T6,T7
ODD	-	1	Covered	T5,T6,T7
ODD	-	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	307	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	316	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Module : prim_sync_reqack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	1469797664	7976603	0	0
SyncReqAckHoldReq	1516665665	80240	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	1469797664	7976603	0	0
T1	59034	13	0	0
T2	1169766	51	0	0
T3	879783	13	0	0
T4	22416	0	0	0
T5	3277	65	0	0
T6	3136	66	0	0
T7	4249	90	0	0
T11	0	68	0	0
T12	0	68	0	0
T13	0	13	0	0
T14	0	16	0	0
T15	0	7	0	0
T16	0	11	0	0
T17	0	3	0	0
T18	3072	0	0	0
T19	6174	0	0	0
T20	4125	0	0	0
T21	3729	0	0	0
T22	6510	0	0	0
T23	2019	0	0	0
T24	3015	65	0	0
T25	3073	64	0	0
T26	1934	36	0	0
T27	4188	85	0	0
T28	1047	23	0	0
T29	2738	51	0	0
T30	1474	31	0	0
T31	0	10	0	0
T32	1822	0	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	1516665665	80240	0	0
T1	600161	120	0	0
T2	5080854	805	0	0
T3	1872078	298	0	0
T4	176590	36	0	0
T11	0	1434	0	0
T12	0	1449	0	0
T13	0	129	0	0
T14	0	245	0	0
T15	0	225	0	0
T16	0	27	0	0
T17	0	6	0	0
T18	48330	0	0	0
T19	13374	0	0	0
T20	34578	0	0	0
T21	32382	0	0	0
T22	14074	0	0	0
T23	16966	0	0	0
T31	0	31	0	0
T32	2733	0	0	0
T33	0	70	0	0
T34	0	11	0	0
T35	4409	0	0	0

Line Coverage for Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

	Line No.	Total	Covered	Percent
TOTAL		36	36	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
ALWAYS	219	12	12	100.00
ALWAYS	263	12	12	100.00
ALWAYS	307	5	5	100.00
ALWAYS	316	5	5	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
194	1	1
195	1	1
219	1	1
222	1	1
223	1	1
225	1	1
229	1	1
230	1	1
233	1	1
234	1	1
			MISSING_ELSE
241	1	1
242	1	1
245	1	1
246	1	1
			MISSING_ELSE
263	1	1
266	1	1
267	1	1
269	1	1
273	1	1
274	1	1
277	1	1
278	1	1
			MISSING_ELSE
285	1	1
286	1	1
289	1	1
290	1	1
			MISSING_ELSE
307	1	1
308	1	1
309	1	1
311	1	1
312	1	1
316	1	1
317	1	1
318	1	1
320	1	1
321	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Covered	T5,T6,T7

---

Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
CASE	225	4	4	100.00
CASE	269	4	4	100.00
IF	307	2	2	100.00
IF	316	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	225	case (gen_nrz_hs_protocol.src_fsm_cs)
-2-:	233	if (gen_nrz_hs_protocol.src_handshake)
-3-:	245	if (gen_nrz_hs_protocol.src_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T5,T6,T7
EVEN	0	-	Covered	T5,T6,T7
ODD	-	1	Covered	T5,T6,T7
ODD	-	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	269	case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-:	277	if (gen_nrz_hs_protocol.dst_handshake)
-3-:	289	if (gen_nrz_hs_protocol.dst_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T5,T6,T7
EVEN	0	-	Covered	T5,T6,T7
ODD	-	1	Covered	T5,T6,T7
ODD	-	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	307	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	316	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	221350909	1592394	0	0
SyncReqAckHoldReq	7203217	0	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	221350909	1592394	0	0
T5	4221	65	0	0
T6	4261	66	0	0
T7	5786	91	0	0
T24	4100	65	0	0
T25	4204	64	0	0
T26	2276	36	0	0
T27	5420	85	0	0
T28	1421	23	0	0
T29	3323	51	0	0
T30	2072	31	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	7203217	0	0	0

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

	Line No.	Total	Covered	Percent
TOTAL		36	36	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
ALWAYS	219	12	12	100.00
ALWAYS	263	12	12	100.00
ALWAYS	307	5	5	100.00
ALWAYS	316	5	5	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
194	1	1
195	1	1
219	1	1
222	1	1
223	1	1
225	1	1
229	1	1
230	1	1
233	1	1
234	1	1
			MISSING_ELSE
241	1	1
242	1	1
245	1	1
246	1	1
			MISSING_ELSE
263	1	1
266	1	1
267	1	1
269	1	1
273	1	1
274	1	1
277	1	1
278	1	1
			MISSING_ELSE
285	1	1
286	1	1
289	1	1
290	1	1
			MISSING_ELSE
307	1	1
308	1	1
309	1	1
311	1	1
312	1	1
316	1	1
317	1	1
318	1	1
320	1	1
321	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Covered	T5,T6,T7

---

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
CASE	225	4	4	100.00
CASE	269	4	4	100.00
IF	307	2	2	100.00
IF	316	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	225	case (gen_nrz_hs_protocol.src_fsm_cs)
-2-:	233	if (gen_nrz_hs_protocol.src_handshake)
-3-:	245	if (gen_nrz_hs_protocol.src_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T5,T6,T7
EVEN	0	-	Covered	T5,T6,T7
ODD	-	1	Covered	T5,T6,T7
ODD	-	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	269	case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-:	277	if (gen_nrz_hs_protocol.dst_handshake)
-3-:	289	if (gen_nrz_hs_protocol.dst_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T5,T6,T7
EVEN	0	-	Covered	T5,T6,T7
ODD	-	1	Covered	T5,T6,T7
ODD	-	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	307	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	316	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	109955818	1592274	0	0
SyncReqAckHoldReq	7203217	0	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	109955818	1592274	0	0
T5	2185	65	0	0
T6	2091	66	0	0
T7	2833	90	0	0
T24	2010	65	0	0
T25	2049	64	0	0
T26	1290	36	0	0
T27	2793	85	0	0
T28	698	23	0	0
T29	1827	51	0	0
T30	983	31	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	7203217	0	0	0

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

	Line No.	Total	Covered	Percent
TOTAL		36	36	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
ALWAYS	219	12	12	100.00
ALWAYS	263	12	12	100.00
ALWAYS	307	5	5	100.00
ALWAYS	316	5	5	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
194	1	1
195	1	1
219	1	1
222	1	1
223	1	1
225	1	1
229	1	1
230	1	1
233	1	1
234	1	1
			MISSING_ELSE
241	1	1
242	1	1
245	1	1
246	1	1
			MISSING_ELSE
263	1	1
266	1	1
267	1	1
269	1	1
273	1	1
274	1	1
277	1	1
278	1	1
			MISSING_ELSE
285	1	1
286	1	1
289	1	1
290	1	1
			MISSING_ELSE
307	1	1
308	1	1
309	1	1
311	1	1
312	1	1
316	1	1
317	1	1
318	1	1
320	1	1
321	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Covered	T5,T6,T7

---

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
CASE	225	4	4	100.00
CASE	269	4	4	100.00
IF	307	2	2	100.00
IF	316	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	225	case (gen_nrz_hs_protocol.src_fsm_cs)
-2-:	233	if (gen_nrz_hs_protocol.src_handshake)
-3-:	245	if (gen_nrz_hs_protocol.src_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T5,T6,T7
EVEN	0	-	Covered	T5,T6,T7
ODD	-	1	Covered	T5,T6,T7
ODD	-	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	269	case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-:	277	if (gen_nrz_hs_protocol.dst_handshake)
-3-:	289	if (gen_nrz_hs_protocol.dst_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T5,T6,T7
EVEN	0	-	Covered	T5,T6,T7
ODD	-	1	Covered	T5,T6,T7
ODD	-	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	307	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	316	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	54977509	1519203	0	0
SyncReqAckHoldReq	7203217	0	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	54977509	1519203	0	0
T5	1092	62	0	0
T6	1045	63	0	0
T7	1416	86	0	0
T24	1005	62	0	0
T25	1024	62	0	0
T26	644	34	0	0
T27	1395	82	0	0
T28	349	21	0	0
T29	911	49	0	0
T30	491	30	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	7203217	0	0	0

Line Coverage for Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

	Line No.	Total	Covered	Percent
TOTAL		36	36	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
ALWAYS	219	12	12	100.00
ALWAYS	263	12	12	100.00
ALWAYS	307	5	5	100.00
ALWAYS	316	5	5	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
194	1	1
195	1	1
219	1	1
222	1	1
223	1	1
225	1	1
229	1	1
230	1	1
233	1	1
234	1	1
			MISSING_ELSE
241	1	1
242	1	1
245	1	1
246	1	1
			MISSING_ELSE
263	1	1
266	1	1
267	1	1
269	1	1
273	1	1
274	1	1
277	1	1
278	1	1
			MISSING_ELSE
285	1	1
286	1	1
289	1	1
290	1	1
			MISSING_ELSE
307	1	1
308	1	1
309	1	1
311	1	1
312	1	1
316	1	1
317	1	1
318	1	1
320	1	1
321	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Covered	T5,T6,T7

---

Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
CASE	225	4	4	100.00
CASE	269	4	4	100.00
IF	307	2	2	100.00
IF	316	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	225	case (gen_nrz_hs_protocol.src_fsm_cs)
-2-:	233	if (gen_nrz_hs_protocol.src_handshake)
-3-:	245	if (gen_nrz_hs_protocol.src_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T5,T6,T7
EVEN	0	-	Covered	T5,T6,T7
ODD	-	1	Covered	T5,T6,T7
ODD	-	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	269	case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-:	277	if (gen_nrz_hs_protocol.dst_handshake)
-3-:	289	if (gen_nrz_hs_protocol.dst_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T5,T6,T7
EVEN	0	-	Covered	T5,T6,T7
ODD	-	1	Covered	T5,T6,T7
ODD	-	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	307	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	316	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	236483738	1594650	0	0
SyncReqAckHoldReq	7203217	0	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	236483738	1594650	0	0
T5	4396	65	0	0
T6	4439	66	0	0
T7	5698	85	0	0
T24	4271	65	0	0
T25	4380	64	0	0
T26	2371	36	0	0
T27	5646	85	0	0
T28	1481	23	0	0
T29	3462	51	0	0
T30	2159	31	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	7203217	0	0	0

Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

	Line No.	Total	Covered	Percent
TOTAL		36	36	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
ALWAYS	219	12	12	100.00
ALWAYS	263	12	12	100.00
ALWAYS	307	5	5	100.00
ALWAYS	316	5	5	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
194	1	1
195	1	1
219	1	1
222	1	1
223	1	1
225	1	1
229	1	1
230	1	1
233	1	1
234	1	1
			MISSING_ELSE
241	1	1
242	1	1
245	1	1
246	1	1
			MISSING_ELSE
263	1	1
266	1	1
267	1	1
269	1	1
273	1	1
274	1	1
277	1	1
278	1	1
			MISSING_ELSE
285	1	1
286	1	1
289	1	1
290	1	1
			MISSING_ELSE
307	1	1
308	1	1
309	1	1
311	1	1
312	1	1
316	1	1
317	1	1
318	1	1
320	1	1
321	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Covered	T5,T6,T7

---

Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
CASE	225	4	4	100.00
CASE	269	4	4	100.00
IF	307	2	2	100.00
IF	316	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	225	case (gen_nrz_hs_protocol.src_fsm_cs)
-2-:	233	if (gen_nrz_hs_protocol.src_handshake)
-3-:	245	if (gen_nrz_hs_protocol.src_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T5,T6,T7
EVEN	0	-	Covered	T5,T6,T7
ODD	-	1	Covered	T5,T6,T7
ODD	-	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	269	case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-:	277	if (gen_nrz_hs_protocol.dst_handshake)
-3-:	289	if (gen_nrz_hs_protocol.dst_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T5,T6,T7
EVEN	0	-	Covered	T5,T6,T7
ODD	-	1	Covered	T5,T6,T7
ODD	-	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	307	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	316	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk.u_ref_timeout

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	113377980	1594440	0	0
SyncReqAckHoldReq	7203217	0	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	113377980	1594440	0	0
T5	2110	65	0	0
T6	2131	66	0	0
T7	2787	88	0	0
T24	2050	65	0	0
T25	2102	64	0	0
T26	1138	36	0	0
T27	2710	85	0	0
T28	710	23	0	0
T29	1661	51	0	0
T30	1036	31	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	7203217	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

	Line No.	Total	Covered	Percent
TOTAL		36	36	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
ALWAYS	219	12	12	100.00
ALWAYS	263	12	12	100.00
ALWAYS	307	5	5	100.00
ALWAYS	316	5	5	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
194	1	1
195	1	1
219	1	1
222	1	1
223	1	1
225	1	1
229	1	1
230	1	1
233	1	1
234	1	1
			MISSING_ELSE
241	1	1
242	1	1
245	1	1
246	1	1
			MISSING_ELSE
263	1	1
266	1	1
267	1	1
269	1	1
273	1	1
274	1	1
277	1	1
278	1	1
			MISSING_ELSE
285	1	1
286	1	1
289	1	1
290	1	1
			MISSING_ELSE
307	1	1
308	1	1
309	1	1
311	1	1
312	1	1
316	1	1
317	1	1
318	1	1
320	1	1
321	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

	Total	Covered	Percent
Conditions	4	3	75.00
Logical	4	3	75.00
Non-Logical	0	0
Event	0	0

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
CASE	225	4	4	100.00
CASE	269	4	4	100.00
IF	307	2	2	100.00
IF	316	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	225	case (gen_nrz_hs_protocol.src_fsm_cs)
-2-:	233	if (gen_nrz_hs_protocol.src_handshake)
-3-:	245	if (gen_nrz_hs_protocol.src_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T1,T2,T4
EVEN	0	-	Covered	T1,T2,T4
ODD	-	1	Covered	T1,T2,T4
ODD	-	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	269	case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-:	277	if (gen_nrz_hs_protocol.dst_handshake)
-3-:	289	if (gen_nrz_hs_protocol.dst_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T1,T2,T4
EVEN	0	-	Covered	T1,T2,T4
ODD	-	1	Covered	T1,T2,T4
ODD	-	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	307	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	316	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	73828701	15151	0	0
SyncReqAckHoldReq	223910640	14511	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	73828701	15151	0	0
T1	29517	23	0	0
T2	389922	153	0	0
T3	293261	56	0	0
T4	7472	8	0	0
T11	0	265	0	0
T12	0	258	0	0
T13	0	22	0	0
T14	0	44	0	0
T15	0	39	0	0
T18	1536	0	0	0
T19	2058	0	0	0
T20	1375	0	0	0
T21	1243	0	0	0
T22	2170	0	0	0
T23	673	0	0	0
T33	0	14	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	223910640	14511	0	0
T1	118070	20	0	0
T2	768287	136	0	0
T3	284364	50	0	0
T4	28697	8	0	0
T11	0	259	0	0
T12	0	254	0	0
T13	0	20	0	0
T14	0	40	0	0
T15	0	38	0	0
T18	9219	0	0	0
T19	1995	0	0	0
T20	5283	0	0	0
T21	4775	0	0	0
T22	2084	0	0	0
T23	2589	0	0	0
T33	0	14	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

	Line No.	Total	Covered	Percent
TOTAL		36	36	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
ALWAYS	219	12	12	100.00
ALWAYS	263	12	12	100.00
ALWAYS	307	5	5	100.00
ALWAYS	316	5	5	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
194	1	1
195	1	1
219	1	1
222	1	1
223	1	1
225	1	1
229	1	1
230	1	1
233	1	1
234	1	1
			MISSING_ELSE
241	1	1
242	1	1
245	1	1
246	1	1
			MISSING_ELSE
263	1	1
266	1	1
267	1	1
269	1	1
273	1	1
274	1	1
277	1	1
278	1	1
			MISSING_ELSE
285	1	1
286	1	1
289	1	1
290	1	1
			MISSING_ELSE
307	1	1
308	1	1
309	1	1
311	1	1
312	1	1
316	1	1
317	1	1
318	1	1
320	1	1
321	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

	Total	Covered	Percent
Conditions	4	3	75.00
Logical	4	3	75.00
Non-Logical	0	0
Event	0	0

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
CASE	225	4	4	100.00
CASE	269	4	4	100.00
IF	307	2	2	100.00
IF	316	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	225	case (gen_nrz_hs_protocol.src_fsm_cs)
-2-:	233	if (gen_nrz_hs_protocol.src_handshake)
-3-:	245	if (gen_nrz_hs_protocol.src_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T1,T2,T4
EVEN	0	-	Covered	T1,T2,T4
ODD	-	1	Covered	T1,T2,T4
ODD	-	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	269	case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-:	277	if (gen_nrz_hs_protocol.dst_handshake)
-3-:	289	if (gen_nrz_hs_protocol.dst_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T1,T2,T4
EVEN	0	-	Covered	T1,T2,T4
ODD	-	1	Covered	T1,T2,T4
ODD	-	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	307	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	316	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	73828701	15151	0	0
SyncReqAckHoldReq	111190200	14507	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	73828701	15151	0	0
T1	29517	23	0	0
T2	389922	153	0	0
T3	293261	56	0	0
T4	7472	8	0	0
T11	0	265	0	0
T12	0	258	0	0
T13	0	22	0	0
T14	0	44	0	0
T15	0	39	0	0
T18	1536	0	0	0
T19	2058	0	0	0
T20	1375	0	0	0
T21	1243	0	0	0
T22	2170	0	0	0
T23	673	0	0	0
T33	0	14	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	111190200	14507	0	0
T1	59023	20	0	0
T2	383768	136	0	0
T3	142179	50	0	0
T4	10237	8	0	0
T11	0	259	0	0
T12	0	254	0	0
T13	0	20	0	0
T14	0	40	0	0
T15	0	38	0	0
T18	5099	0	0	0
T19	1078	0	0	0
T20	2575	0	0	0
T21	2702	0	0	0
T22	1162	0	0	0
T23	1268	0	0	0
T33	0	14	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

	Line No.	Total	Covered	Percent
TOTAL		36	36	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
ALWAYS	219	12	12	100.00
ALWAYS	263	12	12	100.00
ALWAYS	307	5	5	100.00
ALWAYS	316	5	5	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
194	1	1
195	1	1
219	1	1
222	1	1
223	1	1
225	1	1
229	1	1
230	1	1
233	1	1
234	1	1
			MISSING_ELSE
241	1	1
242	1	1
245	1	1
246	1	1
			MISSING_ELSE
263	1	1
266	1	1
267	1	1
269	1	1
273	1	1
274	1	1
277	1	1
278	1	1
			MISSING_ELSE
285	1	1
286	1	1
289	1	1
290	1	1
			MISSING_ELSE
307	1	1
308	1	1
309	1	1
311	1	1
312	1	1
316	1	1
317	1	1
318	1	1
320	1	1
321	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

	Total	Covered	Percent
Conditions	4	3	75.00
Logical	4	3	75.00
Non-Logical	0	0
Event	0	0

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
CASE	225	4	4	100.00
CASE	269	4	4	100.00
IF	307	2	2	100.00
IF	316	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	225	case (gen_nrz_hs_protocol.src_fsm_cs)
-2-:	233	if (gen_nrz_hs_protocol.src_handshake)
-3-:	245	if (gen_nrz_hs_protocol.src_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T1,T2,T4
EVEN	0	-	Covered	T1,T2,T4
ODD	-	1	Covered	T1,T2,T4
ODD	-	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	269	case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-:	277	if (gen_nrz_hs_protocol.dst_handshake)
-3-:	289	if (gen_nrz_hs_protocol.dst_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T1,T2,T4
EVEN	0	-	Covered	T1,T2,T4
ODD	-	1	Covered	T1,T2,T4
ODD	-	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	307	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	316	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	73828701	15151	0	0
SyncReqAckHoldReq	55594684	14448	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	73828701	15151	0	0
T1	29517	23	0	0
T2	389922	153	0	0
T3	293261	56	0	0
T4	7472	8	0	0
T11	0	265	0	0
T12	0	258	0	0
T13	0	22	0	0
T14	0	44	0	0
T15	0	39	0	0
T18	1536	0	0	0
T19	2058	0	0	0
T20	1375	0	0	0
T21	1243	0	0	0
T22	2170	0	0	0
T23	673	0	0	0
T33	0	14	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	55594684	14448	0	0
T1	29511	20	0	0
T2	191885	136	0	0
T3	71085	50	0	0
T4	5118	8	0	0
T11	0	259	0	0
T12	0	254	0	0
T13	0	20	0	0
T14	0	40	0	0
T15	0	38	0	0
T18	2548	0	0	0
T19	538	0	0	0
T20	1287	0	0	0
T21	1351	0	0	0
T22	579	0	0	0
T23	634	0	0	0
T33	0	14	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

	Line No.	Total	Covered	Percent
TOTAL		36	36	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
ALWAYS	219	12	12	100.00
ALWAYS	263	12	12	100.00
ALWAYS	307	5	5	100.00
ALWAYS	316	5	5	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
194	1	1
195	1	1
219	1	1
222	1	1
223	1	1
225	1	1
229	1	1
230	1	1
233	1	1
234	1	1
			MISSING_ELSE
241	1	1
242	1	1
245	1	1
246	1	1
			MISSING_ELSE
263	1	1
266	1	1
267	1	1
269	1	1
273	1	1
274	1	1
277	1	1
278	1	1
			MISSING_ELSE
285	1	1
286	1	1
289	1	1
290	1	1
			MISSING_ELSE
307	1	1
308	1	1
309	1	1
311	1	1
312	1	1
316	1	1
317	1	1
318	1	1
320	1	1
321	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

	Total	Covered	Percent
Conditions	4	3	75.00
Logical	4	3	75.00
Non-Logical	0	0
Event	0	0

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
CASE	225	4	4	100.00
CASE	269	4	4	100.00
IF	307	2	2	100.00
IF	316	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	225	case (gen_nrz_hs_protocol.src_fsm_cs)
-2-:	233	if (gen_nrz_hs_protocol.src_handshake)
-3-:	245	if (gen_nrz_hs_protocol.src_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T1,T2,T4
EVEN	0	-	Covered	T1,T2,T4
ODD	-	1	Covered	T1,T2,T4
ODD	-	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	269	case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-:	277	if (gen_nrz_hs_protocol.dst_handshake)
-3-:	289	if (gen_nrz_hs_protocol.dst_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T1,T2,T4
EVEN	0	-	Covered	T1,T2,T4
ODD	-	1	Covered	T1,T2,T4
ODD	-	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	307	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	316	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	73828701	15151	0	0
SyncReqAckHoldReq	239150230	14511	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	73828701	15151	0	0
T1	29517	23	0	0
T2	389922	153	0	0
T3	293261	56	0	0
T4	7472	8	0	0
T11	0	265	0	0
T12	0	258	0	0
T13	0	22	0	0
T14	0	44	0	0
T15	0	39	0	0
T18	1536	0	0	0
T19	2058	0	0	0
T20	1375	0	0	0
T21	1243	0	0	0
T22	2170	0	0	0
T23	673	0	0	0
T33	0	14	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	239150230	14511	0	0
T1	122993	20	0	0
T2	812325	136	0	0
T3	296222	50	0	0
T4	29894	8	0	0
T11	0	259	0	0
T12	0	254	0	0
T13	0	20	0	0
T14	0	40	0	0
T15	0	38	0	0
T18	9604	0	0	0
T19	2079	0	0	0
T20	5503	0	0	0
T21	4975	0	0	0
T22	2170	0	0	0
T23	2697	0	0	0
T33	0	14	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

	Line No.	Total	Covered	Percent
TOTAL		36	36	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
ALWAYS	219	12	12	100.00
ALWAYS	263	12	12	100.00
ALWAYS	307	5	5	100.00
ALWAYS	316	5	5	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
194	1	1
195	1	1
219	1	1
222	1	1
223	1	1
225	1	1
229	1	1
230	1	1
233	1	1
234	1	1
			MISSING_ELSE
241	1	1
242	1	1
245	1	1
246	1	1
			MISSING_ELSE
263	1	1
266	1	1
267	1	1
269	1	1
273	1	1
274	1	1
277	1	1
278	1	1
			MISSING_ELSE
285	1	1
286	1	1
289	1	1
290	1	1
			MISSING_ELSE
307	1	1
308	1	1
309	1	1
311	1	1
312	1	1
316	1	1
317	1	1
318	1	1
320	1	1
321	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

	Total	Covered	Percent
Conditions	4	3	75.00
Logical	4	3	75.00
Non-Logical	0	0
Event	0	0

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
CASE	225	4	4	100.00
CASE	269	4	4	100.00
IF	307	2	2	100.00
IF	316	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	225	case (gen_nrz_hs_protocol.src_fsm_cs)
-2-:	233	if (gen_nrz_hs_protocol.src_handshake)
-3-:	245	if (gen_nrz_hs_protocol.src_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T1,T2,T4
EVEN	0	-	Covered	T1,T2,T4
ODD	-	1	Covered	T1,T2,T3
ODD	-	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	269	case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-:	277	if (gen_nrz_hs_protocol.dst_handshake)
-3-:	289	if (gen_nrz_hs_protocol.dst_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T1,T2,T4
EVEN	0	-	Covered	T1,T2,T4
ODD	-	1	Covered	T1,T2,T3
ODD	-	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	307	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	316	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb.gen_wr_req.u_dst_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	73828701	14639	0	0
SyncReqAckHoldReq	114657872	13864	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	73828701	14639	0	0
T1	29517	23	0	0
T2	389922	153	0	0
T3	293261	56	0	0
T4	7472	4	0	0
T11	0	265	0	0
T12	0	258	0	0
T13	0	22	0	0
T14	0	44	0	0
T15	0	39	0	0
T18	1536	0	0	0
T19	2058	0	0	0
T20	1375	0	0	0
T21	1243	0	0	0
T22	2170	0	0	0
T23	673	0	0	0
T33	0	14	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	114657872	13864	0	0
T1	59037	20	0	0
T2	384162	136	0	0
T3	142189	50	0	0
T4	14349	4	0	0
T11	0	259	0	0
T12	0	254	0	0
T13	0	20	0	0
T14	0	40	0	0
T15	0	38	0	0
T18	4609	0	0	0
T19	997	0	0	0
T20	2641	0	0	0
T21	2388	0	0	0
T22	1042	0	0	0
T23	1295	0	0	0
T33	0	14	0	0

Line Coverage for Instance : tb.dut.u_io_meas.u_err_sync

	Line No.	Total	Covered	Percent
TOTAL		36	36	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
ALWAYS	219	12	12	100.00
ALWAYS	263	12	12	100.00
ALWAYS	307	5	5	100.00
ALWAYS	316	5	5	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
194	1	1
195	1	1
219	1	1
222	1	1
223	1	1
225	1	1
229	1	1
230	1	1
233	1	1
234	1	1
			MISSING_ELSE
241	1	1
242	1	1
245	1	1
246	1	1
			MISSING_ELSE
263	1	1
266	1	1
267	1	1
269	1	1
273	1	1
274	1	1
277	1	1
278	1	1
			MISSING_ELSE
285	1	1
286	1	1
289	1	1
290	1	1
			MISSING_ELSE
307	1	1
308	1	1
309	1	1
311	1	1
312	1	1
316	1	1
317	1	1
318	1	1
320	1	1
321	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_io_meas.u_err_sync

	Total	Covered	Percent
Conditions	4	3	75.00
Logical	4	3	75.00
Non-Logical	0	0
Event	0	0

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T11
1	1	Covered	T2,T3,T11

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T3,T11

---

Branch Coverage for Instance : tb.dut.u_io_meas.u_err_sync

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
CASE	225	4	4	100.00
CASE	269	4	4	100.00
IF	307	2	2	100.00
IF	316	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	225	case (gen_nrz_hs_protocol.src_fsm_cs)
-2-:	233	if (gen_nrz_hs_protocol.src_handshake)
-3-:	245	if (gen_nrz_hs_protocol.src_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T2,T3,T11
EVEN	0	-	Covered	T2,T3,T11
ODD	-	1	Covered	T2,T3,T11
ODD	-	0	Covered	T2,T3,T11

	LineNo.	Expression
-1-:	269	case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-:	277	if (gen_nrz_hs_protocol.dst_handshake)
-3-:	289	if (gen_nrz_hs_protocol.dst_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T2,T3,T11
EVEN	0	-	Covered	T2,T3,T11
ODD	-	1	Covered	T2,T3,T11
ODD	-	0	Covered	T2,T3,T11

	LineNo.	Expression
-1-:	307	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	316	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_io_meas.u_err_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	72901641	1921	0	0
SyncReqAckHoldReq	221350909	1921	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	72901641	1921	0	0
T2	389922	31	0	0
T3	293261	14	0	0
T4	7472	0	0	0
T11	0	26	0	0
T12	0	38	0	0
T13	0	4	0	0
T14	0	21	0	0
T15	0	7	0	0
T16	0	3	0	0
T17	0	3	0	0
T19	2058	0	0	0
T20	1375	0	0	0
T21	1243	0	0	0
T22	2170	0	0	0
T23	673	0	0	0
T31	0	10	0	0
T32	1822	0	0	0
T35	1501	0	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	221350909	1921	0	0
T2	768287	31	0	0
T3	284364	14	0	0
T4	28697	0	0	0
T11	0	26	0	0
T12	0	38	0	0
T13	0	4	0	0
T14	0	21	0	0
T15	0	7	0	0
T16	0	3	0	0
T17	0	3	0	0
T19	1995	0	0	0
T20	5283	0	0	0
T21	4775	0	0	0
T22	2084	0	0	0
T23	2589	0	0	0
T31	0	10	0	0
T32	1822	0	0	0
T35	2939	0	0	0

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_err_sync

	Line No.	Total	Covered	Percent
TOTAL		36	36	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
ALWAYS	219	12	12	100.00
ALWAYS	263	12	12	100.00
ALWAYS	307	5	5	100.00
ALWAYS	316	5	5	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
194	1	1
195	1	1
219	1	1
222	1	1
223	1	1
225	1	1
229	1	1
230	1	1
233	1	1
234	1	1
			MISSING_ELSE
241	1	1
242	1	1
245	1	1
246	1	1
			MISSING_ELSE
263	1	1
266	1	1
267	1	1
269	1	1
273	1	1
274	1	1
277	1	1
278	1	1
			MISSING_ELSE
285	1	1
286	1	1
289	1	1
290	1	1
			MISSING_ELSE
307	1	1
308	1	1
309	1	1
311	1	1
312	1	1
316	1	1
317	1	1
318	1	1
320	1	1
321	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_err_sync

	Total	Covered	Percent
Conditions	4	3	75.00
Logical	4	3	75.00
Non-Logical	0	0
Event	0	0

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_err_sync

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
CASE	225	4	4	100.00
CASE	269	4	4	100.00
IF	307	2	2	100.00
IF	316	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	225	case (gen_nrz_hs_protocol.src_fsm_cs)
-2-:	233	if (gen_nrz_hs_protocol.src_handshake)
-3-:	245	if (gen_nrz_hs_protocol.src_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T1,T2,T3
EVEN	0	-	Covered	T1,T2,T3
ODD	-	1	Covered	T1,T2,T3
ODD	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	269	case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-:	277	if (gen_nrz_hs_protocol.dst_handshake)
-3-:	289	if (gen_nrz_hs_protocol.dst_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T1,T2,T3
EVEN	0	-	Covered	T1,T2,T3
ODD	-	1	Covered	T1,T2,T3
ODD	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	307	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	316	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_err_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	72901641	1671	0	0
SyncReqAckHoldReq	109955818	1671	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	72901641	1671	0	0
T1	29517	9	0	0
T2	389922	29	0	0
T3	293261	13	0	0
T4	7472	0	0	0
T11	0	46	0	0
T12	0	21	0	0
T13	0	8	0	0
T14	0	9	0	0
T16	0	3	0	0
T17	0	3	0	0
T18	1536	0	0	0
T19	2058	0	0	0
T20	1375	0	0	0
T21	1243	0	0	0
T22	2170	0	0	0
T23	673	0	0	0
T31	0	4	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	109955818	1671	0	0
T1	59023	9	0	0
T2	383768	29	0	0
T3	142179	13	0	0
T4	10237	0	0	0
T11	0	46	0	0
T12	0	21	0	0
T13	0	8	0	0
T14	0	9	0	0
T16	0	3	0	0
T17	0	3	0	0
T18	5099	0	0	0
T19	1078	0	0	0
T20	2575	0	0	0
T21	2702	0	0	0
T22	1162	0	0	0
T23	1268	0	0	0
T31	0	4	0	0

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_err_sync

	Line No.	Total	Covered	Percent
TOTAL		36	36	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
ALWAYS	219	12	12	100.00
ALWAYS	263	12	12	100.00
ALWAYS	307	5	5	100.00
ALWAYS	316	5	5	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
194	1	1
195	1	1
219	1	1
222	1	1
223	1	1
225	1	1
229	1	1
230	1	1
233	1	1
234	1	1
			MISSING_ELSE
241	1	1
242	1	1
245	1	1
246	1	1
			MISSING_ELSE
263	1	1
266	1	1
267	1	1
269	1	1
273	1	1
274	1	1
277	1	1
278	1	1
			MISSING_ELSE
285	1	1
286	1	1
289	1	1
290	1	1
			MISSING_ELSE
307	1	1
308	1	1
309	1	1
311	1	1
312	1	1
316	1	1
317	1	1
318	1	1
320	1	1
321	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_err_sync

	Total	Covered	Percent
Conditions	4	3	75.00
Logical	4	3	75.00
Non-Logical	0	0
Event	0	0

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T11
1	1	Covered	T1,T2,T11

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T11

---

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_err_sync

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
CASE	225	4	4	100.00
CASE	269	4	4	100.00
IF	307	2	2	100.00
IF	316	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	225	case (gen_nrz_hs_protocol.src_fsm_cs)
-2-:	233	if (gen_nrz_hs_protocol.src_handshake)
-3-:	245	if (gen_nrz_hs_protocol.src_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T1,T2,T11
EVEN	0	-	Covered	T1,T2,T11
ODD	-	1	Covered	T1,T2,T11
ODD	-	0	Covered	T1,T2,T11

	LineNo.	Expression
-1-:	269	case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-:	277	if (gen_nrz_hs_protocol.dst_handshake)
-3-:	289	if (gen_nrz_hs_protocol.dst_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T1,T2,T11
EVEN	0	-	Covered	T1,T2,T11
ODD	-	1	Covered	T1,T2,T11
ODD	-	0	Covered	T1,T2,T11

	LineNo.	Expression
-1-:	307	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	316	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_err_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	72901641	1693	0	0
SyncReqAckHoldReq	54977509	1693	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	72901641	1693	0	0
T1	29517	4	0	0
T2	389922	22	0	0
T3	293261	0	0	0
T4	7472	0	0	0
T11	0	22	0	0
T12	0	47	0	0
T13	0	5	0	0
T14	0	7	0	0
T15	0	7	0	0
T16	0	8	0	0
T18	1536	0	0	0
T19	2058	0	0	0
T20	1375	0	0	0
T21	1243	0	0	0
T22	2170	0	0	0
T23	673	0	0	0
T31	0	6	0	0
T34	0	7	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	54977509	1693	0	0
T1	29511	4	0	0
T2	191885	22	0	0
T3	71085	0	0	0
T4	5118	0	0	0
T11	0	22	0	0
T12	0	47	0	0
T13	0	5	0	0
T14	0	7	0	0
T15	0	7	0	0
T16	0	8	0	0
T18	2548	0	0	0
T19	538	0	0	0
T20	1287	0	0	0
T21	1351	0	0	0
T22	579	0	0	0
T23	634	0	0	0
T31	0	6	0	0
T34	0	7	0	0

Line Coverage for Instance : tb.dut.u_main_meas.u_err_sync

	Line No.	Total	Covered	Percent
TOTAL		36	36	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
ALWAYS	219	12	12	100.00
ALWAYS	263	12	12	100.00
ALWAYS	307	5	5	100.00
ALWAYS	316	5	5	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
194	1	1
195	1	1
219	1	1
222	1	1
223	1	1
225	1	1
229	1	1
230	1	1
233	1	1
234	1	1
			MISSING_ELSE
241	1	1
242	1	1
245	1	1
246	1	1
			MISSING_ELSE
263	1	1
266	1	1
267	1	1
269	1	1
273	1	1
274	1	1
277	1	1
278	1	1
			MISSING_ELSE
285	1	1
286	1	1
289	1	1
290	1	1
			MISSING_ELSE
307	1	1
308	1	1
309	1	1
311	1	1
312	1	1
316	1	1
317	1	1
318	1	1
320	1	1
321	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_main_meas.u_err_sync

	Total	Covered	Percent
Conditions	4	3	75.00
Logical	4	3	75.00
Non-Logical	0	0
Event	0	0

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_main_meas.u_err_sync

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
CASE	225	4	4	100.00
CASE	269	4	4	100.00
IF	307	2	2	100.00
IF	316	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	225	case (gen_nrz_hs_protocol.src_fsm_cs)
-2-:	233	if (gen_nrz_hs_protocol.src_handshake)
-3-:	245	if (gen_nrz_hs_protocol.src_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T1,T2,T3
EVEN	0	-	Covered	T1,T2,T3
ODD	-	1	Covered	T1,T2,T3
ODD	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	269	case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-:	277	if (gen_nrz_hs_protocol.dst_handshake)
-3-:	289	if (gen_nrz_hs_protocol.dst_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T1,T2,T3
EVEN	0	-	Covered	T1,T2,T3
ODD	-	1	Covered	T1,T2,T3
ODD	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	307	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	316	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_main_meas.u_err_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	72901641	1534	0	0
SyncReqAckHoldReq	236483738	1534	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	72901641	1534	0	0
T1	29517	7	0	0
T2	389922	18	0	0
T3	293261	10	0	0
T4	7472	0	0	0
T11	0	13	0	0
T12	0	28	0	0
T13	0	9	0	0
T14	0	4	0	0
T15	0	17	0	0
T16	0	3	0	0
T18	1536	0	0	0
T19	2058	0	0	0
T20	1375	0	0	0
T21	1243	0	0	0
T22	2170	0	0	0
T23	673	0	0	0
T31	0	4	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	236483738	1534	0	0
T1	122993	7	0	0
T2	812325	18	0	0
T3	296222	10	0	0
T4	29894	0	0	0
T11	0	13	0	0
T12	0	28	0	0
T13	0	9	0	0
T14	0	4	0	0
T15	0	17	0	0
T16	0	3	0	0
T18	9604	0	0	0
T19	2079	0	0	0
T20	5503	0	0	0
T21	4975	0	0	0
T22	2170	0	0	0
T23	2697	0	0	0
T31	0	4	0	0

Line Coverage for Instance : tb.dut.u_usb_meas.u_err_sync

	Line No.	Total	Covered	Percent
TOTAL		36	36	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	194	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
ALWAYS	219	12	12	100.00
ALWAYS	263	12	12	100.00
ALWAYS	307	5	5	100.00
ALWAYS	316	5	5	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
194	1	1
195	1	1
219	1	1
222	1	1
223	1	1
225	1	1
229	1	1
230	1	1
233	1	1
234	1	1
			MISSING_ELSE
241	1	1
242	1	1
245	1	1
246	1	1
			MISSING_ELSE
263	1	1
266	1	1
267	1	1
269	1	1
273	1	1
274	1	1
277	1	1
278	1	1
			MISSING_ELSE
285	1	1
286	1	1
289	1	1
290	1	1
			MISSING_ELSE
307	1	1
308	1	1
309	1	1
311	1	1
312	1	1
316	1	1
317	1	1
318	1	1
320	1	1
321	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_usb_meas.u_err_sync

	Total	Covered	Percent
Conditions	4	3	75.00
Logical	4	3	75.00
Non-Logical	0	0
Event	0	0

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T11
1	1	Covered	T2,T3,T11

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Covered	T2,T3,T11

---

Branch Coverage for Instance : tb.dut.u_usb_meas.u_err_sync

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
CASE	225	4	4	100.00
CASE	269	4	4	100.00
IF	307	2	2	100.00
IF	316	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	225	case (gen_nrz_hs_protocol.src_fsm_cs)
-2-:	233	if (gen_nrz_hs_protocol.src_handshake)
-3-:	245	if (gen_nrz_hs_protocol.src_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T2,T3,T11
EVEN	0	-	Covered	T2,T3,T11
ODD	-	1	Covered	T2,T3,T11
ODD	-	0	Covered	T2,T3,T11

	LineNo.	Expression
-1-:	269	case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-:	277	if (gen_nrz_hs_protocol.dst_handshake)
-3-:	289	if (gen_nrz_hs_protocol.dst_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Covered	T2,T3,T11
EVEN	0	-	Covered	T2,T3,T11
ODD	-	1	Covered	T2,T3,T11
ODD	-	0	Covered	T2,T3,T11

	LineNo.	Expression
-1-:	307	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	316	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_usb_meas.u_err_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	72901641	1580	0	0
SyncReqAckHoldReq	113377980	1580	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	72901641	1580	0	0
T2	389922	25	0	0
T3	293261	11	0	0
T4	7472	0	0	0
T11	0	32	0	0
T12	0	45	0	0
T13	0	3	0	0
T14	0	4	0	0
T15	0	4	0	0
T16	0	10	0	0
T19	2058	0	0	0
T20	1375	0	0	0
T21	1243	0	0	0
T22	2170	0	0	0
T23	673	0	0	0
T31	0	7	0	0
T32	1822	0	0	0
T34	0	4	0	0
T35	1501	0	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	113377980	1580	0	0
T2	384162	25	0	0
T3	142189	11	0	0
T4	14349	0	0	0
T11	0	32	0	0
T12	0	45	0	0
T13	0	3	0	0
T14	0	4	0	0
T15	0	4	0	0
T16	0	10	0	0
T19	997	0	0	0
T20	2641	0	0	0
T21	2388	0	0	0
T22	1042	0	0	0
T23	1295	0	0	0
T31	0	7	0	0
T32	911	0	0	0
T34	0	4	0	0
T35	1470	0	0	0