Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	72901641	11170118	0	55

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	72901641	11170118	0	55
T1	29517	9823	0	1
T2	389922	101106	0	1
T3	293261	73020	0	0
T4	7472	0	0	0
T11	0	557184	0	0
T12	0	67558	0	0
T13	0	7451	0	1
T14	0	47232	0	1
T15	0	7947	0	0
T16	0	7578	0	1
T17	0	2551	0	1
T18	1536	0	0	0
T19	2058	0	0	0
T20	1375	0	0	0
T21	1243	0	0	0
T22	2170	0	0	0
T23	673	0	0	0
T31	0	0	0	1
T34	0	0	0	1
T115	0	0	0	1
T116	0	0	0	1