Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	73828701	1923993	0	0
clk_enables_rd_A	73828701	20754	0	0
clk_hints_rd_A	73828701	18513	0	0
extclk_ctrl_rd_A	73828701	22858	0	0
extclk_ctrl_regwen_rd_A	73828701	16569	0	0
jitter_enable_rd_A	73828701	27863	0	0
jitter_regwen_rd_A	73828701	18252	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73828701	1923993	0	0
T11	160441	45537	0	0
T12	836038	28458	0	0
T13	31909	0	0	0
T41	0	105981	0	0
T68	0	62557	0	0
T69	0	51251	0	0
T70	0	238906	0	0
T71	0	76308	0	0
T72	0	52217	0	0
T73	0	77560	0	0
T74	0	59843	0	0
T75	2271	0	0	0
T76	2126	0	0	0
T77	1664	0	0	0
T78	1687	0	0	0
T79	1691	0	0	0
T80	1901	0	0	0
T81	1919	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73828701	20754	0	0
T1	29517	0	0	0
T2	389922	0	0	0
T4	7472	0	0	0
T11	0	1736	0	0
T18	1536	0	0	0
T19	2058	0	0	0
T20	1375	0	0	0
T21	1243	0	0	0
T22	2170	0	0	0
T30	2138	2	0	0
T41	0	3961	0	0
T67	693	0	0	0
T68	0	2471	0	0
T78	0	5	0	0
T138	0	2	0	0
T139	0	1	0	0
T140	0	4	0	0
T141	0	7	0	0
T142	0	5	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73828701	18513	0	0
T1	29517	0	0	0
T2	389922	0	0	0
T4	7472	0	0	0
T11	0	1581	0	0
T18	1536	0	0	0
T19	2058	0	0	0
T20	1375	0	0	0
T21	1243	0	0	0
T22	2170	0	0	0
T30	2138	4	0	0
T41	0	3320	0	0
T67	693	0	0	0
T68	0	2284	0	0
T78	0	4	0	0
T138	0	4	0	0
T139	0	5	0	0
T140	0	15	0	0
T141	0	6	0	0
T143	0	8	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73828701	22858	0	0
T5	1098	8	0	0
T6	1153	0	0	0
T7	1037	0	0	0
T11	0	1969	0	0
T21	0	24	0	0
T22	0	64	0	0
T24	1153	0	0	0
T25	1050	0	0	0
T26	2371	0	0	0
T27	1354	0	0	0
T28	1437	15	0	0
T29	2423	0	0	0
T30	2138	0	0	0
T41	0	4402	0	0
T79	0	39	0	0
T144	0	55	0	0
T145	0	31	0	0
T146	0	3	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73828701	16569	0	0
T11	160441	1533	0	0
T12	836038	0	0	0
T13	31909	0	0	0
T41	0	3508	0	0
T68	0	2123	0	0
T72	0	1639	0	0
T75	2271	0	0	0
T76	2126	0	0	0
T77	1664	0	0	0
T78	1687	0	0	0
T79	1691	0	0	0
T80	1901	0	0	0
T81	1919	0	0	0
T147	0	16	0	0
T148	0	8	0	0
T149	0	9	0	0
T150	0	25	0	0
T151	0	23	0	0
T152	0	3634	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73828701	27863	0	0
T1	29517	0	0	0
T2	389922	0	0	0
T4	7472	0	0	0
T11	0	2278	0	0
T18	1536	0	0	0
T19	2058	0	0	0
T20	1375	0	0	0
T21	1243	0	0	0
T22	2170	0	0	0
T30	2138	76	0	0
T41	0	4662	0	0
T67	693	0	0	0
T68	0	3983	0	0
T78	0	51	0	0
T138	0	101	0	0
T139	0	127	0	0
T140	0	122	0	0
T141	0	78	0	0
T143	0	89	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73828701	18252	0	0
T11	160441	1480	0	0
T12	836038	0	0	0
T13	31909	0	0	0
T41	0	3640	0	0
T56	0	137	0	0
T58	0	37	0	0
T68	0	2256	0	0
T72	0	1983	0	0
T75	2271	0	0	0
T76	2126	0	0	0
T77	1664	0	0	0
T78	1687	0	0	0
T79	1691	0	0	0
T80	1901	0	0	0
T81	1919	0	0	0
T95	0	43	0	0
T152	0	4220	0	0
T153	0	2047	0	0
T154	0	200	0	0