SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.clkmgr_div2_sva_if | 100.00 | 100.00 | 100.00 | 100.00 | |||
tb.dut.clkmgr_div4_sva_if | 100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.65 | 100.00 | 93.24 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.65 | 100.00 | 93.24 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T5,T6,T25 |
1 | 0 | Covered | T26,T27,T28 |
1 | 1 | Covered | T5,T26,T27 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div2.Div2Stepped_A | 221351331 | 2879 | 0 | 0 |
g_div2.Div2Whole_A | 221351331 | 3347 | 0 | 0 |
g_div4.Div4Stepped_A | 109956206 | 2826 | 0 | 0 |
g_div4.Div4Whole_A | 109956206 | 3194 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 221351331 | 2879 | 0 | 0 |
T3 | 0 | 18 | 0 | 0 |
T5 | 4221 | 2 | 0 | 0 |
T6 | 4262 | 0 | 0 | 0 |
T7 | 5787 | 0 | 0 | 0 |
T18 | 0 | 8 | 0 | 0 |
T19 | 0 | 10 | 0 | 0 |
T21 | 0 | 4 | 0 | 0 |
T22 | 0 | 6 | 0 | 0 |
T24 | 4100 | 0 | 0 | 0 |
T25 | 4205 | 0 | 0 | 0 |
T26 | 2277 | 10 | 0 | 0 |
T27 | 5421 | 2 | 0 | 0 |
T28 | 1422 | 0 | 0 | 0 |
T29 | 3324 | 10 | 0 | 0 |
T30 | 2073 | 0 | 0 | 0 |
T35 | 0 | 10 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 221351331 | 3347 | 0 | 0 |
T3 | 0 | 26 | 0 | 0 |
T5 | 4221 | 2 | 0 | 0 |
T6 | 4262 | 0 | 0 | 0 |
T7 | 5787 | 0 | 0 | 0 |
T18 | 0 | 8 | 0 | 0 |
T19 | 0 | 11 | 0 | 0 |
T21 | 0 | 4 | 0 | 0 |
T22 | 0 | 7 | 0 | 0 |
T24 | 4100 | 0 | 0 | 0 |
T25 | 4205 | 0 | 0 | 0 |
T26 | 2277 | 9 | 0 | 0 |
T27 | 5421 | 3 | 0 | 0 |
T28 | 1422 | 0 | 0 | 0 |
T29 | 3324 | 11 | 0 | 0 |
T30 | 2073 | 0 | 0 | 0 |
T35 | 0 | 10 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 109956206 | 2826 | 0 | 0 |
T3 | 0 | 16 | 0 | 0 |
T5 | 2185 | 2 | 0 | 0 |
T6 | 2091 | 0 | 0 | 0 |
T7 | 2833 | 0 | 0 | 0 |
T18 | 0 | 8 | 0 | 0 |
T19 | 0 | 8 | 0 | 0 |
T21 | 0 | 4 | 0 | 0 |
T22 | 0 | 6 | 0 | 0 |
T24 | 2011 | 0 | 0 | 0 |
T25 | 2049 | 0 | 0 | 0 |
T26 | 1291 | 9 | 0 | 0 |
T27 | 2793 | 2 | 0 | 0 |
T28 | 699 | 0 | 0 | 0 |
T29 | 1827 | 10 | 0 | 0 |
T30 | 983 | 0 | 0 | 0 |
T35 | 0 | 10 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 109956206 | 3194 | 0 | 0 |
T3 | 0 | 21 | 0 | 0 |
T5 | 2185 | 2 | 0 | 0 |
T6 | 2091 | 0 | 0 | 0 |
T7 | 2833 | 0 | 0 | 0 |
T18 | 0 | 8 | 0 | 0 |
T19 | 0 | 7 | 0 | 0 |
T21 | 0 | 4 | 0 | 0 |
T22 | 0 | 7 | 0 | 0 |
T24 | 2011 | 0 | 0 | 0 |
T25 | 2049 | 0 | 0 | 0 |
T26 | 1291 | 8 | 0 | 0 |
T27 | 2793 | 3 | 0 | 0 |
T28 | 699 | 0 | 0 | 0 |
T29 | 1827 | 11 | 0 | 0 |
T30 | 983 | 0 | 0 | 0 |
T35 | 0 | 8 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T5,T6,T25 |
1 | 0 | Covered | T26,T27,T28 |
1 | 1 | Covered | T5,T26,T27 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div2.Div2Stepped_A | 221351331 | 2879 | 0 | 0 |
g_div2.Div2Whole_A | 221351331 | 3347 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 221351331 | 2879 | 0 | 0 |
T3 | 0 | 18 | 0 | 0 |
T5 | 4221 | 2 | 0 | 0 |
T6 | 4262 | 0 | 0 | 0 |
T7 | 5787 | 0 | 0 | 0 |
T18 | 0 | 8 | 0 | 0 |
T19 | 0 | 10 | 0 | 0 |
T21 | 0 | 4 | 0 | 0 |
T22 | 0 | 6 | 0 | 0 |
T24 | 4100 | 0 | 0 | 0 |
T25 | 4205 | 0 | 0 | 0 |
T26 | 2277 | 10 | 0 | 0 |
T27 | 5421 | 2 | 0 | 0 |
T28 | 1422 | 0 | 0 | 0 |
T29 | 3324 | 10 | 0 | 0 |
T30 | 2073 | 0 | 0 | 0 |
T35 | 0 | 10 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 221351331 | 3347 | 0 | 0 |
T3 | 0 | 26 | 0 | 0 |
T5 | 4221 | 2 | 0 | 0 |
T6 | 4262 | 0 | 0 | 0 |
T7 | 5787 | 0 | 0 | 0 |
T18 | 0 | 8 | 0 | 0 |
T19 | 0 | 11 | 0 | 0 |
T21 | 0 | 4 | 0 | 0 |
T22 | 0 | 7 | 0 | 0 |
T24 | 4100 | 0 | 0 | 0 |
T25 | 4205 | 0 | 0 | 0 |
T26 | 2277 | 9 | 0 | 0 |
T27 | 5421 | 3 | 0 | 0 |
T28 | 1422 | 0 | 0 | 0 |
T29 | 3324 | 11 | 0 | 0 |
T30 | 2073 | 0 | 0 | 0 |
T35 | 0 | 10 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T5,T6,T25 |
1 | 0 | Covered | T26,T27,T28 |
1 | 1 | Covered | T5,T26,T27 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div4.Div4Stepped_A | 109956206 | 2826 | 0 | 0 |
g_div4.Div4Whole_A | 109956206 | 3194 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 109956206 | 2826 | 0 | 0 |
T3 | 0 | 16 | 0 | 0 |
T5 | 2185 | 2 | 0 | 0 |
T6 | 2091 | 0 | 0 | 0 |
T7 | 2833 | 0 | 0 | 0 |
T18 | 0 | 8 | 0 | 0 |
T19 | 0 | 8 | 0 | 0 |
T21 | 0 | 4 | 0 | 0 |
T22 | 0 | 6 | 0 | 0 |
T24 | 2011 | 0 | 0 | 0 |
T25 | 2049 | 0 | 0 | 0 |
T26 | 1291 | 9 | 0 | 0 |
T27 | 2793 | 2 | 0 | 0 |
T28 | 699 | 0 | 0 | 0 |
T29 | 1827 | 10 | 0 | 0 |
T30 | 983 | 0 | 0 | 0 |
T35 | 0 | 10 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 109956206 | 3194 | 0 | 0 |
T3 | 0 | 21 | 0 | 0 |
T5 | 2185 | 2 | 0 | 0 |
T6 | 2091 | 0 | 0 | 0 |
T7 | 2833 | 0 | 0 | 0 |
T18 | 0 | 8 | 0 | 0 |
T19 | 0 | 7 | 0 | 0 |
T21 | 0 | 4 | 0 | 0 |
T22 | 0 | 7 | 0 | 0 |
T24 | 2011 | 0 | 0 | 0 |
T25 | 2049 | 0 | 0 | 0 |
T26 | 1291 | 8 | 0 | 0 |
T27 | 2793 | 3 | 0 | 0 |
T28 | 699 | 0 | 0 | 0 |
T29 | 1827 | 11 | 0 | 0 |
T30 | 983 | 0 | 0 | 0 |
T35 | 0 | 8 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |